2 * Low-Level PCI Support for the SH7780
4 * Dustin McIntire (dustin@sensoria.com)
5 * Derived from arch/i386/kernel/pci-*.c which bore the message:
6 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org>
9 * With cleanup by Paul van Gool <pvangool@mimotech.com>
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
18 #include <linux/config.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23 #include <linux/sched.h>
24 #include <linux/ioport.h>
25 #include <linux/errno.h>
26 #include <linux/irq.h>
27 #include <linux/delay.h>
29 #include <asm/machvec.h>
31 #include "pci-sh7780.h"
33 static unsigned int pci_probe = PCI_PROBE_CONF1;
34 extern int pci_fixup_pcic(void);
37 * Direct access to PCI hardware...
40 #define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
43 * Functions for accessing PCI configuration space with type 1 accesses
45 static int sh7780_pci_read(struct pci_bus *bus, unsigned int devfn,
46 int where, int size, u32 *val)
52 * PCIPDR may only be accessed as 32 bit words,
53 * so we must do byte alignment by hand
55 local_irq_save(flags);
56 outl(CONFIG_CMD(bus, devfn, where), PCI_REG(SH7780_PCIPAR));
57 data = inl(PCI_REG(SH7780_PCIPDR));
58 local_irq_restore(flags);
62 *val = (data >> ((where & 3) << 3)) & 0xff;
65 *val = (data >> ((where & 2) << 3)) & 0xffff;
71 return PCIBIOS_FUNC_NOT_SUPPORTED;
74 return PCIBIOS_SUCCESSFUL;
78 * Since SH7780 only does 32bit access we'll have to do a read,
79 * mask,write operation.
80 * We'll allow an odd byte offset, though it should be illegal.
82 static int sh7780_pci_write(struct pci_bus *bus, unsigned int devfn,
83 int where, int size, u32 val)
89 local_irq_save(flags);
90 outl(CONFIG_CMD(bus, devfn, where), PCI_REG(SH7780_PCIPAR));
91 data = inl(PCI_REG(SH7780_PCIPDR));
92 local_irq_restore(flags);
96 shift = (where & 3) << 3;
97 data &= ~(0xff << shift);
98 data |= ((val & 0xff) << shift);
101 shift = (where & 2) << 3;
102 data &= ~(0xffff << shift);
103 data |= ((val & 0xffff) << shift);
109 return PCIBIOS_FUNC_NOT_SUPPORTED;
112 outl(data, PCI_REG(SH7780_PCIPDR));
114 return PCIBIOS_SUCCESSFUL;
119 struct pci_ops sh7780_pci_ops = {
120 .read = sh7780_pci_read,
121 .write = sh7780_pci_write,
124 static int __init pci_check_direct(void)
126 unsigned int tmp, id;
128 outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
130 /* check for SH7780/SH7780R hardware */
131 id = inl(PCI_REG(SH7780_PCIVID));
132 if ((id != ((SH7780_DEVICE_ID << 16) | SH7780_VENDOR_ID)) &&
133 (id != ((SH7781_DEVICE_ID << 16) | SH7780_VENDOR_ID))) {
134 printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id);
139 * Check if configuration works.
141 if (pci_probe & PCI_PROBE_CONF1) {
142 tmp = inl(PCI_REG(SH7780_PCIPAR));
143 outl(0x80000000, PCI_REG(SH7780_PCIPAR));
144 if (inl(PCI_REG(SH7780_PCIPAR)) == 0x80000000) {
145 outl(tmp, PCI_REG(SH7780_PCIPAR));
146 printk(KERN_INFO "PCI: Using configuration type 1\n");
147 request_region(PCI_REG(SH7780_PCIPAR), 8, "PCI conf1");
150 outl(tmp, PCI_REG(SH7780_PCIPAR));
153 pr_debug("PCI: pci_check_direct failed\n");
157 /***************************************************************************************/
160 * Handle bus scanning and fixups ....
163 static void __init pci_fixup_ide_bases(struct pci_dev *d)
168 * PCI IDE controllers use non-standard I/O port decoding, respect it.
170 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
172 pr_debug("PCI: IDE base address fixup for %s\n", pci_name(d));
174 struct resource *r = &d->resource[i];
175 if ((r->start & ~0x80) == 0x374) {
182 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
185 * Called after each bus is probed, but before its children
189 void __init pcibios_fixup_bus(struct pci_bus *b)
191 pci_read_bridge_bases(b);
195 * Initialization. Try all known PCI access methods. Note that we support
196 * using both PCI BIOS and direct access: in such cases, we use I/O ports
197 * to access config space.
199 * Note that the platform specific initialization (BSC registers, and memory
200 * space mapping) will be called via the machine vectors (sh_mv.mv_pci_init()) if it
201 * exists and via the platform defined function pcibios_init_platform().
202 * See pci_bigsur.c for implementation;
204 * The BIOS version of the pci functions is not yet implemented but it is left
205 * in for completeness. Currently an error will be genereated at compile time.
208 static int __init sh7780_pci_init(void)
212 pr_debug("PCI: Starting intialization.\n");
215 ctrl_outl(0x00200000, INTC_ICR0); /* INTC SH-4 Mode */
216 ctrl_outl(0x00078000, INTC_INT2MSKCR); /* enable PCIINTA - PCIINTD */
217 ctrl_outl(0x40000000, INTC_INTMSK1); /* disable IRL4-7 Interrupt */
218 ctrl_outl(0x0000fffe, INTC_INTMSK2); /* disable IRL4-7 Interrupt */
219 ctrl_outl(0x80000000, INTC_INTMSKCLR1); /* enable IRL0-3 Interrupt */
220 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); /* enable IRL0-3 Interrupt */
222 if ((ret = pci_check_direct()) != 0)
225 return pcibios_init_platform();
228 core_initcall(sh7780_pci_init);
230 int __init sh7780_pcic_init(struct sh7780_pci_address_map *map)
235 * This code is unused for some boards as it is done in the
236 * bootloader and doing it here means the MAC addresses loaded
237 * by the bootloader get lost.
239 if (!(map->flags & SH7780_PCIC_NO_RESET)) {
240 /* toggle PCI reset pin */
241 word = SH7780_PCICR_PREFIX | SH7780_PCICR_PRST;
242 outl(word,PCI_REG(SH7780_PCICR));
243 /* Wait for a long time... not 1 sec. but long enough */
245 word = SH7780_PCICR_PREFIX;
246 outl(word,PCI_REG(SH7780_PCICR));
249 /* set the command/status bits to:
250 * Wait Cycle Control + Parity Enable + Bus Master +
253 outl(0x00000046, PCI_REG(SH7780_PCICMD));
255 /* define this host as the host bridge */
256 word = SH7780_PCI_HOST_BRIDGE << 24;
257 outl(word, PCI_REG(SH7780_PCIRID));
259 /* Set IO and Mem windows to local address
260 * Make PCI and local address the same for easy 1 to 1 mapping
261 * Window0 = map->window0.size @ non-cached area base = SDRAM
262 * Window1 = map->window1.size @ cached area base = SDRAM
264 word = ((map->window0.size - 1) & 0x1ff00001) | 0x01;
265 outl(0x07f00001, PCI_REG(SH7780_PCILSR0));
266 word = ((map->window1.size - 1) & 0x1ff00001) | 0x01;
267 outl(0x00000001, PCI_REG(SH7780_PCILSR1));
268 /* Set the values on window 0 PCI config registers */
269 word = P2SEGADDR(map->window0.base);
270 outl(0xa8000000, PCI_REG(SH7780_PCILAR0));
271 outl(0x08000000, PCI_REG(SH7780_PCIMBAR0));
272 /* Set the values on window 1 PCI config registers */
273 word = P2SEGADDR(map->window1.base);
274 outl(0x00000000, PCI_REG(SH7780_PCILAR1));
275 outl(0x00000000, PCI_REG(SH7780_PCIMBAR1));
277 /* Map IO space into PCI IO window
278 * The IO window is 64K-PCIBIOS_MIN_IO in size
279 * IO addresses will be translated to the
280 * PCI IO window base address
282 PCIDBG(3,"PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", PCIBIOS_MIN_IO,
283 (64*1024), SH7780_PCI_IO_BASE+PCIBIOS_MIN_IO);
285 /* NOTE: I'm ignoring the PCI error IRQs for now..
286 * TODO: add support for the internal error interrupts and
290 #ifdef CONFIG_SH_R7780RP
294 /* SH7780 init done, set central function init complete */
295 /* use round robin mode to stop a device starving/overruning */
296 word = SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | /* SH7780_PCICR_ARBM |*/ SH7780_PCICR_FTO;
297 outl(word, PCI_REG(SH7780_PCICR));
302 char * __init pcibios_setup(char *str)
304 if (!strcmp(str, "off")) {
315 static u8 __init sh7780_no_swizzle(struct pci_dev *dev, u8 *pin)
318 return PCI_SLOT(dev->devfn);
321 static int sh7780_pci_lookup_irq(struct pci_dev *dev, u8 slot, u8 pin)
325 /* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */
326 irq = pcibios_map_platform_irq(slot,pin);
328 pr_debug("PCI: Error mapping IRQ on device %s\n", pci_name(dev));
332 pr_debug("Setting IRQ for slot %s to %d\n", pci_name(dev), irq);
337 void __init pcibios_fixup_irqs(void)
339 pci_fixup_irqs(sh7780_no_swizzle, sh7780_pci_lookup_irq);