2 * arch/powerpc/kernel/mpic.c
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
31 #include <asm/ptrace.h>
32 #include <asm/signal.h>
34 #include <asm/pgtable.h>
36 #include <asm/machdep.h>
43 #define DBG(fmt...) printk(fmt)
48 static struct mpic *mpics;
49 static struct mpic *mpic_primary;
50 static DEFINE_RAW_SPINLOCK(mpic_lock);
52 #ifdef CONFIG_PPC32 /* XXX for now */
53 #ifdef CONFIG_IRQ_ALL_CPUS
54 #define distribute_irqs (1)
56 #define distribute_irqs (0)
60 #ifdef CONFIG_MPIC_WEIRD
61 static u32 mpic_infos[][MPIC_IDX_END] = {
62 [0] = { /* Original OpenPIC compatible MPIC */
65 MPIC_GREG_GLOBAL_CONF_0,
67 MPIC_GREG_IPI_VECTOR_PRI_0,
74 MPIC_TIMER_CURRENT_CNT,
76 MPIC_TIMER_VECTOR_PRI,
77 MPIC_TIMER_DESTINATION,
81 MPIC_CPU_IPI_DISPATCH_0,
82 MPIC_CPU_IPI_DISPATCH_STRIDE,
83 MPIC_CPU_CURRENT_TASK_PRI,
92 MPIC_VECPRI_VECTOR_MASK,
93 MPIC_VECPRI_POLARITY_POSITIVE,
94 MPIC_VECPRI_POLARITY_NEGATIVE,
95 MPIC_VECPRI_SENSE_LEVEL,
96 MPIC_VECPRI_SENSE_EDGE,
97 MPIC_VECPRI_POLARITY_MASK,
98 MPIC_VECPRI_SENSE_MASK,
101 [1] = { /* Tsi108/109 PIC */
103 TSI108_GREG_FEATURE_0,
104 TSI108_GREG_GLOBAL_CONF_0,
105 TSI108_GREG_VENDOR_ID,
106 TSI108_GREG_IPI_VECTOR_PRI_0,
107 TSI108_GREG_IPI_STRIDE,
108 TSI108_GREG_SPURIOUS,
109 TSI108_GREG_TIMER_FREQ,
113 TSI108_TIMER_CURRENT_CNT,
114 TSI108_TIMER_BASE_CNT,
115 TSI108_TIMER_VECTOR_PRI,
116 TSI108_TIMER_DESTINATION,
120 TSI108_CPU_IPI_DISPATCH_0,
121 TSI108_CPU_IPI_DISPATCH_STRIDE,
122 TSI108_CPU_CURRENT_TASK_PRI,
130 TSI108_IRQ_VECTOR_PRI,
131 TSI108_VECPRI_VECTOR_MASK,
132 TSI108_VECPRI_POLARITY_POSITIVE,
133 TSI108_VECPRI_POLARITY_NEGATIVE,
134 TSI108_VECPRI_SENSE_LEVEL,
135 TSI108_VECPRI_SENSE_EDGE,
136 TSI108_VECPRI_POLARITY_MASK,
137 TSI108_VECPRI_SENSE_MASK,
138 TSI108_IRQ_DESTINATION
142 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
144 #else /* CONFIG_MPIC_WEIRD */
146 #define MPIC_INFO(name) MPIC_##name
148 #endif /* CONFIG_MPIC_WEIRD */
150 static inline unsigned int mpic_processor_id(struct mpic *mpic)
152 unsigned int cpu = 0;
154 if (mpic->flags & MPIC_PRIMARY)
155 cpu = hard_smp_processor_id();
161 * Register accessor functions
165 static inline u32 _mpic_read(enum mpic_reg_type type,
166 struct mpic_reg_bank *rb,
170 #ifdef CONFIG_PPC_DCR
171 case mpic_access_dcr:
172 return dcr_read(rb->dhost, reg);
174 case mpic_access_mmio_be:
175 return in_be32(rb->base + (reg >> 2));
176 case mpic_access_mmio_le:
178 return in_le32(rb->base + (reg >> 2));
182 static inline void _mpic_write(enum mpic_reg_type type,
183 struct mpic_reg_bank *rb,
184 unsigned int reg, u32 value)
187 #ifdef CONFIG_PPC_DCR
188 case mpic_access_dcr:
189 dcr_write(rb->dhost, reg, value);
192 case mpic_access_mmio_be:
193 out_be32(rb->base + (reg >> 2), value);
195 case mpic_access_mmio_le:
197 out_le32(rb->base + (reg >> 2), value);
202 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
204 enum mpic_reg_type type = mpic->reg_type;
205 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
206 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
208 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
209 type = mpic_access_mmio_be;
210 return _mpic_read(type, &mpic->gregs, offset);
213 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
215 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
216 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
218 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
221 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
223 unsigned int cpu = mpic_processor_id(mpic);
225 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
228 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
230 unsigned int cpu = mpic_processor_id(mpic);
232 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
235 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
237 unsigned int isu = src_no >> mpic->isu_shift;
238 unsigned int idx = src_no & mpic->isu_mask;
241 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
242 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
243 #ifdef CONFIG_MPIC_BROKEN_REGREAD
245 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
246 mpic->isu_reg0_shadow[src_no];
251 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
252 unsigned int reg, u32 value)
254 unsigned int isu = src_no >> mpic->isu_shift;
255 unsigned int idx = src_no & mpic->isu_mask;
257 _mpic_write(mpic->reg_type, &mpic->isus[isu],
258 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
260 #ifdef CONFIG_MPIC_BROKEN_REGREAD
262 mpic->isu_reg0_shadow[src_no] =
263 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
267 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
268 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
269 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
270 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
271 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
272 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
273 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
274 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
278 * Low level utility functions
282 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
283 struct mpic_reg_bank *rb, unsigned int offset,
286 rb->base = ioremap(phys_addr + offset, size);
287 BUG_ON(rb->base == NULL);
290 #ifdef CONFIG_PPC_DCR
291 static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
292 struct mpic_reg_bank *rb,
293 unsigned int offset, unsigned int size)
297 dbasep = of_get_property(node, "dcr-reg", NULL);
299 rb->dhost = dcr_map(node, *dbasep + offset, size);
300 BUG_ON(!DCR_MAP_OK(rb->dhost));
303 static inline void mpic_map(struct mpic *mpic, struct device_node *node,
304 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
305 unsigned int offset, unsigned int size)
307 if (mpic->flags & MPIC_USES_DCR)
308 _mpic_map_dcr(mpic, node, rb, offset, size);
310 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
312 #else /* CONFIG_PPC_DCR */
313 #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
314 #endif /* !CONFIG_PPC_DCR */
318 /* Check if we have one of those nice broken MPICs with a flipped endian on
319 * reads from IPI registers
321 static void __init mpic_test_broken_ipi(struct mpic *mpic)
325 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
326 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
328 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
329 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
330 mpic->flags |= MPIC_BROKEN_IPI;
334 #ifdef CONFIG_MPIC_U3_HT_IRQS
336 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
337 * to force the edge setting on the MPIC and do the ack workaround.
339 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
341 if (source >= 128 || !mpic->fixups)
343 return mpic->fixups[source].base != NULL;
347 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
349 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
351 if (fixup->applebase) {
352 unsigned int soff = (fixup->index >> 3) & ~3;
353 unsigned int mask = 1U << (fixup->index & 0x1f);
354 writel(mask, fixup->applebase + soff);
356 raw_spin_lock(&mpic->fixup_lock);
357 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
358 writel(fixup->data, fixup->base + 4);
359 raw_spin_unlock(&mpic->fixup_lock);
363 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
366 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
370 if (fixup->base == NULL)
373 DBG("startup_ht_interrupt(0x%x) index: %d\n",
374 source, fixup->index);
375 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
376 /* Enable and configure */
377 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
378 tmp = readl(fixup->base + 4);
382 writel(tmp, fixup->base + 4);
383 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
386 /* use the lowest bit inverted to the actual HW,
387 * set if this fixup was enabled, clear otherwise */
388 mpic->save_data[source].fixup_data = tmp | 1;
392 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
394 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
398 if (fixup->base == NULL)
401 DBG("shutdown_ht_interrupt(0x%x)\n", source);
404 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
405 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
406 tmp = readl(fixup->base + 4);
408 writel(tmp, fixup->base + 4);
409 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
412 /* use the lowest bit inverted to the actual HW,
413 * set if this fixup was enabled, clear otherwise */
414 mpic->save_data[source].fixup_data = tmp & ~1;
418 #ifdef CONFIG_PCI_MSI
419 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
426 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
427 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
428 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
429 if (id == PCI_CAP_ID_HT) {
430 id = readb(devbase + pos + 3);
431 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
439 base = devbase + pos;
441 flags = readb(base + HT_MSI_FLAGS);
442 if (!(flags & HT_MSI_FLAGS_FIXED)) {
443 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
444 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
447 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
448 PCI_SLOT(devfn), PCI_FUNC(devfn),
449 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
451 if (!(flags & HT_MSI_FLAGS_ENABLE))
452 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
455 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
462 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
463 unsigned int devfn, u32 vdid)
470 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
471 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
472 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
473 if (id == PCI_CAP_ID_HT) {
474 id = readb(devbase + pos + 3);
475 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
482 base = devbase + pos;
483 writeb(0x01, base + 2);
484 n = (readl(base + 4) >> 16) & 0xff;
486 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
488 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
490 for (i = 0; i <= n; i++) {
491 writeb(0x10 + 2 * i, base + 2);
492 tmp = readl(base + 4);
493 irq = (tmp >> 16) & 0xff;
494 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
495 /* mask it , will be unmasked later */
497 writel(tmp, base + 4);
498 mpic->fixups[irq].index = i;
499 mpic->fixups[irq].base = base;
500 /* Apple HT PIC has a non-standard way of doing EOIs */
501 if ((vdid & 0xffff) == 0x106b)
502 mpic->fixups[irq].applebase = devbase + 0x60;
504 mpic->fixups[irq].applebase = NULL;
505 writeb(0x11 + 2 * i, base + 2);
506 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
511 static void __init mpic_scan_ht_pics(struct mpic *mpic)
514 u8 __iomem *cfgspace;
516 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
518 /* Allocate fixups array */
519 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
520 BUG_ON(mpic->fixups == NULL);
523 raw_spin_lock_init(&mpic->fixup_lock);
525 /* Map U3 config space. We assume all IO-APICs are on the primary bus
526 * so we only need to map 64kB.
528 cfgspace = ioremap(0xf2000000, 0x10000);
529 BUG_ON(cfgspace == NULL);
531 /* Now we scan all slots. We do a very quick scan, we read the header
532 * type, vendor ID and device ID only, that's plenty enough
534 for (devfn = 0; devfn < 0x100; devfn++) {
535 u8 __iomem *devbase = cfgspace + (devfn << 8);
536 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
537 u32 l = readl(devbase + PCI_VENDOR_ID);
540 DBG("devfn %x, l: %x\n", devfn, l);
542 /* If no device, skip */
543 if (l == 0xffffffff || l == 0x00000000 ||
544 l == 0x0000ffff || l == 0xffff0000)
546 /* Check if is supports capability lists */
547 s = readw(devbase + PCI_STATUS);
548 if (!(s & PCI_STATUS_CAP_LIST))
551 mpic_scan_ht_pic(mpic, devbase, devfn, l);
552 mpic_scan_ht_msi(mpic, devbase, devfn);
555 /* next device, if function 0 */
556 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
561 #else /* CONFIG_MPIC_U3_HT_IRQS */
563 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
568 static void __init mpic_scan_ht_pics(struct mpic *mpic)
572 #endif /* CONFIG_MPIC_U3_HT_IRQS */
575 static int irq_choose_cpu(const struct cpumask *mask)
579 if (cpumask_equal(mask, cpu_all_mask)) {
580 static int irq_rover = 0;
581 static DEFINE_RAW_SPINLOCK(irq_rover_lock);
584 /* Round-robin distribution... */
586 raw_spin_lock_irqsave(&irq_rover_lock, flags);
588 irq_rover = cpumask_next(irq_rover, cpu_online_mask);
589 if (irq_rover >= nr_cpu_ids)
590 irq_rover = cpumask_first(cpu_online_mask);
594 raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
596 cpuid = cpumask_first_and(mask, cpu_online_mask);
597 if (cpuid >= nr_cpu_ids)
601 return get_hard_smp_processor_id(cpuid);
604 static int irq_choose_cpu(const struct cpumask *mask)
606 return hard_smp_processor_id();
610 /* Find an mpic associated with a given linux interrupt */
611 static struct mpic *mpic_find(unsigned int irq)
613 if (irq < NUM_ISA_INTERRUPTS)
616 return irq_get_chip_data(irq);
619 /* Determine if the linux irq is an IPI */
620 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
622 unsigned int src = virq_to_hw(irq);
624 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
628 /* Convert a cpu mask from logical to physical cpu numbers. */
629 static inline u32 mpic_physmask(u32 cpumask)
634 for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
635 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
640 /* Get the mpic structure from the IPI number */
641 static inline struct mpic * mpic_from_ipi(struct irq_data *d)
643 return irq_data_get_irq_chip_data(d);
647 /* Get the mpic structure from the irq number */
648 static inline struct mpic * mpic_from_irq(unsigned int irq)
650 return irq_get_chip_data(irq);
653 /* Get the mpic structure from the irq data */
654 static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
656 return irq_data_get_irq_chip_data(d);
660 static inline void mpic_eoi(struct mpic *mpic)
662 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
663 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
667 * Linux descriptor level callbacks
671 void mpic_unmask_irq(struct irq_data *d)
673 unsigned int loops = 100000;
674 struct mpic *mpic = mpic_from_irq_data(d);
675 unsigned int src = irqd_to_hwirq(d);
677 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
679 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
680 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
682 /* make sure mask gets to controller before we return to user */
685 printk(KERN_ERR "%s: timeout on hwirq %u\n",
689 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
692 void mpic_mask_irq(struct irq_data *d)
694 unsigned int loops = 100000;
695 struct mpic *mpic = mpic_from_irq_data(d);
696 unsigned int src = irqd_to_hwirq(d);
698 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
700 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
701 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
704 /* make sure mask gets to controller before we return to user */
707 printk(KERN_ERR "%s: timeout on hwirq %u\n",
711 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
714 void mpic_end_irq(struct irq_data *d)
716 struct mpic *mpic = mpic_from_irq_data(d);
719 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
721 /* We always EOI on end_irq() even for edge interrupts since that
722 * should only lower the priority, the MPIC should have properly
723 * latched another edge interrupt coming in anyway
729 #ifdef CONFIG_MPIC_U3_HT_IRQS
731 static void mpic_unmask_ht_irq(struct irq_data *d)
733 struct mpic *mpic = mpic_from_irq_data(d);
734 unsigned int src = irqd_to_hwirq(d);
738 if (irqd_is_level_type(d))
739 mpic_ht_end_irq(mpic, src);
742 static unsigned int mpic_startup_ht_irq(struct irq_data *d)
744 struct mpic *mpic = mpic_from_irq_data(d);
745 unsigned int src = irqd_to_hwirq(d);
748 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
753 static void mpic_shutdown_ht_irq(struct irq_data *d)
755 struct mpic *mpic = mpic_from_irq_data(d);
756 unsigned int src = irqd_to_hwirq(d);
758 mpic_shutdown_ht_interrupt(mpic, src);
762 static void mpic_end_ht_irq(struct irq_data *d)
764 struct mpic *mpic = mpic_from_irq_data(d);
765 unsigned int src = irqd_to_hwirq(d);
768 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
770 /* We always EOI on end_irq() even for edge interrupts since that
771 * should only lower the priority, the MPIC should have properly
772 * latched another edge interrupt coming in anyway
775 if (irqd_is_level_type(d))
776 mpic_ht_end_irq(mpic, src);
779 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
783 static void mpic_unmask_ipi(struct irq_data *d)
785 struct mpic *mpic = mpic_from_ipi(d);
786 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
788 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
789 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
792 static void mpic_mask_ipi(struct irq_data *d)
794 /* NEVER disable an IPI... that's just plain wrong! */
797 static void mpic_end_ipi(struct irq_data *d)
799 struct mpic *mpic = mpic_from_ipi(d);
802 * IPIs are marked IRQ_PER_CPU. This has the side effect of
803 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
804 * applying to them. We EOI them late to avoid re-entering.
805 * We mark IPI's with IRQF_DISABLED as they must run with
811 #endif /* CONFIG_SMP */
813 int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
816 struct mpic *mpic = mpic_from_irq_data(d);
817 unsigned int src = irqd_to_hwirq(d);
819 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
820 int cpuid = irq_choose_cpu(cpumask);
822 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
824 u32 mask = cpumask_bits(cpumask)[0];
826 mask &= cpumask_bits(cpu_online_mask)[0];
828 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
829 mpic_physmask(mask));
835 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
837 /* Now convert sense value */
838 switch(type & IRQ_TYPE_SENSE_MASK) {
839 case IRQ_TYPE_EDGE_RISING:
840 return MPIC_INFO(VECPRI_SENSE_EDGE) |
841 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
842 case IRQ_TYPE_EDGE_FALLING:
843 case IRQ_TYPE_EDGE_BOTH:
844 return MPIC_INFO(VECPRI_SENSE_EDGE) |
845 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
846 case IRQ_TYPE_LEVEL_HIGH:
847 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
848 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
849 case IRQ_TYPE_LEVEL_LOW:
851 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
852 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
856 int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
858 struct mpic *mpic = mpic_from_irq_data(d);
859 unsigned int src = irqd_to_hwirq(d);
860 unsigned int vecpri, vold, vnew;
862 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
863 mpic, d->irq, src, flow_type);
865 if (src >= mpic->irq_count)
868 if (flow_type == IRQ_TYPE_NONE)
869 if (mpic->senses && src < mpic->senses_count)
870 flow_type = mpic->senses[src];
871 if (flow_type == IRQ_TYPE_NONE)
872 flow_type = IRQ_TYPE_LEVEL_LOW;
874 irqd_set_trigger_type(d, flow_type);
876 if (mpic_is_ht_interrupt(mpic, src))
877 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
878 MPIC_VECPRI_SENSE_EDGE;
880 vecpri = mpic_type_to_vecpri(mpic, flow_type);
882 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
883 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
884 MPIC_INFO(VECPRI_SENSE_MASK));
887 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
889 return IRQ_SET_MASK_OK_NOCOPY;;
892 void mpic_set_vector(unsigned int virq, unsigned int vector)
894 struct mpic *mpic = mpic_from_irq(virq);
895 unsigned int src = virq_to_hw(virq);
898 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
899 mpic, virq, src, vector);
901 if (src >= mpic->irq_count)
904 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
905 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
907 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
910 void mpic_set_destination(unsigned int virq, unsigned int cpuid)
912 struct mpic *mpic = mpic_from_irq(virq);
913 unsigned int src = virq_to_hw(virq);
915 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
916 mpic, virq, src, cpuid);
918 if (src >= mpic->irq_count)
921 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
924 static struct irq_chip mpic_irq_chip = {
925 .irq_mask = mpic_mask_irq,
926 .irq_unmask = mpic_unmask_irq,
927 .irq_eoi = mpic_end_irq,
928 .irq_set_type = mpic_set_irq_type,
932 static struct irq_chip mpic_ipi_chip = {
933 .irq_mask = mpic_mask_ipi,
934 .irq_unmask = mpic_unmask_ipi,
935 .irq_eoi = mpic_end_ipi,
937 #endif /* CONFIG_SMP */
939 #ifdef CONFIG_MPIC_U3_HT_IRQS
940 static struct irq_chip mpic_irq_ht_chip = {
941 .irq_startup = mpic_startup_ht_irq,
942 .irq_shutdown = mpic_shutdown_ht_irq,
943 .irq_mask = mpic_mask_irq,
944 .irq_unmask = mpic_unmask_ht_irq,
945 .irq_eoi = mpic_end_ht_irq,
946 .irq_set_type = mpic_set_irq_type,
948 #endif /* CONFIG_MPIC_U3_HT_IRQS */
951 static int mpic_host_match(struct irq_host *h, struct device_node *node)
953 /* Exact match, unless mpic node is NULL */
954 return h->of_node == NULL || h->of_node == node;
957 static int mpic_host_map(struct irq_host *h, unsigned int virq,
960 struct mpic *mpic = h->host_data;
961 struct irq_chip *chip;
963 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
965 if (hw == mpic->spurious_vec)
967 if (mpic->protected && test_bit(hw, mpic->protected))
971 else if (hw >= mpic->ipi_vecs[0]) {
972 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
974 DBG("mpic: mapping as IPI\n");
975 irq_set_chip_data(virq, mpic);
976 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
980 #endif /* CONFIG_SMP */
982 if (hw >= mpic->irq_count)
985 mpic_msi_reserve_hwirq(mpic, hw);
988 chip = &mpic->hc_irq;
990 #ifdef CONFIG_MPIC_U3_HT_IRQS
991 /* Check for HT interrupts, override vecpri */
992 if (mpic_is_ht_interrupt(mpic, hw))
993 chip = &mpic->hc_ht_irq;
994 #endif /* CONFIG_MPIC_U3_HT_IRQS */
996 DBG("mpic: mapping to irq chip @%p\n", chip);
998 irq_set_chip_data(virq, mpic);
999 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1001 /* Set default irq type */
1002 irq_set_irq_type(virq, IRQ_TYPE_NONE);
1004 /* If the MPIC was reset, then all vectors have already been
1005 * initialized. Otherwise, a per source lazy initialization
1008 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1009 mpic_set_vector(virq, hw);
1010 mpic_set_destination(virq, mpic_processor_id(mpic));
1011 mpic_irq_set_priority(virq, 8);
1017 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1018 const u32 *intspec, unsigned int intsize,
1019 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1022 static unsigned char map_mpic_senses[4] = {
1023 IRQ_TYPE_EDGE_RISING,
1025 IRQ_TYPE_LEVEL_HIGH,
1026 IRQ_TYPE_EDGE_FALLING,
1029 *out_hwirq = intspec[0];
1033 /* Apple invented a new race of encoding on machines with
1034 * an HT APIC. They encode, among others, the index within
1035 * the HT APIC. We don't care about it here since thankfully,
1036 * it appears that they have the APIC already properly
1037 * configured, and thus our current fixup code that reads the
1038 * APIC config works fine. However, we still need to mask out
1039 * bits in the specifier to make sure we only get bit 0 which
1040 * is the level/edge bit (the only sense bit exposed by Apple),
1041 * as their bit 1 means something else.
1043 if (machine_is(powermac))
1045 *out_flags = map_mpic_senses[intspec[1] & mask];
1047 *out_flags = IRQ_TYPE_NONE;
1049 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1050 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1055 static struct irq_host_ops mpic_host_ops = {
1056 .match = mpic_host_match,
1057 .map = mpic_host_map,
1058 .xlate = mpic_host_xlate,
1061 static int mpic_reset_prohibited(struct device_node *node)
1063 return node && of_get_property(node, "pic-no-reset", NULL);
1067 * Exported functions
1070 struct mpic * __init mpic_alloc(struct device_node *node,
1071 phys_addr_t phys_addr,
1073 unsigned int isu_size,
1074 unsigned int irq_count,
1082 u64 paddr = phys_addr;
1084 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1090 mpic->hc_irq = mpic_irq_chip;
1091 mpic->hc_irq.name = name;
1092 if (flags & MPIC_PRIMARY)
1093 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1094 #ifdef CONFIG_MPIC_U3_HT_IRQS
1095 mpic->hc_ht_irq = mpic_irq_ht_chip;
1096 mpic->hc_ht_irq.name = name;
1097 if (flags & MPIC_PRIMARY)
1098 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1099 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1102 mpic->hc_ipi = mpic_ipi_chip;
1103 mpic->hc_ipi.name = name;
1104 #endif /* CONFIG_SMP */
1106 mpic->flags = flags;
1107 mpic->isu_size = isu_size;
1108 mpic->irq_count = irq_count;
1109 mpic->num_sources = 0; /* so far */
1111 if (flags & MPIC_LARGE_VECTORS)
1116 mpic->timer_vecs[0] = intvec_top - 8;
1117 mpic->timer_vecs[1] = intvec_top - 7;
1118 mpic->timer_vecs[2] = intvec_top - 6;
1119 mpic->timer_vecs[3] = intvec_top - 5;
1120 mpic->ipi_vecs[0] = intvec_top - 4;
1121 mpic->ipi_vecs[1] = intvec_top - 3;
1122 mpic->ipi_vecs[2] = intvec_top - 2;
1123 mpic->ipi_vecs[3] = intvec_top - 1;
1124 mpic->spurious_vec = intvec_top;
1126 /* Check for "big-endian" in device-tree */
1127 if (node && of_get_property(node, "big-endian", NULL) != NULL)
1128 mpic->flags |= MPIC_BIG_ENDIAN;
1130 /* Look for protected sources */
1133 unsigned int bits, mapsize;
1135 of_get_property(node, "protected-sources", &psize);
1138 bits = intvec_top + 1;
1139 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1140 mpic->protected = kzalloc(mapsize, GFP_KERNEL);
1141 BUG_ON(mpic->protected == NULL);
1142 for (i = 0; i < psize; i++) {
1143 if (psrc[i] > intvec_top)
1145 __set_bit(psrc[i], mpic->protected);
1150 #ifdef CONFIG_MPIC_WEIRD
1151 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1154 /* default register type */
1155 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1156 mpic_access_mmio_be : mpic_access_mmio_le;
1158 /* If no physical address is passed in, a device-node is mandatory */
1159 BUG_ON(paddr == 0 && node == NULL);
1161 /* If no physical address passed in, check if it's dcr based */
1162 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1163 #ifdef CONFIG_PPC_DCR
1164 mpic->flags |= MPIC_USES_DCR;
1165 mpic->reg_type = mpic_access_dcr;
1168 #endif /* CONFIG_PPC_DCR */
1171 /* If the MPIC is not DCR based, and no physical address was passed
1172 * in, try to obtain one
1174 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1175 const u32 *reg = of_get_property(node, "reg", NULL);
1176 BUG_ON(reg == NULL);
1177 paddr = of_translate_address(node, reg);
1178 BUG_ON(paddr == OF_BAD_ADDR);
1181 /* Map the global registers */
1182 mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1183 mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1187 /* When using a device-node, reset requests are only honored if the MPIC
1188 * is allowed to reset.
1190 if (mpic_reset_prohibited(node))
1191 mpic->flags |= MPIC_NO_RESET;
1193 if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
1194 printk(KERN_DEBUG "mpic: Resetting\n");
1195 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1196 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1197 | MPIC_GREG_GCONF_RESET);
1198 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1199 & MPIC_GREG_GCONF_RESET)
1204 if (flags & MPIC_ENABLE_COREINT)
1205 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1206 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1207 | MPIC_GREG_GCONF_COREINT);
1209 if (flags & MPIC_ENABLE_MCK)
1210 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1211 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1212 | MPIC_GREG_GCONF_MCK);
1214 /* Read feature register, calculate num CPUs and, for non-ISU
1215 * MPICs, num sources as well. On ISU MPICs, sources are counted
1218 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1219 mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1220 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1221 if (isu_size == 0) {
1222 if (flags & MPIC_BROKEN_FRR_NIRQS)
1223 mpic->num_sources = mpic->irq_count;
1226 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1227 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1230 /* Map the per-CPU registers */
1231 for (i = 0; i < mpic->num_cpus; i++) {
1232 mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
1233 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1237 /* Initialize main ISU if none provided */
1238 if (mpic->isu_size == 0) {
1239 mpic->isu_size = mpic->num_sources;
1240 mpic_map(mpic, node, paddr, &mpic->isus[0],
1241 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1243 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1244 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1246 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
1247 isu_size ? isu_size : mpic->num_sources,
1249 flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1250 if (mpic->irqhost == NULL)
1253 mpic->irqhost->host_data = mpic;
1255 /* Display version */
1256 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1270 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1272 name, vers, (unsigned long long)paddr, mpic->num_cpus);
1273 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1274 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1279 if (flags & MPIC_PRIMARY) {
1280 mpic_primary = mpic;
1281 irq_set_default_host(mpic->irqhost);
1287 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1290 unsigned int isu_first = isu_num * mpic->isu_size;
1292 BUG_ON(isu_num >= MPIC_MAX_ISU);
1294 mpic_map(mpic, mpic->irqhost->of_node,
1295 paddr, &mpic->isus[isu_num], 0,
1296 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1298 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1299 mpic->num_sources = isu_first + mpic->isu_size;
1302 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1304 mpic->senses = senses;
1305 mpic->senses_count = count;
1308 void __init mpic_init(struct mpic *mpic)
1313 BUG_ON(mpic->num_sources == 0);
1315 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1317 /* Set current processor priority to max */
1318 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1320 /* Initialize timers: just disable them all */
1321 for (i = 0; i < 4; i++) {
1322 mpic_write(mpic->tmregs,
1323 i * MPIC_INFO(TIMER_STRIDE) +
1324 MPIC_INFO(TIMER_DESTINATION), 0);
1325 mpic_write(mpic->tmregs,
1326 i * MPIC_INFO(TIMER_STRIDE) +
1327 MPIC_INFO(TIMER_VECTOR_PRI),
1329 (mpic->timer_vecs[0] + i));
1332 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1333 mpic_test_broken_ipi(mpic);
1334 for (i = 0; i < 4; i++) {
1337 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1338 (mpic->ipi_vecs[0] + i));
1341 /* Initialize interrupt sources */
1342 if (mpic->irq_count == 0)
1343 mpic->irq_count = mpic->num_sources;
1345 /* Do the HT PIC fixups on U3 broken mpic */
1346 DBG("MPIC flags: %x\n", mpic->flags);
1347 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1348 mpic_scan_ht_pics(mpic);
1349 mpic_u3msi_init(mpic);
1352 mpic_pasemi_msi_init(mpic);
1354 cpu = mpic_processor_id(mpic);
1356 if (!(mpic->flags & MPIC_NO_RESET)) {
1357 for (i = 0; i < mpic->num_sources; i++) {
1358 /* start with vector = source number, and masked */
1359 u32 vecpri = MPIC_VECPRI_MASK | i |
1360 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1362 /* check if protected */
1363 if (mpic->protected && test_bit(i, mpic->protected))
1366 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1367 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1371 /* Init spurious vector */
1372 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1374 /* Disable 8259 passthrough, if supported */
1375 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1376 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1377 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1378 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1380 if (mpic->flags & MPIC_NO_BIAS)
1381 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1382 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1383 | MPIC_GREG_GCONF_NO_BIAS);
1385 /* Set current processor priority to 0 */
1386 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1389 /* allocate memory to save mpic state */
1390 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1392 BUG_ON(mpic->save_data == NULL);
1396 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1400 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1401 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1402 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1403 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1406 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1408 unsigned long flags;
1411 raw_spin_lock_irqsave(&mpic_lock, flags);
1412 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1414 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1416 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1417 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1418 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1421 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1423 struct mpic *mpic = mpic_find(irq);
1424 unsigned int src = virq_to_hw(irq);
1425 unsigned long flags;
1431 raw_spin_lock_irqsave(&mpic_lock, flags);
1432 if (mpic_is_ipi(mpic, irq)) {
1433 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1434 ~MPIC_VECPRI_PRIORITY_MASK;
1435 mpic_ipi_write(src - mpic->ipi_vecs[0],
1436 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1438 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1439 & ~MPIC_VECPRI_PRIORITY_MASK;
1440 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1441 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1443 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1446 void mpic_setup_this_cpu(void)
1449 struct mpic *mpic = mpic_primary;
1450 unsigned long flags;
1451 u32 msk = 1 << hard_smp_processor_id();
1454 BUG_ON(mpic == NULL);
1456 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1458 raw_spin_lock_irqsave(&mpic_lock, flags);
1460 /* let the mpic know we want intrs. default affinity is 0xffffffff
1461 * until changed via /proc. That's how it's done on x86. If we want
1462 * it differently, then we should make sure we also change the default
1463 * values of irq_desc[].affinity in irq.c.
1465 if (distribute_irqs) {
1466 for (i = 0; i < mpic->num_sources ; i++)
1467 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1468 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1471 /* Set current processor priority to 0 */
1472 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1474 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1475 #endif /* CONFIG_SMP */
1478 int mpic_cpu_get_priority(void)
1480 struct mpic *mpic = mpic_primary;
1482 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1485 void mpic_cpu_set_priority(int prio)
1487 struct mpic *mpic = mpic_primary;
1489 prio &= MPIC_CPU_TASKPRI_MASK;
1490 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1493 void mpic_teardown_this_cpu(int secondary)
1495 struct mpic *mpic = mpic_primary;
1496 unsigned long flags;
1497 u32 msk = 1 << hard_smp_processor_id();
1500 BUG_ON(mpic == NULL);
1502 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1503 raw_spin_lock_irqsave(&mpic_lock, flags);
1505 /* let the mpic know we don't want intrs. */
1506 for (i = 0; i < mpic->num_sources ; i++)
1507 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1508 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1510 /* Set current processor priority to max */
1511 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1512 /* We need to EOI the IPI since not all platforms reset the MPIC
1513 * on boot and new interrupts wouldn't get delivered otherwise.
1517 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1521 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1525 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1527 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1529 if (unlikely(src == mpic->spurious_vec)) {
1530 if (mpic->flags & MPIC_SPV_EOI)
1534 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1535 if (printk_ratelimit())
1536 printk(KERN_WARNING "%s: Got protected source %d !\n",
1537 mpic->name, (int)src);
1542 return irq_linear_revmap(mpic->irqhost, src);
1545 unsigned int mpic_get_one_irq(struct mpic *mpic)
1547 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1550 unsigned int mpic_get_irq(void)
1552 struct mpic *mpic = mpic_primary;
1554 BUG_ON(mpic == NULL);
1556 return mpic_get_one_irq(mpic);
1559 unsigned int mpic_get_coreint_irq(void)
1562 struct mpic *mpic = mpic_primary;
1565 BUG_ON(mpic == NULL);
1567 src = mfspr(SPRN_EPR);
1569 if (unlikely(src == mpic->spurious_vec)) {
1570 if (mpic->flags & MPIC_SPV_EOI)
1574 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1575 if (printk_ratelimit())
1576 printk(KERN_WARNING "%s: Got protected source %d !\n",
1577 mpic->name, (int)src);
1581 return irq_linear_revmap(mpic->irqhost, src);
1587 unsigned int mpic_get_mcirq(void)
1589 struct mpic *mpic = mpic_primary;
1591 BUG_ON(mpic == NULL);
1593 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1597 void mpic_request_ipis(void)
1599 struct mpic *mpic = mpic_primary;
1601 BUG_ON(mpic == NULL);
1603 printk(KERN_INFO "mpic: requesting IPIs...\n");
1605 for (i = 0; i < 4; i++) {
1606 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1607 mpic->ipi_vecs[0] + i);
1608 if (vipi == NO_IRQ) {
1609 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1612 smp_request_message_ipi(vipi, i);
1616 static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask)
1618 struct mpic *mpic = mpic_primary;
1620 BUG_ON(mpic == NULL);
1623 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1626 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1627 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1628 mpic_physmask(cpumask_bits(cpu_mask)[0]));
1631 void smp_mpic_message_pass(int target, int msg)
1635 /* make sure we're sending something that translates to an IPI */
1636 if ((unsigned int)msg > 3) {
1637 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1638 smp_processor_id(), msg);
1643 mpic_send_ipi(msg, cpu_online_mask);
1645 case MSG_ALL_BUT_SELF:
1646 alloc_cpumask_var(&tmp, GFP_NOWAIT);
1647 cpumask_andnot(tmp, cpu_online_mask,
1648 cpumask_of(smp_processor_id()));
1649 mpic_send_ipi(msg, tmp);
1650 free_cpumask_var(tmp);
1653 mpic_send_ipi(msg, cpumask_of(target));
1658 int __init smp_mpic_probe(void)
1662 DBG("smp_mpic_probe()...\n");
1664 nr_cpus = cpumask_weight(cpu_possible_mask);
1666 DBG("nr_cpus: %d\n", nr_cpus);
1669 mpic_request_ipis();
1674 void __devinit smp_mpic_setup_cpu(int cpu)
1676 mpic_setup_this_cpu();
1679 void mpic_reset_core(int cpu)
1681 struct mpic *mpic = mpic_primary;
1683 int cpuid = get_hard_smp_processor_id(cpu);
1685 /* Set target bit for core reset */
1686 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1687 pir |= (1 << cpuid);
1688 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1689 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1691 /* Restore target bit after reset complete */
1692 pir &= ~(1 << cpuid);
1693 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1694 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1696 #endif /* CONFIG_SMP */
1699 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1701 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1704 for (i = 0; i < mpic->num_sources; i++) {
1705 mpic->save_data[i].vecprio =
1706 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1707 mpic->save_data[i].dest =
1708 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1714 static int mpic_resume(struct sys_device *dev)
1716 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1719 for (i = 0; i < mpic->num_sources; i++) {
1720 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1721 mpic->save_data[i].vecprio);
1722 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1723 mpic->save_data[i].dest);
1725 #ifdef CONFIG_MPIC_U3_HT_IRQS
1727 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1730 /* we use the lowest bit in an inverted meaning */
1731 if ((mpic->save_data[i].fixup_data & 1) == 0)
1734 /* Enable and configure */
1735 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1737 writel(mpic->save_data[i].fixup_data & ~1,
1742 } /* end for loop */
1748 static struct sysdev_class mpic_sysclass = {
1750 .resume = mpic_resume,
1751 .suspend = mpic_suspend,
1756 static int mpic_init_sys(void)
1758 struct mpic *mpic = mpics;
1761 error = sysdev_class_register(&mpic_sysclass);
1763 while (mpic && !error) {
1764 mpic->sysdev.cls = &mpic_sysclass;
1765 mpic->sysdev.id = id++;
1766 error = sysdev_register(&mpic->sysdev);
1772 device_initcall(mpic_init_sys);