2 * arch/powerpc/kernel/mpic.c
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
31 #include <asm/ptrace.h>
32 #include <asm/signal.h>
34 #include <asm/pgtable.h>
36 #include <asm/machdep.h>
43 #define DBG(fmt...) printk(fmt)
48 static struct mpic *mpics;
49 static struct mpic *mpic_primary;
50 static DEFINE_RAW_SPINLOCK(mpic_lock);
52 #ifdef CONFIG_PPC32 /* XXX for now */
53 #ifdef CONFIG_IRQ_ALL_CPUS
54 #define distribute_irqs (1)
56 #define distribute_irqs (0)
60 #ifdef CONFIG_MPIC_WEIRD
61 static u32 mpic_infos[][MPIC_IDX_END] = {
62 [0] = { /* Original OpenPIC compatible MPIC */
65 MPIC_GREG_GLOBAL_CONF_0,
67 MPIC_GREG_IPI_VECTOR_PRI_0,
74 MPIC_TIMER_CURRENT_CNT,
76 MPIC_TIMER_VECTOR_PRI,
77 MPIC_TIMER_DESTINATION,
81 MPIC_CPU_IPI_DISPATCH_0,
82 MPIC_CPU_IPI_DISPATCH_STRIDE,
83 MPIC_CPU_CURRENT_TASK_PRI,
92 MPIC_VECPRI_VECTOR_MASK,
93 MPIC_VECPRI_POLARITY_POSITIVE,
94 MPIC_VECPRI_POLARITY_NEGATIVE,
95 MPIC_VECPRI_SENSE_LEVEL,
96 MPIC_VECPRI_SENSE_EDGE,
97 MPIC_VECPRI_POLARITY_MASK,
98 MPIC_VECPRI_SENSE_MASK,
101 [1] = { /* Tsi108/109 PIC */
103 TSI108_GREG_FEATURE_0,
104 TSI108_GREG_GLOBAL_CONF_0,
105 TSI108_GREG_VENDOR_ID,
106 TSI108_GREG_IPI_VECTOR_PRI_0,
107 TSI108_GREG_IPI_STRIDE,
108 TSI108_GREG_SPURIOUS,
109 TSI108_GREG_TIMER_FREQ,
113 TSI108_TIMER_CURRENT_CNT,
114 TSI108_TIMER_BASE_CNT,
115 TSI108_TIMER_VECTOR_PRI,
116 TSI108_TIMER_DESTINATION,
120 TSI108_CPU_IPI_DISPATCH_0,
121 TSI108_CPU_IPI_DISPATCH_STRIDE,
122 TSI108_CPU_CURRENT_TASK_PRI,
130 TSI108_IRQ_VECTOR_PRI,
131 TSI108_VECPRI_VECTOR_MASK,
132 TSI108_VECPRI_POLARITY_POSITIVE,
133 TSI108_VECPRI_POLARITY_NEGATIVE,
134 TSI108_VECPRI_SENSE_LEVEL,
135 TSI108_VECPRI_SENSE_EDGE,
136 TSI108_VECPRI_POLARITY_MASK,
137 TSI108_VECPRI_SENSE_MASK,
138 TSI108_IRQ_DESTINATION
142 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
144 #else /* CONFIG_MPIC_WEIRD */
146 #define MPIC_INFO(name) MPIC_##name
148 #endif /* CONFIG_MPIC_WEIRD */
150 static inline unsigned int mpic_processor_id(struct mpic *mpic)
152 unsigned int cpu = 0;
154 if (mpic->flags & MPIC_PRIMARY)
155 cpu = hard_smp_processor_id();
161 * Register accessor functions
165 static inline u32 _mpic_read(enum mpic_reg_type type,
166 struct mpic_reg_bank *rb,
170 #ifdef CONFIG_PPC_DCR
171 case mpic_access_dcr:
172 return dcr_read(rb->dhost, reg);
174 case mpic_access_mmio_be:
175 return in_be32(rb->base + (reg >> 2));
176 case mpic_access_mmio_le:
178 return in_le32(rb->base + (reg >> 2));
182 static inline void _mpic_write(enum mpic_reg_type type,
183 struct mpic_reg_bank *rb,
184 unsigned int reg, u32 value)
187 #ifdef CONFIG_PPC_DCR
188 case mpic_access_dcr:
189 dcr_write(rb->dhost, reg, value);
192 case mpic_access_mmio_be:
193 out_be32(rb->base + (reg >> 2), value);
195 case mpic_access_mmio_le:
197 out_le32(rb->base + (reg >> 2), value);
202 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
204 enum mpic_reg_type type = mpic->reg_type;
205 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
206 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
208 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
209 type = mpic_access_mmio_be;
210 return _mpic_read(type, &mpic->gregs, offset);
213 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
215 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
216 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
218 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
221 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
223 unsigned int cpu = mpic_processor_id(mpic);
225 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
228 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
230 unsigned int cpu = mpic_processor_id(mpic);
232 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
235 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
237 unsigned int isu = src_no >> mpic->isu_shift;
238 unsigned int idx = src_no & mpic->isu_mask;
241 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
242 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
243 #ifdef CONFIG_MPIC_BROKEN_REGREAD
245 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
246 mpic->isu_reg0_shadow[src_no];
251 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
252 unsigned int reg, u32 value)
254 unsigned int isu = src_no >> mpic->isu_shift;
255 unsigned int idx = src_no & mpic->isu_mask;
257 _mpic_write(mpic->reg_type, &mpic->isus[isu],
258 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
260 #ifdef CONFIG_MPIC_BROKEN_REGREAD
262 mpic->isu_reg0_shadow[src_no] =
263 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
267 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
268 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
269 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
270 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
271 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
272 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
273 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
274 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
278 * Low level utility functions
282 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
283 struct mpic_reg_bank *rb, unsigned int offset,
286 rb->base = ioremap(phys_addr + offset, size);
287 BUG_ON(rb->base == NULL);
290 #ifdef CONFIG_PPC_DCR
291 static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
292 struct mpic_reg_bank *rb,
293 unsigned int offset, unsigned int size)
297 dbasep = of_get_property(node, "dcr-reg", NULL);
299 rb->dhost = dcr_map(node, *dbasep + offset, size);
300 BUG_ON(!DCR_MAP_OK(rb->dhost));
303 static inline void mpic_map(struct mpic *mpic, struct device_node *node,
304 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
305 unsigned int offset, unsigned int size)
307 if (mpic->flags & MPIC_USES_DCR)
308 _mpic_map_dcr(mpic, node, rb, offset, size);
310 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
312 #else /* CONFIG_PPC_DCR */
313 #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
314 #endif /* !CONFIG_PPC_DCR */
318 /* Check if we have one of those nice broken MPICs with a flipped endian on
319 * reads from IPI registers
321 static void __init mpic_test_broken_ipi(struct mpic *mpic)
325 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
326 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
328 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
329 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
330 mpic->flags |= MPIC_BROKEN_IPI;
334 #ifdef CONFIG_MPIC_U3_HT_IRQS
336 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
337 * to force the edge setting on the MPIC and do the ack workaround.
339 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
341 if (source >= 128 || !mpic->fixups)
343 return mpic->fixups[source].base != NULL;
347 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
349 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
351 if (fixup->applebase) {
352 unsigned int soff = (fixup->index >> 3) & ~3;
353 unsigned int mask = 1U << (fixup->index & 0x1f);
354 writel(mask, fixup->applebase + soff);
356 raw_spin_lock(&mpic->fixup_lock);
357 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
358 writel(fixup->data, fixup->base + 4);
359 raw_spin_unlock(&mpic->fixup_lock);
363 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
366 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
370 if (fixup->base == NULL)
373 DBG("startup_ht_interrupt(0x%x) index: %d\n",
374 source, fixup->index);
375 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
376 /* Enable and configure */
377 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
378 tmp = readl(fixup->base + 4);
382 writel(tmp, fixup->base + 4);
383 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
386 /* use the lowest bit inverted to the actual HW,
387 * set if this fixup was enabled, clear otherwise */
388 mpic->save_data[source].fixup_data = tmp | 1;
392 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
394 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
398 if (fixup->base == NULL)
401 DBG("shutdown_ht_interrupt(0x%x)\n", source);
404 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
405 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
406 tmp = readl(fixup->base + 4);
408 writel(tmp, fixup->base + 4);
409 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
412 /* use the lowest bit inverted to the actual HW,
413 * set if this fixup was enabled, clear otherwise */
414 mpic->save_data[source].fixup_data = tmp & ~1;
418 #ifdef CONFIG_PCI_MSI
419 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
426 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
427 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
428 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
429 if (id == PCI_CAP_ID_HT) {
430 id = readb(devbase + pos + 3);
431 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
439 base = devbase + pos;
441 flags = readb(base + HT_MSI_FLAGS);
442 if (!(flags & HT_MSI_FLAGS_FIXED)) {
443 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
444 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
447 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
448 PCI_SLOT(devfn), PCI_FUNC(devfn),
449 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
451 if (!(flags & HT_MSI_FLAGS_ENABLE))
452 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
455 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
462 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
463 unsigned int devfn, u32 vdid)
470 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
471 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
472 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
473 if (id == PCI_CAP_ID_HT) {
474 id = readb(devbase + pos + 3);
475 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
482 base = devbase + pos;
483 writeb(0x01, base + 2);
484 n = (readl(base + 4) >> 16) & 0xff;
486 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
488 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
490 for (i = 0; i <= n; i++) {
491 writeb(0x10 + 2 * i, base + 2);
492 tmp = readl(base + 4);
493 irq = (tmp >> 16) & 0xff;
494 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
495 /* mask it , will be unmasked later */
497 writel(tmp, base + 4);
498 mpic->fixups[irq].index = i;
499 mpic->fixups[irq].base = base;
500 /* Apple HT PIC has a non-standard way of doing EOIs */
501 if ((vdid & 0xffff) == 0x106b)
502 mpic->fixups[irq].applebase = devbase + 0x60;
504 mpic->fixups[irq].applebase = NULL;
505 writeb(0x11 + 2 * i, base + 2);
506 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
511 static void __init mpic_scan_ht_pics(struct mpic *mpic)
514 u8 __iomem *cfgspace;
516 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
518 /* Allocate fixups array */
519 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
520 BUG_ON(mpic->fixups == NULL);
523 raw_spin_lock_init(&mpic->fixup_lock);
525 /* Map U3 config space. We assume all IO-APICs are on the primary bus
526 * so we only need to map 64kB.
528 cfgspace = ioremap(0xf2000000, 0x10000);
529 BUG_ON(cfgspace == NULL);
531 /* Now we scan all slots. We do a very quick scan, we read the header
532 * type, vendor ID and device ID only, that's plenty enough
534 for (devfn = 0; devfn < 0x100; devfn++) {
535 u8 __iomem *devbase = cfgspace + (devfn << 8);
536 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
537 u32 l = readl(devbase + PCI_VENDOR_ID);
540 DBG("devfn %x, l: %x\n", devfn, l);
542 /* If no device, skip */
543 if (l == 0xffffffff || l == 0x00000000 ||
544 l == 0x0000ffff || l == 0xffff0000)
546 /* Check if is supports capability lists */
547 s = readw(devbase + PCI_STATUS);
548 if (!(s & PCI_STATUS_CAP_LIST))
551 mpic_scan_ht_pic(mpic, devbase, devfn, l);
552 mpic_scan_ht_msi(mpic, devbase, devfn);
555 /* next device, if function 0 */
556 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
561 #else /* CONFIG_MPIC_U3_HT_IRQS */
563 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
568 static void __init mpic_scan_ht_pics(struct mpic *mpic)
572 #endif /* CONFIG_MPIC_U3_HT_IRQS */
575 static int irq_choose_cpu(const struct cpumask *mask)
579 if (cpumask_equal(mask, cpu_all_mask)) {
580 static int irq_rover = 0;
581 static DEFINE_RAW_SPINLOCK(irq_rover_lock);
584 /* Round-robin distribution... */
586 raw_spin_lock_irqsave(&irq_rover_lock, flags);
588 irq_rover = cpumask_next(irq_rover, cpu_online_mask);
589 if (irq_rover >= nr_cpu_ids)
590 irq_rover = cpumask_first(cpu_online_mask);
594 raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
596 cpuid = cpumask_first_and(mask, cpu_online_mask);
597 if (cpuid >= nr_cpu_ids)
601 return get_hard_smp_processor_id(cpuid);
604 static int irq_choose_cpu(const struct cpumask *mask)
606 return hard_smp_processor_id();
610 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
612 /* Find an mpic associated with a given linux interrupt */
613 static struct mpic *mpic_find(unsigned int irq)
615 if (irq < NUM_ISA_INTERRUPTS)
618 return irq_get_chip_data(irq);
621 /* Determine if the linux irq is an IPI */
622 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
624 unsigned int src = mpic_irq_to_hw(irq);
626 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
630 /* Convert a cpu mask from logical to physical cpu numbers. */
631 static inline u32 mpic_physmask(u32 cpumask)
636 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
637 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
642 /* Get the mpic structure from the IPI number */
643 static inline struct mpic * mpic_from_ipi(struct irq_data *d)
645 return irq_data_get_irq_chip_data(d);
649 /* Get the mpic structure from the irq number */
650 static inline struct mpic * mpic_from_irq(unsigned int irq)
652 return irq_get_chip_data(irq);
655 /* Get the mpic structure from the irq data */
656 static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
658 return irq_data_get_irq_chip_data(d);
662 static inline void mpic_eoi(struct mpic *mpic)
664 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
665 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
669 * Linux descriptor level callbacks
673 void mpic_unmask_irq(struct irq_data *d)
675 unsigned int loops = 100000;
676 struct mpic *mpic = mpic_from_irq_data(d);
677 unsigned int src = mpic_irq_to_hw(d->irq);
679 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
681 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
682 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
684 /* make sure mask gets to controller before we return to user */
687 printk(KERN_ERR "%s: timeout on hwirq %u\n",
691 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
694 void mpic_mask_irq(struct irq_data *d)
696 unsigned int loops = 100000;
697 struct mpic *mpic = mpic_from_irq_data(d);
698 unsigned int src = mpic_irq_to_hw(d->irq);
700 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
702 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
703 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
706 /* make sure mask gets to controller before we return to user */
709 printk(KERN_ERR "%s: timeout on hwirq %u\n",
713 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
716 void mpic_end_irq(struct irq_data *d)
718 struct mpic *mpic = mpic_from_irq_data(d);
721 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
723 /* We always EOI on end_irq() even for edge interrupts since that
724 * should only lower the priority, the MPIC should have properly
725 * latched another edge interrupt coming in anyway
731 #ifdef CONFIG_MPIC_U3_HT_IRQS
733 static void mpic_unmask_ht_irq(struct irq_data *d)
735 struct mpic *mpic = mpic_from_irq_data(d);
736 unsigned int src = mpic_irq_to_hw(d->irq);
740 if (irqd_is_level_type(d))
741 mpic_ht_end_irq(mpic, src);
744 static unsigned int mpic_startup_ht_irq(struct irq_data *d)
746 struct mpic *mpic = mpic_from_irq_data(d);
747 unsigned int src = mpic_irq_to_hw(d->irq);
750 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
755 static void mpic_shutdown_ht_irq(struct irq_data *d)
757 struct mpic *mpic = mpic_from_irq_data(d);
758 unsigned int src = mpic_irq_to_hw(d->irq);
760 mpic_shutdown_ht_interrupt(mpic, src);
764 static void mpic_end_ht_irq(struct irq_data *d)
766 struct mpic *mpic = mpic_from_irq_data(d);
767 unsigned int src = mpic_irq_to_hw(d->irq);
770 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
772 /* We always EOI on end_irq() even for edge interrupts since that
773 * should only lower the priority, the MPIC should have properly
774 * latched another edge interrupt coming in anyway
777 if (irqd_is_level_type(d))
778 mpic_ht_end_irq(mpic, src);
781 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
785 static void mpic_unmask_ipi(struct irq_data *d)
787 struct mpic *mpic = mpic_from_ipi(d);
788 unsigned int src = mpic_irq_to_hw(d->irq) - mpic->ipi_vecs[0];
790 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
791 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
794 static void mpic_mask_ipi(struct irq_data *d)
796 /* NEVER disable an IPI... that's just plain wrong! */
799 static void mpic_end_ipi(struct irq_data *d)
801 struct mpic *mpic = mpic_from_ipi(d);
804 * IPIs are marked IRQ_PER_CPU. This has the side effect of
805 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
806 * applying to them. We EOI them late to avoid re-entering.
807 * We mark IPI's with IRQF_DISABLED as they must run with
813 #endif /* CONFIG_SMP */
815 int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
818 struct mpic *mpic = mpic_from_irq_data(d);
819 unsigned int src = mpic_irq_to_hw(d->irq);
821 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
822 int cpuid = irq_choose_cpu(cpumask);
824 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
828 alloc_cpumask_var(&tmp, GFP_KERNEL);
830 cpumask_and(tmp, cpumask, cpu_online_mask);
832 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
833 mpic_physmask(cpumask_bits(tmp)[0]));
835 free_cpumask_var(tmp);
841 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
843 /* Now convert sense value */
844 switch(type & IRQ_TYPE_SENSE_MASK) {
845 case IRQ_TYPE_EDGE_RISING:
846 return MPIC_INFO(VECPRI_SENSE_EDGE) |
847 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
848 case IRQ_TYPE_EDGE_FALLING:
849 case IRQ_TYPE_EDGE_BOTH:
850 return MPIC_INFO(VECPRI_SENSE_EDGE) |
851 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
852 case IRQ_TYPE_LEVEL_HIGH:
853 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
854 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
855 case IRQ_TYPE_LEVEL_LOW:
857 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
858 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
862 int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
864 struct mpic *mpic = mpic_from_irq_data(d);
865 unsigned int src = mpic_irq_to_hw(d->irq);
866 unsigned int vecpri, vold, vnew;
868 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
869 mpic, d->irq, src, flow_type);
871 if (src >= mpic->irq_count)
874 if (flow_type == IRQ_TYPE_NONE)
875 if (mpic->senses && src < mpic->senses_count)
876 flow_type = mpic->senses[src];
877 if (flow_type == IRQ_TYPE_NONE)
878 flow_type = IRQ_TYPE_LEVEL_LOW;
880 irqd_set_trigger_type(d, flow_type);
882 if (mpic_is_ht_interrupt(mpic, src))
883 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
884 MPIC_VECPRI_SENSE_EDGE;
886 vecpri = mpic_type_to_vecpri(mpic, flow_type);
888 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
889 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
890 MPIC_INFO(VECPRI_SENSE_MASK));
893 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
895 return IRQ_SET_MASK_OK_NOCOPY;;
898 void mpic_set_vector(unsigned int virq, unsigned int vector)
900 struct mpic *mpic = mpic_from_irq(virq);
901 unsigned int src = mpic_irq_to_hw(virq);
904 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
905 mpic, virq, src, vector);
907 if (src >= mpic->irq_count)
910 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
911 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
913 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
916 void mpic_set_destination(unsigned int virq, unsigned int cpuid)
918 struct mpic *mpic = mpic_from_irq(virq);
919 unsigned int src = mpic_irq_to_hw(virq);
921 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
922 mpic, virq, src, cpuid);
924 if (src >= mpic->irq_count)
927 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
930 static struct irq_chip mpic_irq_chip = {
931 .irq_mask = mpic_mask_irq,
932 .irq_unmask = mpic_unmask_irq,
933 .irq_eoi = mpic_end_irq,
934 .irq_set_type = mpic_set_irq_type,
938 static struct irq_chip mpic_ipi_chip = {
939 .irq_mask = mpic_mask_ipi,
940 .irq_unmask = mpic_unmask_ipi,
941 .irq_eoi = mpic_end_ipi,
943 #endif /* CONFIG_SMP */
945 #ifdef CONFIG_MPIC_U3_HT_IRQS
946 static struct irq_chip mpic_irq_ht_chip = {
947 .irq_startup = mpic_startup_ht_irq,
948 .irq_shutdown = mpic_shutdown_ht_irq,
949 .irq_mask = mpic_mask_irq,
950 .irq_unmask = mpic_unmask_ht_irq,
951 .irq_eoi = mpic_end_ht_irq,
952 .irq_set_type = mpic_set_irq_type,
954 #endif /* CONFIG_MPIC_U3_HT_IRQS */
957 static int mpic_host_match(struct irq_host *h, struct device_node *node)
959 /* Exact match, unless mpic node is NULL */
960 return h->of_node == NULL || h->of_node == node;
963 static int mpic_host_map(struct irq_host *h, unsigned int virq,
966 struct mpic *mpic = h->host_data;
967 struct irq_chip *chip;
969 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
971 if (hw == mpic->spurious_vec)
973 if (mpic->protected && test_bit(hw, mpic->protected))
977 else if (hw >= mpic->ipi_vecs[0]) {
978 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
980 DBG("mpic: mapping as IPI\n");
981 irq_set_chip_data(virq, mpic);
982 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
986 #endif /* CONFIG_SMP */
988 if (hw >= mpic->irq_count)
991 mpic_msi_reserve_hwirq(mpic, hw);
994 chip = &mpic->hc_irq;
996 #ifdef CONFIG_MPIC_U3_HT_IRQS
997 /* Check for HT interrupts, override vecpri */
998 if (mpic_is_ht_interrupt(mpic, hw))
999 chip = &mpic->hc_ht_irq;
1000 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1002 DBG("mpic: mapping to irq chip @%p\n", chip);
1004 irq_set_chip_data(virq, mpic);
1005 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1007 /* Set default irq type */
1008 irq_set_irq_type(virq, IRQ_TYPE_NONE);
1010 /* If the MPIC was reset, then all vectors have already been
1011 * initialized. Otherwise, a per source lazy initialization
1014 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1015 mpic_set_vector(virq, hw);
1016 mpic_set_destination(virq, mpic_processor_id(mpic));
1017 mpic_irq_set_priority(virq, 8);
1023 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1024 const u32 *intspec, unsigned int intsize,
1025 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1028 static unsigned char map_mpic_senses[4] = {
1029 IRQ_TYPE_EDGE_RISING,
1031 IRQ_TYPE_LEVEL_HIGH,
1032 IRQ_TYPE_EDGE_FALLING,
1035 *out_hwirq = intspec[0];
1039 /* Apple invented a new race of encoding on machines with
1040 * an HT APIC. They encode, among others, the index within
1041 * the HT APIC. We don't care about it here since thankfully,
1042 * it appears that they have the APIC already properly
1043 * configured, and thus our current fixup code that reads the
1044 * APIC config works fine. However, we still need to mask out
1045 * bits in the specifier to make sure we only get bit 0 which
1046 * is the level/edge bit (the only sense bit exposed by Apple),
1047 * as their bit 1 means something else.
1049 if (machine_is(powermac))
1051 *out_flags = map_mpic_senses[intspec[1] & mask];
1053 *out_flags = IRQ_TYPE_NONE;
1055 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1056 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1061 static struct irq_host_ops mpic_host_ops = {
1062 .match = mpic_host_match,
1063 .map = mpic_host_map,
1064 .xlate = mpic_host_xlate,
1067 static int mpic_reset_prohibited(struct device_node *node)
1069 return node && of_get_property(node, "pic-no-reset", NULL);
1073 * Exported functions
1076 struct mpic * __init mpic_alloc(struct device_node *node,
1077 phys_addr_t phys_addr,
1079 unsigned int isu_size,
1080 unsigned int irq_count,
1088 u64 paddr = phys_addr;
1090 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1096 mpic->hc_irq = mpic_irq_chip;
1097 mpic->hc_irq.name = name;
1098 if (flags & MPIC_PRIMARY)
1099 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1100 #ifdef CONFIG_MPIC_U3_HT_IRQS
1101 mpic->hc_ht_irq = mpic_irq_ht_chip;
1102 mpic->hc_ht_irq.name = name;
1103 if (flags & MPIC_PRIMARY)
1104 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1105 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1108 mpic->hc_ipi = mpic_ipi_chip;
1109 mpic->hc_ipi.name = name;
1110 #endif /* CONFIG_SMP */
1112 mpic->flags = flags;
1113 mpic->isu_size = isu_size;
1114 mpic->irq_count = irq_count;
1115 mpic->num_sources = 0; /* so far */
1117 if (flags & MPIC_LARGE_VECTORS)
1122 mpic->timer_vecs[0] = intvec_top - 8;
1123 mpic->timer_vecs[1] = intvec_top - 7;
1124 mpic->timer_vecs[2] = intvec_top - 6;
1125 mpic->timer_vecs[3] = intvec_top - 5;
1126 mpic->ipi_vecs[0] = intvec_top - 4;
1127 mpic->ipi_vecs[1] = intvec_top - 3;
1128 mpic->ipi_vecs[2] = intvec_top - 2;
1129 mpic->ipi_vecs[3] = intvec_top - 1;
1130 mpic->spurious_vec = intvec_top;
1132 /* Check for "big-endian" in device-tree */
1133 if (node && of_get_property(node, "big-endian", NULL) != NULL)
1134 mpic->flags |= MPIC_BIG_ENDIAN;
1136 /* Look for protected sources */
1139 unsigned int bits, mapsize;
1141 of_get_property(node, "protected-sources", &psize);
1144 bits = intvec_top + 1;
1145 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1146 mpic->protected = kzalloc(mapsize, GFP_KERNEL);
1147 BUG_ON(mpic->protected == NULL);
1148 for (i = 0; i < psize; i++) {
1149 if (psrc[i] > intvec_top)
1151 __set_bit(psrc[i], mpic->protected);
1156 #ifdef CONFIG_MPIC_WEIRD
1157 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1160 /* default register type */
1161 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1162 mpic_access_mmio_be : mpic_access_mmio_le;
1164 /* If no physical address is passed in, a device-node is mandatory */
1165 BUG_ON(paddr == 0 && node == NULL);
1167 /* If no physical address passed in, check if it's dcr based */
1168 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1169 #ifdef CONFIG_PPC_DCR
1170 mpic->flags |= MPIC_USES_DCR;
1171 mpic->reg_type = mpic_access_dcr;
1174 #endif /* CONFIG_PPC_DCR */
1177 /* If the MPIC is not DCR based, and no physical address was passed
1178 * in, try to obtain one
1180 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1181 const u32 *reg = of_get_property(node, "reg", NULL);
1182 BUG_ON(reg == NULL);
1183 paddr = of_translate_address(node, reg);
1184 BUG_ON(paddr == OF_BAD_ADDR);
1187 /* Map the global registers */
1188 mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1189 mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1193 /* When using a device-node, reset requests are only honored if the MPIC
1194 * is allowed to reset.
1196 if (mpic_reset_prohibited(node))
1197 mpic->flags |= MPIC_NO_RESET;
1199 if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
1200 printk(KERN_DEBUG "mpic: Resetting\n");
1201 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1202 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1203 | MPIC_GREG_GCONF_RESET);
1204 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1205 & MPIC_GREG_GCONF_RESET)
1210 if (flags & MPIC_ENABLE_COREINT)
1211 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1212 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1213 | MPIC_GREG_GCONF_COREINT);
1215 if (flags & MPIC_ENABLE_MCK)
1216 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1217 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1218 | MPIC_GREG_GCONF_MCK);
1220 /* Read feature register, calculate num CPUs and, for non-ISU
1221 * MPICs, num sources as well. On ISU MPICs, sources are counted
1224 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1225 mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1226 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1227 if (isu_size == 0) {
1228 if (flags & MPIC_BROKEN_FRR_NIRQS)
1229 mpic->num_sources = mpic->irq_count;
1232 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1233 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1236 /* Map the per-CPU registers */
1237 for (i = 0; i < mpic->num_cpus; i++) {
1238 mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
1239 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1243 /* Initialize main ISU if none provided */
1244 if (mpic->isu_size == 0) {
1245 mpic->isu_size = mpic->num_sources;
1246 mpic_map(mpic, node, paddr, &mpic->isus[0],
1247 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1249 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1250 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1252 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
1253 isu_size ? isu_size : mpic->num_sources,
1255 flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1256 if (mpic->irqhost == NULL)
1259 mpic->irqhost->host_data = mpic;
1261 /* Display version */
1262 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1276 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1278 name, vers, (unsigned long long)paddr, mpic->num_cpus);
1279 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1280 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1285 if (flags & MPIC_PRIMARY) {
1286 mpic_primary = mpic;
1287 irq_set_default_host(mpic->irqhost);
1293 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1296 unsigned int isu_first = isu_num * mpic->isu_size;
1298 BUG_ON(isu_num >= MPIC_MAX_ISU);
1300 mpic_map(mpic, mpic->irqhost->of_node,
1301 paddr, &mpic->isus[isu_num], 0,
1302 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1304 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1305 mpic->num_sources = isu_first + mpic->isu_size;
1308 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1310 mpic->senses = senses;
1311 mpic->senses_count = count;
1314 void __init mpic_init(struct mpic *mpic)
1319 BUG_ON(mpic->num_sources == 0);
1321 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1323 /* Set current processor priority to max */
1324 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1326 /* Initialize timers: just disable them all */
1327 for (i = 0; i < 4; i++) {
1328 mpic_write(mpic->tmregs,
1329 i * MPIC_INFO(TIMER_STRIDE) +
1330 MPIC_INFO(TIMER_DESTINATION), 0);
1331 mpic_write(mpic->tmregs,
1332 i * MPIC_INFO(TIMER_STRIDE) +
1333 MPIC_INFO(TIMER_VECTOR_PRI),
1335 (mpic->timer_vecs[0] + i));
1338 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1339 mpic_test_broken_ipi(mpic);
1340 for (i = 0; i < 4; i++) {
1343 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1344 (mpic->ipi_vecs[0] + i));
1347 /* Initialize interrupt sources */
1348 if (mpic->irq_count == 0)
1349 mpic->irq_count = mpic->num_sources;
1351 /* Do the HT PIC fixups on U3 broken mpic */
1352 DBG("MPIC flags: %x\n", mpic->flags);
1353 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1354 mpic_scan_ht_pics(mpic);
1355 mpic_u3msi_init(mpic);
1358 mpic_pasemi_msi_init(mpic);
1360 cpu = mpic_processor_id(mpic);
1362 if (!(mpic->flags & MPIC_NO_RESET)) {
1363 for (i = 0; i < mpic->num_sources; i++) {
1364 /* start with vector = source number, and masked */
1365 u32 vecpri = MPIC_VECPRI_MASK | i |
1366 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1368 /* check if protected */
1369 if (mpic->protected && test_bit(i, mpic->protected))
1372 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1373 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1377 /* Init spurious vector */
1378 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1380 /* Disable 8259 passthrough, if supported */
1381 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1382 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1383 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1384 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1386 if (mpic->flags & MPIC_NO_BIAS)
1387 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1388 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1389 | MPIC_GREG_GCONF_NO_BIAS);
1391 /* Set current processor priority to 0 */
1392 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1395 /* allocate memory to save mpic state */
1396 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1398 BUG_ON(mpic->save_data == NULL);
1402 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1406 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1407 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1408 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1409 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1412 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1414 unsigned long flags;
1417 raw_spin_lock_irqsave(&mpic_lock, flags);
1418 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1420 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1422 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1423 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1424 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1427 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1429 struct mpic *mpic = mpic_find(irq);
1430 unsigned int src = mpic_irq_to_hw(irq);
1431 unsigned long flags;
1437 raw_spin_lock_irqsave(&mpic_lock, flags);
1438 if (mpic_is_ipi(mpic, irq)) {
1439 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1440 ~MPIC_VECPRI_PRIORITY_MASK;
1441 mpic_ipi_write(src - mpic->ipi_vecs[0],
1442 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1444 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1445 & ~MPIC_VECPRI_PRIORITY_MASK;
1446 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1447 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1449 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1452 void mpic_setup_this_cpu(void)
1455 struct mpic *mpic = mpic_primary;
1456 unsigned long flags;
1457 u32 msk = 1 << hard_smp_processor_id();
1460 BUG_ON(mpic == NULL);
1462 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1464 raw_spin_lock_irqsave(&mpic_lock, flags);
1466 /* let the mpic know we want intrs. default affinity is 0xffffffff
1467 * until changed via /proc. That's how it's done on x86. If we want
1468 * it differently, then we should make sure we also change the default
1469 * values of irq_desc[].affinity in irq.c.
1471 if (distribute_irqs) {
1472 for (i = 0; i < mpic->num_sources ; i++)
1473 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1474 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1477 /* Set current processor priority to 0 */
1478 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1480 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1481 #endif /* CONFIG_SMP */
1484 int mpic_cpu_get_priority(void)
1486 struct mpic *mpic = mpic_primary;
1488 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1491 void mpic_cpu_set_priority(int prio)
1493 struct mpic *mpic = mpic_primary;
1495 prio &= MPIC_CPU_TASKPRI_MASK;
1496 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1499 void mpic_teardown_this_cpu(int secondary)
1501 struct mpic *mpic = mpic_primary;
1502 unsigned long flags;
1503 u32 msk = 1 << hard_smp_processor_id();
1506 BUG_ON(mpic == NULL);
1508 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1509 raw_spin_lock_irqsave(&mpic_lock, flags);
1511 /* let the mpic know we don't want intrs. */
1512 for (i = 0; i < mpic->num_sources ; i++)
1513 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1514 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1516 /* Set current processor priority to max */
1517 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1518 /* We need to EOI the IPI since not all platforms reset the MPIC
1519 * on boot and new interrupts wouldn't get delivered otherwise.
1523 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1527 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1531 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1533 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1535 if (unlikely(src == mpic->spurious_vec)) {
1536 if (mpic->flags & MPIC_SPV_EOI)
1540 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1541 if (printk_ratelimit())
1542 printk(KERN_WARNING "%s: Got protected source %d !\n",
1543 mpic->name, (int)src);
1548 return irq_linear_revmap(mpic->irqhost, src);
1551 unsigned int mpic_get_one_irq(struct mpic *mpic)
1553 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1556 unsigned int mpic_get_irq(void)
1558 struct mpic *mpic = mpic_primary;
1560 BUG_ON(mpic == NULL);
1562 return mpic_get_one_irq(mpic);
1565 unsigned int mpic_get_coreint_irq(void)
1568 struct mpic *mpic = mpic_primary;
1571 BUG_ON(mpic == NULL);
1573 src = mfspr(SPRN_EPR);
1575 if (unlikely(src == mpic->spurious_vec)) {
1576 if (mpic->flags & MPIC_SPV_EOI)
1580 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1581 if (printk_ratelimit())
1582 printk(KERN_WARNING "%s: Got protected source %d !\n",
1583 mpic->name, (int)src);
1587 return irq_linear_revmap(mpic->irqhost, src);
1593 unsigned int mpic_get_mcirq(void)
1595 struct mpic *mpic = mpic_primary;
1597 BUG_ON(mpic == NULL);
1599 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1603 void mpic_request_ipis(void)
1605 struct mpic *mpic = mpic_primary;
1607 BUG_ON(mpic == NULL);
1609 printk(KERN_INFO "mpic: requesting IPIs...\n");
1611 for (i = 0; i < 4; i++) {
1612 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1613 mpic->ipi_vecs[0] + i);
1614 if (vipi == NO_IRQ) {
1615 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1618 smp_request_message_ipi(vipi, i);
1622 static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask)
1624 struct mpic *mpic = mpic_primary;
1626 BUG_ON(mpic == NULL);
1629 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1632 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1633 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1634 mpic_physmask(cpumask_bits(cpu_mask)[0]));
1637 void smp_mpic_message_pass(int target, int msg)
1641 /* make sure we're sending something that translates to an IPI */
1642 if ((unsigned int)msg > 3) {
1643 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1644 smp_processor_id(), msg);
1649 mpic_send_ipi(msg, cpu_online_mask);
1651 case MSG_ALL_BUT_SELF:
1652 alloc_cpumask_var(&tmp, GFP_NOWAIT);
1653 cpumask_andnot(tmp, cpu_online_mask,
1654 cpumask_of(smp_processor_id()));
1655 mpic_send_ipi(msg, tmp);
1656 free_cpumask_var(tmp);
1659 mpic_send_ipi(msg, cpumask_of(target));
1664 int __init smp_mpic_probe(void)
1668 DBG("smp_mpic_probe()...\n");
1670 nr_cpus = cpumask_weight(cpu_possible_mask);
1672 DBG("nr_cpus: %d\n", nr_cpus);
1675 mpic_request_ipis();
1680 void __devinit smp_mpic_setup_cpu(int cpu)
1682 mpic_setup_this_cpu();
1685 void mpic_reset_core(int cpu)
1687 struct mpic *mpic = mpic_primary;
1689 int cpuid = get_hard_smp_processor_id(cpu);
1691 /* Set target bit for core reset */
1692 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1693 pir |= (1 << cpuid);
1694 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1695 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1697 /* Restore target bit after reset complete */
1698 pir &= ~(1 << cpuid);
1699 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1700 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1702 #endif /* CONFIG_SMP */
1705 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1707 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1710 for (i = 0; i < mpic->num_sources; i++) {
1711 mpic->save_data[i].vecprio =
1712 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1713 mpic->save_data[i].dest =
1714 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1720 static int mpic_resume(struct sys_device *dev)
1722 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1725 for (i = 0; i < mpic->num_sources; i++) {
1726 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1727 mpic->save_data[i].vecprio);
1728 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1729 mpic->save_data[i].dest);
1731 #ifdef CONFIG_MPIC_U3_HT_IRQS
1733 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1736 /* we use the lowest bit in an inverted meaning */
1737 if ((mpic->save_data[i].fixup_data & 1) == 0)
1740 /* Enable and configure */
1741 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1743 writel(mpic->save_data[i].fixup_data & ~1,
1748 } /* end for loop */
1754 static struct sysdev_class mpic_sysclass = {
1756 .resume = mpic_resume,
1757 .suspend = mpic_suspend,
1762 static int mpic_init_sys(void)
1764 struct mpic *mpic = mpics;
1767 error = sysdev_class_register(&mpic_sysclass);
1769 while (mpic && !error) {
1770 mpic->sysdev.cls = &mpic_sysclass;
1771 mpic->sysdev.id = id++;
1772 error = sysdev_register(&mpic->sysdev);
1778 device_initcall(mpic_init_sys);