arch/powerpc/sysdev/mpic.c

   1 /*
   2  *  arch/powerpc/kernel/mpic.c
   3  *
   4  *  Driver for interrupt controllers following the OpenPIC standard, the
   5  *  common implementation beeing IBM's MPIC. This driver also can deal
   6  *  with various broken implementations of this HW.
   7  *
   8  *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
   9  *
  10  *  This file is subject to the terms and conditions of the GNU General Public
  11  *  License.  See the file COPYING in the main directory of this archive
  12  *  for more details.
  13  */
  14
  15 #undef DEBUG
  16 #undef DEBUG_IPI
  17 #undef DEBUG_IRQ
  18 #undef DEBUG_LOW
  19
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/irq.h>
  24 #include <linux/smp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/bootmem.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/pci.h>
  29 #include <linux/slab.h>
  30
  31 #include <asm/ptrace.h>
  32 #include <asm/signal.h>
  33 #include <asm/io.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/irq.h>
  36 #include <asm/machdep.h>
  37 #include <asm/mpic.h>
  38 #include <asm/smp.h>
  39
  40 #include "mpic.h"
  41
  42 #ifdef DEBUG
  43 #define DBG(fmt...) printk(fmt)
  44 #else
  45 #define DBG(fmt...)
  46 #endif
  47
  48 static struct mpic *mpics;
  49 static struct mpic *mpic_primary;
  50 static DEFINE_RAW_SPINLOCK(mpic_lock);
  51
  52 #ifdef CONFIG_PPC32     /* XXX for now */
  53 #ifdef CONFIG_IRQ_ALL_CPUS
  54 #define distribute_irqs (1)
  55 #else
  56 #define distribute_irqs (0)
  57 #endif
  58 #endif
  59
  60 #ifdef CONFIG_MPIC_WEIRD
  61 static u32 mpic_infos[][MPIC_IDX_END] = {
  62         [0] = { /* Original OpenPIC compatible MPIC */
  63                 MPIC_GREG_BASE,
  64                 MPIC_GREG_FEATURE_0,
  65                 MPIC_GREG_GLOBAL_CONF_0,
  66                 MPIC_GREG_VENDOR_ID,
  67                 MPIC_GREG_IPI_VECTOR_PRI_0,
  68                 MPIC_GREG_IPI_STRIDE,
  69                 MPIC_GREG_SPURIOUS,
  70                 MPIC_GREG_TIMER_FREQ,
  71
  72                 MPIC_TIMER_BASE,
  73                 MPIC_TIMER_STRIDE,
  74                 MPIC_TIMER_CURRENT_CNT,
  75                 MPIC_TIMER_BASE_CNT,
  76                 MPIC_TIMER_VECTOR_PRI,
  77                 MPIC_TIMER_DESTINATION,
  78
  79                 MPIC_CPU_BASE,
  80                 MPIC_CPU_STRIDE,
  81                 MPIC_CPU_IPI_DISPATCH_0,
  82                 MPIC_CPU_IPI_DISPATCH_STRIDE,
  83                 MPIC_CPU_CURRENT_TASK_PRI,
  84                 MPIC_CPU_WHOAMI,
  85                 MPIC_CPU_INTACK,
  86                 MPIC_CPU_EOI,
  87                 MPIC_CPU_MCACK,
  88
  89                 MPIC_IRQ_BASE,
  90                 MPIC_IRQ_STRIDE,
  91                 MPIC_IRQ_VECTOR_PRI,
  92                 MPIC_VECPRI_VECTOR_MASK,
  93                 MPIC_VECPRI_POLARITY_POSITIVE,
  94                 MPIC_VECPRI_POLARITY_NEGATIVE,
  95                 MPIC_VECPRI_SENSE_LEVEL,
  96                 MPIC_VECPRI_SENSE_EDGE,
  97                 MPIC_VECPRI_POLARITY_MASK,
  98                 MPIC_VECPRI_SENSE_MASK,
  99                 MPIC_IRQ_DESTINATION
 100         },
 101         [1] = { /* Tsi108/109 PIC */
 102                 TSI108_GREG_BASE,
 103                 TSI108_GREG_FEATURE_0,
 104                 TSI108_GREG_GLOBAL_CONF_0,
 105                 TSI108_GREG_VENDOR_ID,
 106                 TSI108_GREG_IPI_VECTOR_PRI_0,
 107                 TSI108_GREG_IPI_STRIDE,
 108                 TSI108_GREG_SPURIOUS,
 109                 TSI108_GREG_TIMER_FREQ,
 110
 111                 TSI108_TIMER_BASE,
 112                 TSI108_TIMER_STRIDE,
 113                 TSI108_TIMER_CURRENT_CNT,
 114                 TSI108_TIMER_BASE_CNT,
 115                 TSI108_TIMER_VECTOR_PRI,
 116                 TSI108_TIMER_DESTINATION,
 117
 118                 TSI108_CPU_BASE,
 119                 TSI108_CPU_STRIDE,
 120                 TSI108_CPU_IPI_DISPATCH_0,
 121                 TSI108_CPU_IPI_DISPATCH_STRIDE,
 122                 TSI108_CPU_CURRENT_TASK_PRI,
 123                 TSI108_CPU_WHOAMI,
 124                 TSI108_CPU_INTACK,
 125                 TSI108_CPU_EOI,
 126                 TSI108_CPU_MCACK,
 127
 128                 TSI108_IRQ_BASE,
 129                 TSI108_IRQ_STRIDE,
 130                 TSI108_IRQ_VECTOR_PRI,
 131                 TSI108_VECPRI_VECTOR_MASK,
 132                 TSI108_VECPRI_POLARITY_POSITIVE,
 133                 TSI108_VECPRI_POLARITY_NEGATIVE,
 134                 TSI108_VECPRI_SENSE_LEVEL,
 135                 TSI108_VECPRI_SENSE_EDGE,
 136                 TSI108_VECPRI_POLARITY_MASK,
 137                 TSI108_VECPRI_SENSE_MASK,
 138                 TSI108_IRQ_DESTINATION
 139         },
 140 };
 141
 142 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
 143
 144 #else /* CONFIG_MPIC_WEIRD */
 145
 146 #define MPIC_INFO(name) MPIC_##name
 147
 148 #endif /* CONFIG_MPIC_WEIRD */
 149
 150 static inline unsigned int mpic_processor_id(struct mpic *mpic)
 151 {
 152         unsigned int cpu = 0;
 153
 154         if (mpic->flags & MPIC_PRIMARY)
 155                 cpu = hard_smp_processor_id();
 156
 157         return cpu;
 158 }
 159
 160 /*
 161  * Register accessor functions
 162  */
 163
 164
 165 static inline u32 _mpic_read(enum mpic_reg_type type,
 166                              struct mpic_reg_bank *rb,
 167                              unsigned int reg)
 168 {
 169         switch(type) {
 170 #ifdef CONFIG_PPC_DCR
 171         case mpic_access_dcr:
 172                 return dcr_read(rb->dhost, reg);
 173 #endif
 174         case mpic_access_mmio_be:
 175                 return in_be32(rb->base + (reg >> 2));
 176         case mpic_access_mmio_le:
 177         default:
 178                 return in_le32(rb->base + (reg >> 2));
 179         }
 180 }
 181
 182 static inline void _mpic_write(enum mpic_reg_type type,
 183                                struct mpic_reg_bank *rb,
 184                                unsigned int reg, u32 value)
 185 {
 186         switch(type) {
 187 #ifdef CONFIG_PPC_DCR
 188         case mpic_access_dcr:
 189                 dcr_write(rb->dhost, reg, value);
 190                 break;
 191 #endif
 192         case mpic_access_mmio_be:
 193                 out_be32(rb->base + (reg >> 2), value);
 194                 break;
 195         case mpic_access_mmio_le:
 196         default:
 197                 out_le32(rb->base + (reg >> 2), value);
 198                 break;
 199         }
 200 }
 201
 202 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
 203 {
 204         enum mpic_reg_type type = mpic->reg_type;
 205         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 206                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 207
 208         if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
 209                 type = mpic_access_mmio_be;
 210         return _mpic_read(type, &mpic->gregs, offset);
 211 }
 212
 213 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
 214 {
 215         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 216                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 217
 218         _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
 219 }
 220
 221 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
 222 {
 223         unsigned int cpu = mpic_processor_id(mpic);
 224
 225         return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
 226 }
 227
 228 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
 229 {
 230         unsigned int cpu = mpic_processor_id(mpic);
 231
 232         _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
 233 }
 234
 235 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
 236 {
 237         unsigned int    isu = src_no >> mpic->isu_shift;
 238         unsigned int    idx = src_no & mpic->isu_mask;
 239         unsigned int    val;
 240
 241         val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
 242                          reg + (idx * MPIC_INFO(IRQ_STRIDE)));
 243 #ifdef CONFIG_MPIC_BROKEN_REGREAD
 244         if (reg == 0)
 245                 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
 246                         mpic->isu_reg0_shadow[src_no];
 247 #endif
 248         return val;
 249 }
 250
 251 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
 252                                    unsigned int reg, u32 value)
 253 {
 254         unsigned int    isu = src_no >> mpic->isu_shift;
 255         unsigned int    idx = src_no & mpic->isu_mask;
 256
 257         _mpic_write(mpic->reg_type, &mpic->isus[isu],
 258                     reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
 259
 260 #ifdef CONFIG_MPIC_BROKEN_REGREAD
 261         if (reg == 0)
 262                 mpic->isu_reg0_shadow[src_no] =
 263                         value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
 264 #endif
 265 }
 266
 267 #define mpic_read(b,r)          _mpic_read(mpic->reg_type,&(b),(r))
 268 #define mpic_write(b,r,v)       _mpic_write(mpic->reg_type,&(b),(r),(v))
 269 #define mpic_ipi_read(i)        _mpic_ipi_read(mpic,(i))
 270 #define mpic_ipi_write(i,v)     _mpic_ipi_write(mpic,(i),(v))
 271 #define mpic_cpu_read(i)        _mpic_cpu_read(mpic,(i))
 272 #define mpic_cpu_write(i,v)     _mpic_cpu_write(mpic,(i),(v))
 273 #define mpic_irq_read(s,r)      _mpic_irq_read(mpic,(s),(r))
 274 #define mpic_irq_write(s,r,v)   _mpic_irq_write(mpic,(s),(r),(v))
 275
 276
 277 /*
 278  * Low level utility functions
 279  */
 280
 281
 282 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
 283                            struct mpic_reg_bank *rb, unsigned int offset,
 284                            unsigned int size)
 285 {
 286         rb->base = ioremap(phys_addr + offset, size);
 287         BUG_ON(rb->base == NULL);
 288 }
 289
 290 #ifdef CONFIG_PPC_DCR
 291 static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
 292                           struct mpic_reg_bank *rb,
 293                           unsigned int offset, unsigned int size)
 294 {
 295         const u32 *dbasep;
 296
 297         dbasep = of_get_property(node, "dcr-reg", NULL);
 298
 299         rb->dhost = dcr_map(node, *dbasep + offset, size);
 300         BUG_ON(!DCR_MAP_OK(rb->dhost));
 301 }
 302
 303 static inline void mpic_map(struct mpic *mpic, struct device_node *node,
 304                             phys_addr_t phys_addr, struct mpic_reg_bank *rb,
 305                             unsigned int offset, unsigned int size)
 306 {
 307         if (mpic->flags & MPIC_USES_DCR)
 308                 _mpic_map_dcr(mpic, node, rb, offset, size);
 309         else
 310                 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
 311 }
 312 #else /* CONFIG_PPC_DCR */
 313 #define mpic_map(m,n,p,b,o,s)   _mpic_map_mmio(m,p,b,o,s)
 314 #endif /* !CONFIG_PPC_DCR */
 315
 316
 317
 318 /* Check if we have one of those nice broken MPICs with a flipped endian on
 319  * reads from IPI registers
 320  */
 321 static void __init mpic_test_broken_ipi(struct mpic *mpic)
 322 {
 323         u32 r;
 324
 325         mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
 326         r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
 327
 328         if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
 329                 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
 330                 mpic->flags |= MPIC_BROKEN_IPI;
 331         }
 332 }
 333
 334 #ifdef CONFIG_MPIC_U3_HT_IRQS
 335
 336 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
 337  * to force the edge setting on the MPIC and do the ack workaround.
 338  */
 339 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 340 {
 341         if (source >= 128 || !mpic->fixups)
 342                 return 0;
 343         return mpic->fixups[source].base != NULL;
 344 }
 345
 346
 347 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
 348 {
 349         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 350
 351         if (fixup->applebase) {
 352                 unsigned int soff = (fixup->index >> 3) & ~3;
 353                 unsigned int mask = 1U << (fixup->index & 0x1f);
 354                 writel(mask, fixup->applebase + soff);
 355         } else {
 356                 raw_spin_lock(&mpic->fixup_lock);
 357                 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
 358                 writel(fixup->data, fixup->base + 4);
 359                 raw_spin_unlock(&mpic->fixup_lock);
 360         }
 361 }
 362
 363 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
 364                                       bool level)
 365 {
 366         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 367         unsigned long flags;
 368         u32 tmp;
 369
 370         if (fixup->base == NULL)
 371                 return;
 372
 373         DBG("startup_ht_interrupt(0x%x) index: %d\n",
 374             source, fixup->index);
 375         raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
 376         /* Enable and configure */
 377         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 378         tmp = readl(fixup->base + 4);
 379         tmp &= ~(0x23U);
 380         if (level)
 381                 tmp |= 0x22;
 382         writel(tmp, fixup->base + 4);
 383         raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 384
 385 #ifdef CONFIG_PM
 386         /* use the lowest bit inverted to the actual HW,
 387          * set if this fixup was enabled, clear otherwise */
 388         mpic->save_data[source].fixup_data = tmp | 1;
 389 #endif
 390 }
 391
 392 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
 393 {
 394         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 395         unsigned long flags;
 396         u32 tmp;
 397
 398         if (fixup->base == NULL)
 399                 return;
 400
 401         DBG("shutdown_ht_interrupt(0x%x)\n", source);
 402
 403         /* Disable */
 404         raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
 405         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 406         tmp = readl(fixup->base + 4);
 407         tmp |= 1;
 408         writel(tmp, fixup->base + 4);
 409         raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 410
 411 #ifdef CONFIG_PM
 412         /* use the lowest bit inverted to the actual HW,
 413          * set if this fixup was enabled, clear otherwise */
 414         mpic->save_data[source].fixup_data = tmp & ~1;
 415 #endif
 416 }
 417
 418 #ifdef CONFIG_PCI_MSI
 419 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 420                                     unsigned int devfn)
 421 {
 422         u8 __iomem *base;
 423         u8 pos, flags;
 424         u64 addr = 0;
 425
 426         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 427              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 428                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 429                 if (id == PCI_CAP_ID_HT) {
 430                         id = readb(devbase + pos + 3);
 431                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
 432                                 break;
 433                 }
 434         }
 435
 436         if (pos == 0)
 437                 return;
 438
 439         base = devbase + pos;
 440
 441         flags = readb(base + HT_MSI_FLAGS);
 442         if (!(flags & HT_MSI_FLAGS_FIXED)) {
 443                 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
 444                 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
 445         }
 446
 447         printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
 448                 PCI_SLOT(devfn), PCI_FUNC(devfn),
 449                 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
 450
 451         if (!(flags & HT_MSI_FLAGS_ENABLE))
 452                 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
 453 }
 454 #else
 455 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 456                                     unsigned int devfn)
 457 {
 458         return;
 459 }
 460 #endif
 461
 462 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
 463                                     unsigned int devfn, u32 vdid)
 464 {
 465         int i, irq, n;
 466         u8 __iomem *base;
 467         u32 tmp;
 468         u8 pos;
 469
 470         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 471              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 472                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 473                 if (id == PCI_CAP_ID_HT) {
 474                         id = readb(devbase + pos + 3);
 475                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
 476                                 break;
 477                 }
 478         }
 479         if (pos == 0)
 480                 return;
 481
 482         base = devbase + pos;
 483         writeb(0x01, base + 2);
 484         n = (readl(base + 4) >> 16) & 0xff;
 485
 486         printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
 487                " has %d irqs\n",
 488                devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
 489
 490         for (i = 0; i <= n; i++) {
 491                 writeb(0x10 + 2 * i, base + 2);
 492                 tmp = readl(base + 4);
 493                 irq = (tmp >> 16) & 0xff;
 494                 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
 495                 /* mask it , will be unmasked later */
 496                 tmp |= 0x1;
 497                 writel(tmp, base + 4);
 498                 mpic->fixups[irq].index = i;
 499                 mpic->fixups[irq].base = base;
 500                 /* Apple HT PIC has a non-standard way of doing EOIs */
 501                 if ((vdid & 0xffff) == 0x106b)
 502                         mpic->fixups[irq].applebase = devbase + 0x60;
 503                 else
 504                         mpic->fixups[irq].applebase = NULL;
 505                 writeb(0x11 + 2 * i, base + 2);
 506                 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
 507         }
 508 }
 509
 510
 511 static void __init mpic_scan_ht_pics(struct mpic *mpic)
 512 {
 513         unsigned int devfn;
 514         u8 __iomem *cfgspace;
 515
 516         printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
 517
 518         /* Allocate fixups array */
 519         mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
 520         BUG_ON(mpic->fixups == NULL);
 521
 522         /* Init spinlock */
 523         raw_spin_lock_init(&mpic->fixup_lock);
 524
 525         /* Map U3 config space. We assume all IO-APICs are on the primary bus
 526          * so we only need to map 64kB.
 527          */
 528         cfgspace = ioremap(0xf2000000, 0x10000);
 529         BUG_ON(cfgspace == NULL);
 530
 531         /* Now we scan all slots. We do a very quick scan, we read the header
 532          * type, vendor ID and device ID only, that's plenty enough
 533          */
 534         for (devfn = 0; devfn < 0x100; devfn++) {
 535                 u8 __iomem *devbase = cfgspace + (devfn << 8);
 536                 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
 537                 u32 l = readl(devbase + PCI_VENDOR_ID);
 538                 u16 s;
 539
 540                 DBG("devfn %x, l: %x\n", devfn, l);
 541
 542                 /* If no device, skip */
 543                 if (l == 0xffffffff || l == 0x00000000 ||
 544                     l == 0x0000ffff || l == 0xffff0000)
 545                         goto next;
 546                 /* Check if is supports capability lists */
 547                 s = readw(devbase + PCI_STATUS);
 548                 if (!(s & PCI_STATUS_CAP_LIST))
 549                         goto next;
 550
 551                 mpic_scan_ht_pic(mpic, devbase, devfn, l);
 552                 mpic_scan_ht_msi(mpic, devbase, devfn);
 553
 554         next:
 555                 /* next device, if function 0 */
 556                 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
 557                         devfn += 7;
 558         }
 559 }
 560
 561 #else /* CONFIG_MPIC_U3_HT_IRQS */
 562
 563 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 564 {
 565         return 0;
 566 }
 567
 568 static void __init mpic_scan_ht_pics(struct mpic *mpic)
 569 {
 570 }
 571
 572 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 573
 574 #ifdef CONFIG_SMP
 575 static int irq_choose_cpu(const struct cpumask *mask)
 576 {
 577         int cpuid;
 578
 579         if (cpumask_equal(mask, cpu_all_mask)) {
 580                 static int irq_rover = 0;
 581                 static DEFINE_RAW_SPINLOCK(irq_rover_lock);
 582                 unsigned long flags;
 583
 584                 /* Round-robin distribution... */
 585         do_round_robin:
 586                 raw_spin_lock_irqsave(&irq_rover_lock, flags);
 587
 588                 irq_rover = cpumask_next(irq_rover, cpu_online_mask);
 589                 if (irq_rover >= nr_cpu_ids)
 590                         irq_rover = cpumask_first(cpu_online_mask);
 591
 592                 cpuid = irq_rover;
 593
 594                 raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
 595         } else {
 596                 cpuid = cpumask_first_and(mask, cpu_online_mask);
 597                 if (cpuid >= nr_cpu_ids)
 598                         goto do_round_robin;
 599         }
 600
 601         return get_hard_smp_processor_id(cpuid);
 602 }
 603 #else
 604 static int irq_choose_cpu(const struct cpumask *mask)
 605 {
 606         return hard_smp_processor_id();
 607 }
 608 #endif
 609
 610 /* Find an mpic associated with a given linux interrupt */
 611 static struct mpic *mpic_find(unsigned int irq)
 612 {
 613         if (irq < NUM_ISA_INTERRUPTS)
 614                 return NULL;
 615
 616         return irq_get_chip_data(irq);
 617 }
 618
 619 /* Determine if the linux irq is an IPI */
 620 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
 621 {
 622         unsigned int src = virq_to_hw(irq);
 623
 624         return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
 625 }
 626
 627
 628 /* Convert a cpu mask from logical to physical cpu numbers. */
 629 static inline u32 mpic_physmask(u32 cpumask)
 630 {
 631         int i;
 632         u32 mask = 0;
 633
 634         for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
 635                 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
 636         return mask;
 637 }
 638
 639 #ifdef CONFIG_SMP
 640 /* Get the mpic structure from the IPI number */
 641 static inline struct mpic * mpic_from_ipi(struct irq_data *d)
 642 {
 643         return irq_data_get_irq_chip_data(d);
 644 }
 645 #endif
 646
 647 /* Get the mpic structure from the irq number */
 648 static inline struct mpic * mpic_from_irq(unsigned int irq)
 649 {
 650         return irq_get_chip_data(irq);
 651 }
 652
 653 /* Get the mpic structure from the irq data */
 654 static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
 655 {
 656         return irq_data_get_irq_chip_data(d);
 657 }
 658
 659 /* Send an EOI */
 660 static inline void mpic_eoi(struct mpic *mpic)
 661 {
 662         mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
 663         (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
 664 }
 665
 666 /*
 667  * Linux descriptor level callbacks
 668  */
 669
 670
 671 void mpic_unmask_irq(struct irq_data *d)
 672 {
 673         unsigned int loops = 100000;
 674         struct mpic *mpic = mpic_from_irq_data(d);
 675         unsigned int src = irqd_to_hwirq(d);
 676
 677         DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
 678
 679         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 680                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
 681                        ~MPIC_VECPRI_MASK);
 682         /* make sure mask gets to controller before we return to user */
 683         do {
 684                 if (!loops--) {
 685                         printk(KERN_ERR "%s: timeout on hwirq %u\n",
 686                                __func__, src);
 687                         break;
 688                 }
 689         } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
 690 }
 691
 692 void mpic_mask_irq(struct irq_data *d)
 693 {
 694         unsigned int loops = 100000;
 695         struct mpic *mpic = mpic_from_irq_data(d);
 696         unsigned int src = irqd_to_hwirq(d);
 697
 698         DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
 699
 700         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 701                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
 702                        MPIC_VECPRI_MASK);
 703
 704         /* make sure mask gets to controller before we return to user */
 705         do {
 706                 if (!loops--) {
 707                         printk(KERN_ERR "%s: timeout on hwirq %u\n",
 708                                __func__, src);
 709                         break;
 710                 }
 711         } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
 712 }
 713
 714 void mpic_end_irq(struct irq_data *d)
 715 {
 716         struct mpic *mpic = mpic_from_irq_data(d);
 717
 718 #ifdef DEBUG_IRQ
 719         DBG("%s: end_irq: %d\n", mpic->name, d->irq);
 720 #endif
 721         /* We always EOI on end_irq() even for edge interrupts since that
 722          * should only lower the priority, the MPIC should have properly
 723          * latched another edge interrupt coming in anyway
 724          */
 725
 726         mpic_eoi(mpic);
 727 }
 728
 729 #ifdef CONFIG_MPIC_U3_HT_IRQS
 730
 731 static void mpic_unmask_ht_irq(struct irq_data *d)
 732 {
 733         struct mpic *mpic = mpic_from_irq_data(d);
 734         unsigned int src = irqd_to_hwirq(d);
 735
 736         mpic_unmask_irq(d);
 737
 738         if (irqd_is_level_type(d))
 739                 mpic_ht_end_irq(mpic, src);
 740 }
 741
 742 static unsigned int mpic_startup_ht_irq(struct irq_data *d)
 743 {
 744         struct mpic *mpic = mpic_from_irq_data(d);
 745         unsigned int src = irqd_to_hwirq(d);
 746
 747         mpic_unmask_irq(d);
 748         mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
 749
 750         return 0;
 751 }
 752
 753 static void mpic_shutdown_ht_irq(struct irq_data *d)
 754 {
 755         struct mpic *mpic = mpic_from_irq_data(d);
 756         unsigned int src = irqd_to_hwirq(d);
 757
 758         mpic_shutdown_ht_interrupt(mpic, src);
 759         mpic_mask_irq(d);
 760 }
 761
 762 static void mpic_end_ht_irq(struct irq_data *d)
 763 {
 764         struct mpic *mpic = mpic_from_irq_data(d);
 765         unsigned int src = irqd_to_hwirq(d);
 766
 767 #ifdef DEBUG_IRQ
 768         DBG("%s: end_irq: %d\n", mpic->name, d->irq);
 769 #endif
 770         /* We always EOI on end_irq() even for edge interrupts since that
 771          * should only lower the priority, the MPIC should have properly
 772          * latched another edge interrupt coming in anyway
 773          */
 774
 775         if (irqd_is_level_type(d))
 776                 mpic_ht_end_irq(mpic, src);
 777         mpic_eoi(mpic);
 778 }
 779 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
 780
 781 #ifdef CONFIG_SMP
 782
 783 static void mpic_unmask_ipi(struct irq_data *d)
 784 {
 785         struct mpic *mpic = mpic_from_ipi(d);
 786         unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
 787
 788         DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
 789         mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
 790 }
 791
 792 static void mpic_mask_ipi(struct irq_data *d)
 793 {
 794         /* NEVER disable an IPI... that's just plain wrong! */
 795 }
 796
 797 static void mpic_end_ipi(struct irq_data *d)
 798 {
 799         struct mpic *mpic = mpic_from_ipi(d);
 800
 801         /*
 802          * IPIs are marked IRQ_PER_CPU. This has the side effect of
 803          * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
 804          * applying to them. We EOI them late to avoid re-entering.
 805          * We mark IPI's with IRQF_DISABLED as they must run with
 806          * irqs disabled.
 807          */
 808         mpic_eoi(mpic);
 809 }
 810
 811 #endif /* CONFIG_SMP */
 812
 813 int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 814                       bool force)
 815 {
 816         struct mpic *mpic = mpic_from_irq_data(d);
 817         unsigned int src = irqd_to_hwirq(d);
 818
 819         if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
 820                 int cpuid = irq_choose_cpu(cpumask);
 821
 822                 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
 823         } else {
 824                 cpumask_var_t tmp;
 825
 826                 alloc_cpumask_var(&tmp, GFP_KERNEL);
 827
 828                 cpumask_and(tmp, cpumask, cpu_online_mask);
 829
 830                 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
 831                                mpic_physmask(cpumask_bits(tmp)[0]));
 832
 833                 free_cpumask_var(tmp);
 834         }
 835
 836         return 0;
 837 }
 838
 839 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
 840 {
 841         /* Now convert sense value */
 842         switch(type & IRQ_TYPE_SENSE_MASK) {
 843         case IRQ_TYPE_EDGE_RISING:
 844                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
 845                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 846         case IRQ_TYPE_EDGE_FALLING:
 847         case IRQ_TYPE_EDGE_BOTH:
 848                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
 849                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 850         case IRQ_TYPE_LEVEL_HIGH:
 851                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 852                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 853         case IRQ_TYPE_LEVEL_LOW:
 854         default:
 855                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 856                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 857         }
 858 }
 859
 860 int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
 861 {
 862         struct mpic *mpic = mpic_from_irq_data(d);
 863         unsigned int src = irqd_to_hwirq(d);
 864         unsigned int vecpri, vold, vnew;
 865
 866         DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
 867             mpic, d->irq, src, flow_type);
 868
 869         if (src >= mpic->irq_count)
 870                 return -EINVAL;
 871
 872         if (flow_type == IRQ_TYPE_NONE)
 873                 if (mpic->senses && src < mpic->senses_count)
 874                         flow_type = mpic->senses[src];
 875         if (flow_type == IRQ_TYPE_NONE)
 876                 flow_type = IRQ_TYPE_LEVEL_LOW;
 877
 878         irqd_set_trigger_type(d, flow_type);
 879
 880         if (mpic_is_ht_interrupt(mpic, src))
 881                 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
 882                         MPIC_VECPRI_SENSE_EDGE;
 883         else
 884                 vecpri = mpic_type_to_vecpri(mpic, flow_type);
 885
 886         vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 887         vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
 888                         MPIC_INFO(VECPRI_SENSE_MASK));
 889         vnew |= vecpri;
 890         if (vold != vnew)
 891                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
 892
 893         return IRQ_SET_MASK_OK_NOCOPY;;
 894 }
 895
 896 void mpic_set_vector(unsigned int virq, unsigned int vector)
 897 {
 898         struct mpic *mpic = mpic_from_irq(virq);
 899         unsigned int src = virq_to_hw(virq);
 900         unsigned int vecpri;
 901
 902         DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
 903             mpic, virq, src, vector);
 904
 905         if (src >= mpic->irq_count)
 906                 return;
 907
 908         vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 909         vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
 910         vecpri |= vector;
 911         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
 912 }
 913
 914 void mpic_set_destination(unsigned int virq, unsigned int cpuid)
 915 {
 916         struct mpic *mpic = mpic_from_irq(virq);
 917         unsigned int src = virq_to_hw(virq);
 918
 919         DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
 920             mpic, virq, src, cpuid);
 921
 922         if (src >= mpic->irq_count)
 923                 return;
 924
 925         mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
 926 }
 927
 928 static struct irq_chip mpic_irq_chip = {
 929         .irq_mask       = mpic_mask_irq,
 930         .irq_unmask     = mpic_unmask_irq,
 931         .irq_eoi        = mpic_end_irq,
 932         .irq_set_type   = mpic_set_irq_type,
 933 };
 934
 935 #ifdef CONFIG_SMP
 936 static struct irq_chip mpic_ipi_chip = {
 937         .irq_mask       = mpic_mask_ipi,
 938         .irq_unmask     = mpic_unmask_ipi,
 939         .irq_eoi        = mpic_end_ipi,
 940 };
 941 #endif /* CONFIG_SMP */
 942
 943 #ifdef CONFIG_MPIC_U3_HT_IRQS
 944 static struct irq_chip mpic_irq_ht_chip = {
 945         .irq_startup    = mpic_startup_ht_irq,
 946         .irq_shutdown   = mpic_shutdown_ht_irq,
 947         .irq_mask       = mpic_mask_irq,
 948         .irq_unmask     = mpic_unmask_ht_irq,
 949         .irq_eoi        = mpic_end_ht_irq,
 950         .irq_set_type   = mpic_set_irq_type,
 951 };
 952 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 953
 954
 955 static int mpic_host_match(struct irq_host *h, struct device_node *node)
 956 {
 957         /* Exact match, unless mpic node is NULL */
 958         return h->of_node == NULL || h->of_node == node;
 959 }
 960
 961 static int mpic_host_map(struct irq_host *h, unsigned int virq,
 962                          irq_hw_number_t hw)
 963 {
 964         struct mpic *mpic = h->host_data;
 965         struct irq_chip *chip;
 966
 967         DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
 968
 969         if (hw == mpic->spurious_vec)
 970                 return -EINVAL;
 971         if (mpic->protected && test_bit(hw, mpic->protected))
 972                 return -EINVAL;
 973
 974 #ifdef CONFIG_SMP
 975         else if (hw >= mpic->ipi_vecs[0]) {
 976                 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
 977
 978                 DBG("mpic: mapping as IPI\n");
 979                 irq_set_chip_data(virq, mpic);
 980                 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
 981                                          handle_percpu_irq);
 982                 return 0;
 983         }
 984 #endif /* CONFIG_SMP */
 985
 986         if (hw >= mpic->irq_count)
 987                 return -EINVAL;
 988
 989         mpic_msi_reserve_hwirq(mpic, hw);
 990
 991         /* Default chip */
 992         chip = &mpic->hc_irq;
 993
 994 #ifdef CONFIG_MPIC_U3_HT_IRQS
 995         /* Check for HT interrupts, override vecpri */
 996         if (mpic_is_ht_interrupt(mpic, hw))
 997                 chip = &mpic->hc_ht_irq;
 998 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 999
1000         DBG("mpic: mapping to irq chip @%p\n", chip);
1001
1002         irq_set_chip_data(virq, mpic);
1003         irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1004
1005         /* Set default irq type */
1006         irq_set_irq_type(virq, IRQ_TYPE_NONE);
1007
1008         /* If the MPIC was reset, then all vectors have already been
1009          * initialized.  Otherwise, a per source lazy initialization
1010          * is done here.
1011          */
1012         if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1013                 mpic_set_vector(virq, hw);
1014                 mpic_set_destination(virq, mpic_processor_id(mpic));
1015                 mpic_irq_set_priority(virq, 8);
1016         }
1017
1018         return 0;
1019 }
1020
1021 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1022                            const u32 *intspec, unsigned int intsize,
1023                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1024
1025 {
1026         static unsigned char map_mpic_senses[4] = {
1027                 IRQ_TYPE_EDGE_RISING,
1028                 IRQ_TYPE_LEVEL_LOW,
1029                 IRQ_TYPE_LEVEL_HIGH,
1030                 IRQ_TYPE_EDGE_FALLING,
1031         };
1032
1033         *out_hwirq = intspec[0];
1034         if (intsize > 1) {
1035                 u32 mask = 0x3;
1036
1037                 /* Apple invented a new race of encoding on machines with
1038                  * an HT APIC. They encode, among others, the index within
1039                  * the HT APIC. We don't care about it here since thankfully,
1040                  * it appears that they have the APIC already properly
1041                  * configured, and thus our current fixup code that reads the
1042                  * APIC config works fine. However, we still need to mask out
1043                  * bits in the specifier to make sure we only get bit 0 which
1044                  * is the level/edge bit (the only sense bit exposed by Apple),
1045                  * as their bit 1 means something else.
1046                  */
1047                 if (machine_is(powermac))
1048                         mask = 0x1;
1049                 *out_flags = map_mpic_senses[intspec[1] & mask];
1050         } else
1051                 *out_flags = IRQ_TYPE_NONE;
1052
1053         DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1054             intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1055
1056         return 0;
1057 }
1058
1059 static struct irq_host_ops mpic_host_ops = {
1060         .match = mpic_host_match,
1061         .map = mpic_host_map,
1062         .xlate = mpic_host_xlate,
1063 };
1064
1065 static int mpic_reset_prohibited(struct device_node *node)
1066 {
1067         return node && of_get_property(node, "pic-no-reset", NULL);
1068 }
1069
1070 /*
1071  * Exported functions
1072  */
1073
1074 struct mpic * __init mpic_alloc(struct device_node *node,
1075                                 phys_addr_t phys_addr,
1076                                 unsigned int flags,
1077                                 unsigned int isu_size,
1078                                 unsigned int irq_count,
1079                                 const char *name)
1080 {
1081         struct mpic     *mpic;
1082         u32             greg_feature;
1083         const char      *vers;
1084         int             i;
1085         int             intvec_top;
1086         u64             paddr = phys_addr;
1087
1088         mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1089         if (mpic == NULL)
1090                 return NULL;
1091
1092         mpic->name = name;
1093
1094         mpic->hc_irq = mpic_irq_chip;
1095         mpic->hc_irq.name = name;
1096         if (flags & MPIC_PRIMARY)
1097                 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1098 #ifdef CONFIG_MPIC_U3_HT_IRQS
1099         mpic->hc_ht_irq = mpic_irq_ht_chip;
1100         mpic->hc_ht_irq.name = name;
1101         if (flags & MPIC_PRIMARY)
1102                 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1103 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1104
1105 #ifdef CONFIG_SMP
1106         mpic->hc_ipi = mpic_ipi_chip;
1107         mpic->hc_ipi.name = name;
1108 #endif /* CONFIG_SMP */
1109
1110         mpic->flags = flags;
1111         mpic->isu_size = isu_size;
1112         mpic->irq_count = irq_count;
1113         mpic->num_sources = 0; /* so far */
1114
1115         if (flags & MPIC_LARGE_VECTORS)
1116                 intvec_top = 2047;
1117         else
1118                 intvec_top = 255;
1119
1120         mpic->timer_vecs[0] = intvec_top - 8;
1121         mpic->timer_vecs[1] = intvec_top - 7;
1122         mpic->timer_vecs[2] = intvec_top - 6;
1123         mpic->timer_vecs[3] = intvec_top - 5;
1124         mpic->ipi_vecs[0]   = intvec_top - 4;
1125         mpic->ipi_vecs[1]   = intvec_top - 3;
1126         mpic->ipi_vecs[2]   = intvec_top - 2;
1127         mpic->ipi_vecs[3]   = intvec_top - 1;
1128         mpic->spurious_vec  = intvec_top;
1129
1130         /* Check for "big-endian" in device-tree */
1131         if (node && of_get_property(node, "big-endian", NULL) != NULL)
1132                 mpic->flags |= MPIC_BIG_ENDIAN;
1133
1134         /* Look for protected sources */
1135         if (node) {
1136                 int psize;
1137                 unsigned int bits, mapsize;
1138                 const u32 *psrc =
1139                         of_get_property(node, "protected-sources", &psize);
1140                 if (psrc) {
1141                         psize /= 4;
1142                         bits = intvec_top + 1;
1143                         mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1144                         mpic->protected = kzalloc(mapsize, GFP_KERNEL);
1145                         BUG_ON(mpic->protected == NULL);
1146                         for (i = 0; i < psize; i++) {
1147                                 if (psrc[i] > intvec_top)
1148                                         continue;
1149                                 __set_bit(psrc[i], mpic->protected);
1150                         }
1151                 }
1152         }
1153
1154 #ifdef CONFIG_MPIC_WEIRD
1155         mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1156 #endif
1157
1158         /* default register type */
1159         mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1160                 mpic_access_mmio_be : mpic_access_mmio_le;
1161
1162         /* If no physical address is passed in, a device-node is mandatory */
1163         BUG_ON(paddr == 0 && node == NULL);
1164
1165         /* If no physical address passed in, check if it's dcr based */
1166         if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1167 #ifdef CONFIG_PPC_DCR
1168                 mpic->flags |= MPIC_USES_DCR;
1169                 mpic->reg_type = mpic_access_dcr;
1170 #else
1171                 BUG();
1172 #endif /* CONFIG_PPC_DCR */
1173         }
1174
1175         /* If the MPIC is not DCR based, and no physical address was passed
1176          * in, try to obtain one
1177          */
1178         if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1179                 const u32 *reg = of_get_property(node, "reg", NULL);
1180                 BUG_ON(reg == NULL);
1181                 paddr = of_translate_address(node, reg);
1182                 BUG_ON(paddr == OF_BAD_ADDR);
1183         }
1184
1185         /* Map the global registers */
1186         mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1187         mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1188
1189         /* Reset */
1190
1191         /* When using a device-node, reset requests are only honored if the MPIC
1192          * is allowed to reset.
1193          */
1194         if (mpic_reset_prohibited(node))
1195                 mpic->flags |= MPIC_NO_RESET;
1196
1197         if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
1198                 printk(KERN_DEBUG "mpic: Resetting\n");
1199                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1200                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1201                            | MPIC_GREG_GCONF_RESET);
1202                 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1203                        & MPIC_GREG_GCONF_RESET)
1204                         mb();
1205         }
1206
1207         /* CoreInt */
1208         if (flags & MPIC_ENABLE_COREINT)
1209                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1210                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1211                            | MPIC_GREG_GCONF_COREINT);
1212
1213         if (flags & MPIC_ENABLE_MCK)
1214                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1215                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1216                            | MPIC_GREG_GCONF_MCK);
1217
1218         /* Read feature register, calculate num CPUs and, for non-ISU
1219          * MPICs, num sources as well. On ISU MPICs, sources are counted
1220          * as ISUs are added
1221          */
1222         greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1223         mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1224                           >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1225         if (isu_size == 0) {
1226                 if (flags & MPIC_BROKEN_FRR_NIRQS)
1227                         mpic->num_sources = mpic->irq_count;
1228                 else
1229                         mpic->num_sources =
1230                                 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1231                                  >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1232         }
1233
1234         /* Map the per-CPU registers */
1235         for (i = 0; i < mpic->num_cpus; i++) {
1236                 mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
1237                          MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1238                          0x1000);
1239         }
1240
1241         /* Initialize main ISU if none provided */
1242         if (mpic->isu_size == 0) {
1243                 mpic->isu_size = mpic->num_sources;
1244                 mpic_map(mpic, node, paddr, &mpic->isus[0],
1245                          MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1246         }
1247         mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1248         mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1249
1250         mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
1251                                        isu_size ? isu_size : mpic->num_sources,
1252                                        &mpic_host_ops,
1253                                        flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1254         if (mpic->irqhost == NULL)
1255                 return NULL;
1256
1257         mpic->irqhost->host_data = mpic;
1258
1259         /* Display version */
1260         switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1261         case 1:
1262                 vers = "1.0";
1263                 break;
1264         case 2:
1265                 vers = "1.2";
1266                 break;
1267         case 3:
1268                 vers = "1.3";
1269                 break;
1270         default:
1271                 vers = "<unknown>";
1272                 break;
1273         }
1274         printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1275                " max %d CPUs\n",
1276                name, vers, (unsigned long long)paddr, mpic->num_cpus);
1277         printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1278                mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1279
1280         mpic->next = mpics;
1281         mpics = mpic;
1282
1283         if (flags & MPIC_PRIMARY) {
1284                 mpic_primary = mpic;
1285                 irq_set_default_host(mpic->irqhost);
1286         }
1287
1288         return mpic;
1289 }
1290
1291 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1292                             phys_addr_t paddr)
1293 {
1294         unsigned int isu_first = isu_num * mpic->isu_size;
1295
1296         BUG_ON(isu_num >= MPIC_MAX_ISU);
1297
1298         mpic_map(mpic, mpic->irqhost->of_node,
1299                  paddr, &mpic->isus[isu_num], 0,
1300                  MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1301
1302         if ((isu_first + mpic->isu_size) > mpic->num_sources)
1303                 mpic->num_sources = isu_first + mpic->isu_size;
1304 }
1305
1306 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1307 {
1308         mpic->senses = senses;
1309         mpic->senses_count = count;
1310 }
1311
1312 void __init mpic_init(struct mpic *mpic)
1313 {
1314         int i;
1315         int cpu;
1316
1317         BUG_ON(mpic->num_sources == 0);
1318
1319         printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1320
1321         /* Set current processor priority to max */
1322         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1323
1324         /* Initialize timers: just disable them all */
1325         for (i = 0; i < 4; i++) {
1326                 mpic_write(mpic->tmregs,
1327                            i * MPIC_INFO(TIMER_STRIDE) +
1328                            MPIC_INFO(TIMER_DESTINATION), 0);
1329                 mpic_write(mpic->tmregs,
1330                            i * MPIC_INFO(TIMER_STRIDE) +
1331                            MPIC_INFO(TIMER_VECTOR_PRI),
1332                            MPIC_VECPRI_MASK |
1333                            (mpic->timer_vecs[0] + i));
1334         }
1335
1336         /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1337         mpic_test_broken_ipi(mpic);
1338         for (i = 0; i < 4; i++) {
1339                 mpic_ipi_write(i,
1340                                MPIC_VECPRI_MASK |
1341                                (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1342                                (mpic->ipi_vecs[0] + i));
1343         }
1344
1345         /* Initialize interrupt sources */
1346         if (mpic->irq_count == 0)
1347                 mpic->irq_count = mpic->num_sources;
1348
1349         /* Do the HT PIC fixups on U3 broken mpic */
1350         DBG("MPIC flags: %x\n", mpic->flags);
1351         if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1352                 mpic_scan_ht_pics(mpic);
1353                 mpic_u3msi_init(mpic);
1354         }
1355
1356         mpic_pasemi_msi_init(mpic);
1357
1358         cpu = mpic_processor_id(mpic);
1359
1360         if (!(mpic->flags & MPIC_NO_RESET)) {
1361                 for (i = 0; i < mpic->num_sources; i++) {
1362                         /* start with vector = source number, and masked */
1363                         u32 vecpri = MPIC_VECPRI_MASK | i |
1364                                 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1365
1366                         /* check if protected */
1367                         if (mpic->protected && test_bit(i, mpic->protected))
1368                                 continue;
1369                         /* init hw */
1370                         mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1371                         mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1372                 }
1373         }
1374
1375         /* Init spurious vector */
1376         mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1377
1378         /* Disable 8259 passthrough, if supported */
1379         if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1380                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1381                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1382                            | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1383
1384         if (mpic->flags & MPIC_NO_BIAS)
1385                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1386                         mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1387                         | MPIC_GREG_GCONF_NO_BIAS);
1388
1389         /* Set current processor priority to 0 */
1390         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1391
1392 #ifdef CONFIG_PM
1393         /* allocate memory to save mpic state */
1394         mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1395                                   GFP_KERNEL);
1396         BUG_ON(mpic->save_data == NULL);
1397 #endif
1398 }
1399
1400 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1401 {
1402         u32 v;
1403
1404         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1405         v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1406         v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1407         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1408 }
1409
1410 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1411 {
1412         unsigned long flags;
1413         u32 v;
1414
1415         raw_spin_lock_irqsave(&mpic_lock, flags);
1416         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1417         if (enable)
1418                 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1419         else
1420                 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1421         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1422         raw_spin_unlock_irqrestore(&mpic_lock, flags);
1423 }
1424
1425 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1426 {
1427         struct mpic *mpic = mpic_find(irq);
1428         unsigned int src = virq_to_hw(irq);
1429         unsigned long flags;
1430         u32 reg;
1431
1432         if (!mpic)
1433                 return;
1434
1435         raw_spin_lock_irqsave(&mpic_lock, flags);
1436         if (mpic_is_ipi(mpic, irq)) {
1437                 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1438                         ~MPIC_VECPRI_PRIORITY_MASK;
1439                 mpic_ipi_write(src - mpic->ipi_vecs[0],
1440                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1441         } else {
1442                 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1443                         & ~MPIC_VECPRI_PRIORITY_MASK;
1444                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1445                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1446         }
1447         raw_spin_unlock_irqrestore(&mpic_lock, flags);
1448 }
1449
1450 void mpic_setup_this_cpu(void)
1451 {
1452 #ifdef CONFIG_SMP
1453         struct mpic *mpic = mpic_primary;
1454         unsigned long flags;
1455         u32 msk = 1 << hard_smp_processor_id();
1456         unsigned int i;
1457
1458         BUG_ON(mpic == NULL);
1459
1460         DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1461
1462         raw_spin_lock_irqsave(&mpic_lock, flags);
1463
1464         /* let the mpic know we want intrs. default affinity is 0xffffffff
1465          * until changed via /proc. That's how it's done on x86. If we want
1466          * it differently, then we should make sure we also change the default
1467          * values of irq_desc[].affinity in irq.c.
1468          */
1469         if (distribute_irqs) {
1470                 for (i = 0; i < mpic->num_sources ; i++)
1471                         mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1472                                 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1473         }
1474
1475         /* Set current processor priority to 0 */
1476         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1477
1478         raw_spin_unlock_irqrestore(&mpic_lock, flags);
1479 #endif /* CONFIG_SMP */
1480 }
1481
1482 int mpic_cpu_get_priority(void)
1483 {
1484         struct mpic *mpic = mpic_primary;
1485
1486         return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1487 }
1488
1489 void mpic_cpu_set_priority(int prio)
1490 {
1491         struct mpic *mpic = mpic_primary;
1492
1493         prio &= MPIC_CPU_TASKPRI_MASK;
1494         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1495 }
1496
1497 void mpic_teardown_this_cpu(int secondary)
1498 {
1499         struct mpic *mpic = mpic_primary;
1500         unsigned long flags;
1501         u32 msk = 1 << hard_smp_processor_id();
1502         unsigned int i;
1503
1504         BUG_ON(mpic == NULL);
1505
1506         DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1507         raw_spin_lock_irqsave(&mpic_lock, flags);
1508
1509         /* let the mpic know we don't want intrs.  */
1510         for (i = 0; i < mpic->num_sources ; i++)
1511                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1512                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1513
1514         /* Set current processor priority to max */
1515         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1516         /* We need to EOI the IPI since not all platforms reset the MPIC
1517          * on boot and new interrupts wouldn't get delivered otherwise.
1518          */
1519         mpic_eoi(mpic);
1520
1521         raw_spin_unlock_irqrestore(&mpic_lock, flags);
1522 }
1523
1524
1525 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1526 {
1527         u32 src;
1528
1529         src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1530 #ifdef DEBUG_LOW
1531         DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1532 #endif
1533         if (unlikely(src == mpic->spurious_vec)) {
1534                 if (mpic->flags & MPIC_SPV_EOI)
1535                         mpic_eoi(mpic);
1536                 return NO_IRQ;
1537         }
1538         if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1539                 if (printk_ratelimit())
1540                         printk(KERN_WARNING "%s: Got protected source %d !\n",
1541                                mpic->name, (int)src);
1542                 mpic_eoi(mpic);
1543                 return NO_IRQ;
1544         }
1545
1546         return irq_linear_revmap(mpic->irqhost, src);
1547 }
1548
1549 unsigned int mpic_get_one_irq(struct mpic *mpic)
1550 {
1551         return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1552 }
1553
1554 unsigned int mpic_get_irq(void)
1555 {
1556         struct mpic *mpic = mpic_primary;
1557
1558         BUG_ON(mpic == NULL);
1559
1560         return mpic_get_one_irq(mpic);
1561 }
1562
1563 unsigned int mpic_get_coreint_irq(void)
1564 {
1565 #ifdef CONFIG_BOOKE
1566         struct mpic *mpic = mpic_primary;
1567         u32 src;
1568
1569         BUG_ON(mpic == NULL);
1570
1571         src = mfspr(SPRN_EPR);
1572
1573         if (unlikely(src == mpic->spurious_vec)) {
1574                 if (mpic->flags & MPIC_SPV_EOI)
1575                         mpic_eoi(mpic);
1576                 return NO_IRQ;
1577         }
1578         if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1579                 if (printk_ratelimit())
1580                         printk(KERN_WARNING "%s: Got protected source %d !\n",
1581                                mpic->name, (int)src);
1582                 return NO_IRQ;
1583         }
1584
1585         return irq_linear_revmap(mpic->irqhost, src);
1586 #else
1587         return NO_IRQ;
1588 #endif
1589 }
1590
1591 unsigned int mpic_get_mcirq(void)
1592 {
1593         struct mpic *mpic = mpic_primary;
1594
1595         BUG_ON(mpic == NULL);
1596
1597         return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1598 }
1599
1600 #ifdef CONFIG_SMP
1601 void mpic_request_ipis(void)
1602 {
1603         struct mpic *mpic = mpic_primary;
1604         int i;
1605         BUG_ON(mpic == NULL);
1606
1607         printk(KERN_INFO "mpic: requesting IPIs...\n");
1608
1609         for (i = 0; i < 4; i++) {
1610                 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1611                                                        mpic->ipi_vecs[0] + i);
1612                 if (vipi == NO_IRQ) {
1613                         printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1614                         continue;
1615                 }
1616                 smp_request_message_ipi(vipi, i);
1617         }
1618 }
1619
1620 static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask)
1621 {
1622         struct mpic *mpic = mpic_primary;
1623
1624         BUG_ON(mpic == NULL);
1625
1626 #ifdef DEBUG_IPI
1627         DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1628 #endif
1629
1630         mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1631                        ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1632                        mpic_physmask(cpumask_bits(cpu_mask)[0]));
1633 }
1634
1635 void smp_mpic_message_pass(int target, int msg)
1636 {
1637         cpumask_var_t tmp;
1638
1639         /* make sure we're sending something that translates to an IPI */
1640         if ((unsigned int)msg > 3) {
1641                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1642                        smp_processor_id(), msg);
1643                 return;
1644         }
1645         switch (target) {
1646         case MSG_ALL:
1647                 mpic_send_ipi(msg, cpu_online_mask);
1648                 break;
1649         case MSG_ALL_BUT_SELF:
1650                 alloc_cpumask_var(&tmp, GFP_NOWAIT);
1651                 cpumask_andnot(tmp, cpu_online_mask,
1652                                cpumask_of(smp_processor_id()));
1653                 mpic_send_ipi(msg, tmp);
1654                 free_cpumask_var(tmp);
1655                 break;
1656         default:
1657                 mpic_send_ipi(msg, cpumask_of(target));
1658                 break;
1659         }
1660 }
1661
1662 int __init smp_mpic_probe(void)
1663 {
1664         int nr_cpus;
1665
1666         DBG("smp_mpic_probe()...\n");
1667
1668         nr_cpus = cpumask_weight(cpu_possible_mask);
1669
1670         DBG("nr_cpus: %d\n", nr_cpus);
1671
1672         if (nr_cpus > 1)
1673                 mpic_request_ipis();
1674
1675         return nr_cpus;
1676 }
1677
1678 void __devinit smp_mpic_setup_cpu(int cpu)
1679 {
1680         mpic_setup_this_cpu();
1681 }
1682
1683 void mpic_reset_core(int cpu)
1684 {
1685         struct mpic *mpic = mpic_primary;
1686         u32 pir;
1687         int cpuid = get_hard_smp_processor_id(cpu);
1688
1689         /* Set target bit for core reset */
1690         pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1691         pir |= (1 << cpuid);
1692         mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1693         mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1694
1695         /* Restore target bit after reset complete */
1696         pir &= ~(1 << cpuid);
1697         mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1698         mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1699 }
1700 #endif /* CONFIG_SMP */
1701
1702 #ifdef CONFIG_PM
1703 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1704 {
1705         struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1706         int i;
1707
1708         for (i = 0; i < mpic->num_sources; i++) {
1709                 mpic->save_data[i].vecprio =
1710                         mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1711                 mpic->save_data[i].dest =
1712                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1713         }
1714
1715         return 0;
1716 }
1717
1718 static int mpic_resume(struct sys_device *dev)
1719 {
1720         struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1721         int i;
1722
1723         for (i = 0; i < mpic->num_sources; i++) {
1724                 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1725                                mpic->save_data[i].vecprio);
1726                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1727                                mpic->save_data[i].dest);
1728
1729 #ifdef CONFIG_MPIC_U3_HT_IRQS
1730         if (mpic->fixups) {
1731                 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1732
1733                 if (fixup->base) {
1734                         /* we use the lowest bit in an inverted meaning */
1735                         if ((mpic->save_data[i].fixup_data & 1) == 0)
1736                                 continue;
1737
1738                         /* Enable and configure */
1739                         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1740
1741                         writel(mpic->save_data[i].fixup_data & ~1,
1742                                fixup->base + 4);
1743                 }
1744         }
1745 #endif
1746         } /* end for loop */
1747
1748         return 0;
1749 }
1750 #endif
1751
1752 static struct sysdev_class mpic_sysclass = {
1753 #ifdef CONFIG_PM
1754         .resume = mpic_resume,
1755         .suspend = mpic_suspend,
1756 #endif
1757         .name = "mpic",
1758 };
1759
1760 static int mpic_init_sys(void)
1761 {
1762         struct mpic *mpic = mpics;
1763         int error, id = 0;
1764
1765         error = sysdev_class_register(&mpic_sysclass);
1766
1767         while (mpic && !error) {
1768                 mpic->sysdev.cls = &mpic_sysclass;
1769                 mpic->sysdev.id = id++;
1770                 error = sysdev_register(&mpic->sysdev);
1771                 mpic = mpic->next;
1772         }
1773         return error;
1774 }
1775
1776 device_initcall(mpic_init_sys);