2 * Freescale MPC85xx/MPC86xx RapidIO support
4 * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc.
5 * Zhang Wei <wei.zhang@freescale.com>
7 * Copyright 2005 MontaVista Software, Inc.
8 * Matt Porter <mporter@kernel.crashing.org>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/interrupt.h>
21 #include <linux/rio.h>
22 #include <linux/rio_drv.h>
26 /* RapidIO definition irq, which read from OF-tree */
27 #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq)
28 #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq)
29 #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq)
31 #define RIO_REGS_BASE (CCSRBAR + 0xc0000)
32 #define RIO_ATMU_REGS_OFFSET 0x10c00
33 #define RIO_MSG_REGS_OFFSET 0x11000
34 #define RIO_MAINT_WIN_SIZE 0x400000
35 #define RIO_DBELL_WIN_SIZE 0x1000
37 #define RIO_MSG_OMR_MUI 0x00000002
38 #define RIO_MSG_OSR_TE 0x00000080
39 #define RIO_MSG_OSR_QOI 0x00000020
40 #define RIO_MSG_OSR_QFI 0x00000010
41 #define RIO_MSG_OSR_MUB 0x00000004
42 #define RIO_MSG_OSR_EOMI 0x00000002
43 #define RIO_MSG_OSR_QEI 0x00000001
45 #define RIO_MSG_IMR_MI 0x00000002
46 #define RIO_MSG_ISR_TE 0x00000080
47 #define RIO_MSG_ISR_QFI 0x00000010
48 #define RIO_MSG_ISR_DIQI 0x00000001
50 #define RIO_MSG_DESC_SIZE 32
51 #define RIO_MSG_BUFFER_SIZE 4096
52 #define RIO_MIN_TX_RING_SIZE 2
53 #define RIO_MAX_TX_RING_SIZE 2048
54 #define RIO_MIN_RX_RING_SIZE 2
55 #define RIO_MAX_RX_RING_SIZE 2048
57 #define DOORBELL_DMR_DI 0x00000002
58 #define DOORBELL_DSR_TE 0x00000080
59 #define DOORBELL_DSR_QFI 0x00000010
60 #define DOORBELL_DSR_DIQI 0x00000001
61 #define DOORBELL_TID_OFFSET 0x03
62 #define DOORBELL_SID_OFFSET 0x05
63 #define DOORBELL_INFO_OFFSET 0x06
65 #define DOORBELL_MESSAGE_SIZE 0x08
66 #define DBELL_SID(x) (*(u8 *)(x + DOORBELL_SID_OFFSET))
67 #define DBELL_TID(x) (*(u8 *)(x + DOORBELL_TID_OFFSET))
68 #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
70 struct rio_atmu_regs {
123 struct rio_dbell_ring {
128 struct rio_msg_tx_ring {
131 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
132 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
138 struct rio_msg_rx_ring {
141 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
148 void __iomem *regs_win;
149 struct rio_atmu_regs __iomem *atmu_regs;
150 struct rio_atmu_regs __iomem *maint_atmu_regs;
151 struct rio_atmu_regs __iomem *dbell_atmu_regs;
152 void __iomem *dbell_win;
153 void __iomem *maint_win;
154 struct rio_msg_regs __iomem *msg_regs;
155 struct rio_dbell_ring dbell_ring;
156 struct rio_msg_tx_ring msg_tx_ring;
157 struct rio_msg_rx_ring msg_rx_ring;
164 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
165 * @index: ID of RapidIO interface
166 * @destid: Destination ID of target device
167 * @data: 16-bit info field of RapidIO doorbell message
169 * Sends a MPC85xx doorbell message. Returns %0 on success or
170 * %-EINVAL on failure.
172 static int fsl_rio_doorbell_send(struct rio_mport *mport,
173 int index, u16 destid, u16 data)
175 struct rio_priv *priv = mport->priv;
176 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
177 index, destid, data);
178 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
179 out_be16(priv->dbell_win, data);
185 * fsl_local_config_read - Generate a MPC85xx local config space read
186 * @index: ID of RapdiIO interface
187 * @offset: Offset into configuration space
188 * @len: Length (in bytes) of the maintenance transaction
189 * @data: Value to be read into
191 * Generates a MPC85xx local configuration space read. Returns %0 on
192 * success or %-EINVAL on failure.
194 static int fsl_local_config_read(struct rio_mport *mport,
195 int index, u32 offset, int len, u32 *data)
197 struct rio_priv *priv = mport->priv;
198 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
200 *data = in_be32(priv->regs_win + offset);
206 * fsl_local_config_write - Generate a MPC85xx local config space write
207 * @index: ID of RapdiIO interface
208 * @offset: Offset into configuration space
209 * @len: Length (in bytes) of the maintenance transaction
210 * @data: Value to be written
212 * Generates a MPC85xx local configuration space write. Returns %0 on
213 * success or %-EINVAL on failure.
215 static int fsl_local_config_write(struct rio_mport *mport,
216 int index, u32 offset, int len, u32 data)
218 struct rio_priv *priv = mport->priv;
220 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
221 index, offset, data);
222 out_be32(priv->regs_win + offset, data);
228 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
229 * @index: ID of RapdiIO interface
230 * @destid: Destination ID of transaction
231 * @hopcount: Number of hops to target device
232 * @offset: Offset into configuration space
233 * @len: Length (in bytes) of the maintenance transaction
234 * @val: Location to be read into
236 * Generates a MPC85xx read maintenance transaction. Returns %0 on
237 * success or %-EINVAL on failure.
240 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
241 u8 hopcount, u32 offset, int len, u32 *val)
243 struct rio_priv *priv = mport->priv;
247 ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
248 index, destid, hopcount, offset, len);
249 out_be32(&priv->maint_atmu_regs->rowtar,
250 (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
252 data = (u8 *) priv->maint_win + offset;
255 *val = in_8((u8 *) data);
258 *val = in_be16((u16 *) data);
261 *val = in_be32((u32 *) data);
269 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
270 * @index: ID of RapdiIO interface
271 * @destid: Destination ID of transaction
272 * @hopcount: Number of hops to target device
273 * @offset: Offset into configuration space
274 * @len: Length (in bytes) of the maintenance transaction
275 * @val: Value to be written
277 * Generates an MPC85xx write maintenance transaction. Returns %0 on
278 * success or %-EINVAL on failure.
281 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
282 u8 hopcount, u32 offset, int len, u32 val)
284 struct rio_priv *priv = mport->priv;
287 ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
288 index, destid, hopcount, offset, len, val);
289 out_be32(&priv->maint_atmu_regs->rowtar,
290 (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
292 data = (u8 *) priv->maint_win + offset;
295 out_8((u8 *) data, val);
298 out_be16((u16 *) data, val);
301 out_be32((u32 *) data, val);
309 * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
310 * @mport: Master port with outbound message queue
311 * @rdev: Target of outbound message
312 * @mbox: Outbound mailbox
313 * @buffer: Message to add to outbound queue
314 * @len: Length of message
316 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
317 * %0 on success or %-EINVAL on failure.
320 rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
321 void *buffer, size_t len)
323 struct rio_priv *priv = mport->priv;
325 struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
326 + priv->msg_tx_ring.tx_slot;
330 ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
331 rdev->destid, mbox, (int)buffer, len);
333 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
338 /* Copy and clear rest of buffer */
339 memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
341 if (len < (RIO_MAX_MSG_SIZE - 4))
342 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
343 + len, 0, RIO_MAX_MSG_SIZE - len);
345 /* Set mbox field for message */
346 desc->dport = mbox & 0x3;
348 /* Enable EOMI interrupt, set priority, and set destid */
349 desc->dattr = 0x28000000 | (rdev->destid << 2);
351 /* Set transfer size aligned to next power of 2 (in double words) */
352 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
354 /* Set snooping and source buffer address */
355 desc->saddr = 0x00000004
356 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
358 /* Increment enqueue pointer */
359 omr = in_be32(&priv->msg_regs->omr);
360 out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
362 /* Go to next descriptor */
363 if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
364 priv->msg_tx_ring.tx_slot = 0;
370 EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
373 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
374 * @irq: Linux interrupt number
375 * @dev_instance: Pointer to interrupt-specific data
377 * Handles outbound message interrupts. Executes a register outbound
378 * mailbox event handler and acks the interrupt occurrence.
381 fsl_rio_tx_handler(int irq, void *dev_instance)
384 struct rio_mport *port = (struct rio_mport *)dev_instance;
385 struct rio_priv *priv = port->priv;
387 osr = in_be32(&priv->msg_regs->osr);
389 if (osr & RIO_MSG_OSR_TE) {
390 pr_info("RIO: outbound message transmission error\n");
391 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
395 if (osr & RIO_MSG_OSR_QOI) {
396 pr_info("RIO: outbound message queue overflow\n");
397 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
401 if (osr & RIO_MSG_OSR_EOMI) {
402 u32 dqp = in_be32(&priv->msg_regs->odqdpar);
403 int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
404 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
407 /* Ack the end-of-message interrupt */
408 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
416 * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
417 * @mport: Master port implementing the outbound message unit
418 * @dev_id: Device specific pointer to pass on event
419 * @mbox: Mailbox to open
420 * @entries: Number of entries in the outbound mailbox ring
422 * Initializes buffer ring, request the outbound message interrupt,
423 * and enables the outbound message unit. Returns %0 on success and
424 * %-EINVAL or %-ENOMEM on failure.
426 int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
429 struct rio_priv *priv = mport->priv;
431 if ((entries < RIO_MIN_TX_RING_SIZE) ||
432 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
437 /* Initialize shadow copy ring */
438 priv->msg_tx_ring.dev_id = dev_id;
439 priv->msg_tx_ring.size = entries;
441 for (i = 0; i < priv->msg_tx_ring.size; i++) {
442 priv->msg_tx_ring.virt_buffer[i] =
443 dma_alloc_coherent(NULL, RIO_MSG_BUFFER_SIZE,
444 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
445 if (!priv->msg_tx_ring.virt_buffer[i]) {
447 for (j = 0; j < priv->msg_tx_ring.size; j++)
448 if (priv->msg_tx_ring.virt_buffer[j])
449 dma_free_coherent(NULL,
459 /* Initialize outbound message descriptor ring */
460 priv->msg_tx_ring.virt = dma_alloc_coherent(NULL,
461 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
462 &priv->msg_tx_ring.phys, GFP_KERNEL);
463 if (!priv->msg_tx_ring.virt) {
467 memset(priv->msg_tx_ring.virt, 0,
468 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
469 priv->msg_tx_ring.tx_slot = 0;
471 /* Point dequeue/enqueue pointers at first entry in ring */
472 out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
473 out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
475 /* Configure for snooping */
476 out_be32(&priv->msg_regs->osar, 0x00000004);
478 /* Clear interrupt status */
479 out_be32(&priv->msg_regs->osr, 0x000000b3);
481 /* Hook up outbound message handler */
482 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
483 "msg_tx", (void *)mport);
488 * Configure outbound message unit
490 * Interrupts (all enabled, except QEIE)
494 out_be32(&priv->msg_regs->omr, 0x00100220);
496 /* Set number of entries */
497 out_be32(&priv->msg_regs->omr,
498 in_be32(&priv->msg_regs->omr) |
499 ((get_bitmask_order(entries) - 2) << 12));
501 /* Now enable the unit */
502 out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
508 dma_free_coherent(NULL, priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
509 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
512 for (i = 0; i < priv->msg_tx_ring.size; i++)
513 dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
514 priv->msg_tx_ring.virt_buffer[i],
515 priv->msg_tx_ring.phys_buffer[i]);
521 * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
522 * @mport: Master port implementing the outbound message unit
523 * @mbox: Mailbox to close
525 * Disables the outbound message unit, free all buffers, and
526 * frees the outbound message interrupt.
528 void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
530 struct rio_priv *priv = mport->priv;
531 /* Disable inbound message unit */
532 out_be32(&priv->msg_regs->omr, 0);
535 dma_free_coherent(NULL, priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
536 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
539 free_irq(IRQ_RIO_TX(mport), (void *)mport);
543 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
544 * @irq: Linux interrupt number
545 * @dev_instance: Pointer to interrupt-specific data
547 * Handles inbound message interrupts. Executes a registered inbound
548 * mailbox event handler and acks the interrupt occurrence.
551 fsl_rio_rx_handler(int irq, void *dev_instance)
554 struct rio_mport *port = (struct rio_mport *)dev_instance;
555 struct rio_priv *priv = port->priv;
557 isr = in_be32(&priv->msg_regs->isr);
559 if (isr & RIO_MSG_ISR_TE) {
560 pr_info("RIO: inbound message reception error\n");
561 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
565 /* XXX Need to check/dispatch until queue empty */
566 if (isr & RIO_MSG_ISR_DIQI) {
568 * We implement *only* mailbox 0, but can receive messages
569 * for any mailbox/letter to that mailbox destination. So,
570 * make the callback with an unknown/invalid mailbox number
573 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
575 /* Ack the queueing interrupt */
576 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
584 * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
585 * @mport: Master port implementing the inbound message unit
586 * @dev_id: Device specific pointer to pass on event
587 * @mbox: Mailbox to open
588 * @entries: Number of entries in the inbound mailbox ring
590 * Initializes buffer ring, request the inbound message interrupt,
591 * and enables the inbound message unit. Returns %0 on success
592 * and %-EINVAL or %-ENOMEM on failure.
594 int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
597 struct rio_priv *priv = mport->priv;
599 if ((entries < RIO_MIN_RX_RING_SIZE) ||
600 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
605 /* Initialize client buffer ring */
606 priv->msg_rx_ring.dev_id = dev_id;
607 priv->msg_rx_ring.size = entries;
608 priv->msg_rx_ring.rx_slot = 0;
609 for (i = 0; i < priv->msg_rx_ring.size; i++)
610 priv->msg_rx_ring.virt_buffer[i] = NULL;
612 /* Initialize inbound message ring */
613 priv->msg_rx_ring.virt = dma_alloc_coherent(NULL,
614 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
615 &priv->msg_rx_ring.phys, GFP_KERNEL);
616 if (!priv->msg_rx_ring.virt) {
621 /* Point dequeue/enqueue pointers at first entry in ring */
622 out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
623 out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
625 /* Clear interrupt status */
626 out_be32(&priv->msg_regs->isr, 0x00000091);
628 /* Hook up inbound message handler */
629 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
630 "msg_rx", (void *)mport);
632 dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
633 priv->msg_tx_ring.virt_buffer[i],
634 priv->msg_tx_ring.phys_buffer[i]);
639 * Configure inbound message unit:
641 * 4KB max message size
642 * Unmask all interrupt sources
645 out_be32(&priv->msg_regs->imr, 0x001b0060);
647 /* Set number of queue entries */
648 setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
650 /* Now enable the unit */
651 setbits32(&priv->msg_regs->imr, 0x1);
658 * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
659 * @mport: Master port implementing the inbound message unit
660 * @mbox: Mailbox to close
662 * Disables the inbound message unit, free all buffers, and
663 * frees the inbound message interrupt.
665 void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
667 struct rio_priv *priv = mport->priv;
668 /* Disable inbound message unit */
669 out_be32(&priv->msg_regs->imr, 0);
672 dma_free_coherent(NULL, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
673 priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
676 free_irq(IRQ_RIO_RX(mport), (void *)mport);
680 * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
681 * @mport: Master port implementing the inbound message unit
682 * @mbox: Inbound mailbox number
683 * @buf: Buffer to add to inbound queue
685 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
686 * %0 on success or %-EINVAL on failure.
688 int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
691 struct rio_priv *priv = mport->priv;
693 pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
694 priv->msg_rx_ring.rx_slot);
696 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
698 "RIO: error adding inbound buffer %d, buffer exists\n",
699 priv->msg_rx_ring.rx_slot);
704 priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
705 if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
706 priv->msg_rx_ring.rx_slot = 0;
712 EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
715 * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
716 * @mport: Master port implementing the inbound message unit
717 * @mbox: Inbound mailbox number
719 * Gets the next available inbound message from the inbound message queue.
720 * A pointer to the message is returned on success or NULL on failure.
722 void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
724 struct rio_priv *priv = mport->priv;
725 u32 phys_buf, virt_buf;
729 phys_buf = in_be32(&priv->msg_regs->ifqdpar);
731 /* If no more messages, then bail out */
732 if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
735 virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
736 - priv->msg_rx_ring.phys);
737 buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
738 buf = priv->msg_rx_ring.virt_buffer[buf_idx];
742 "RIO: inbound message copy failed, no buffers\n");
746 /* Copy max message size, caller is expected to allocate that big */
747 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
749 /* Clear the available buffer */
750 priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
753 setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
759 EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
762 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
763 * @irq: Linux interrupt number
764 * @dev_instance: Pointer to interrupt-specific data
766 * Handles doorbell interrupts. Parses a list of registered
767 * doorbell event handlers and executes a matching event handler.
770 fsl_rio_dbell_handler(int irq, void *dev_instance)
773 struct rio_mport *port = (struct rio_mport *)dev_instance;
774 struct rio_priv *priv = port->priv;
776 dsr = in_be32(&priv->msg_regs->dsr);
778 if (dsr & DOORBELL_DSR_TE) {
779 pr_info("RIO: doorbell reception error\n");
780 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
784 if (dsr & DOORBELL_DSR_QFI) {
785 pr_info("RIO: doorbell queue full\n");
786 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
790 /* XXX Need to check/dispatch until queue empty */
791 if (dsr & DOORBELL_DSR_DIQI) {
793 (u32) priv->dbell_ring.virt +
794 (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
795 struct rio_dbell *dbell;
799 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
800 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
802 list_for_each_entry(dbell, &port->dbells, node) {
803 if ((dbell->res->start <= DBELL_INF(dmsg)) &&
804 (dbell->res->end >= DBELL_INF(dmsg))) {
810 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
814 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
815 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
817 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
818 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
826 * fsl_rio_doorbell_init - MPC85xx doorbell interface init
827 * @mport: Master port implementing the inbound doorbell unit
829 * Initializes doorbell unit hardware and inbound DMA buffer
830 * ring. Called from fsl_rio_setup(). Returns %0 on success
831 * or %-ENOMEM on failure.
833 static int fsl_rio_doorbell_init(struct rio_mport *mport)
835 struct rio_priv *priv = mport->priv;
838 /* Map outbound doorbell window immediately after maintenance window */
839 priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
841 if (!priv->dbell_win) {
843 "RIO: unable to map outbound doorbell window\n");
848 /* Initialize inbound doorbells */
849 priv->dbell_ring.virt = dma_alloc_coherent(NULL, 512 *
850 DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
851 if (!priv->dbell_ring.virt) {
852 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
854 iounmap(priv->dbell_win);
858 /* Point dequeue/enqueue pointers at first entry in ring */
859 out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
860 out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
862 /* Clear interrupt status */
863 out_be32(&priv->msg_regs->dsr, 0x00000091);
865 /* Hook up doorbell handler */
866 rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
867 "dbell_rx", (void *)mport);
869 iounmap(priv->dbell_win);
870 dma_free_coherent(NULL, 512 * DOORBELL_MESSAGE_SIZE,
871 priv->dbell_ring.virt, priv->dbell_ring.phys);
873 "MPC85xx RIO: unable to request inbound doorbell irq");
877 /* Configure doorbells for snooping, 512 entries, and enable */
878 out_be32(&priv->msg_regs->dmr, 0x00108161);
884 static char *cmdline = NULL;
886 static int fsl_rio_get_hdid(int index)
888 /* XXX Need to parse multiple entries in some format */
892 return simple_strtol(cmdline, NULL, 0);
895 static int fsl_rio_get_cmdline(char *s)
904 __setup("riohdid=", fsl_rio_get_cmdline);
907 * fsl_rio_setup - Setup MPC85xx RapidIO interface
908 * @law_start: Starting physical address of RapidIO LAW
909 * @law_size: Size of RapidIO LAW
911 * Initializes MPC85xx RapidIO hardware interface, configures
912 * master port with system-specific info, and registers the
913 * master port with the RapidIO subsystem.
915 void fsl_rio_setup(int law_start, int law_size)
918 struct rio_mport *port;
919 struct rio_priv *priv = NULL;
922 ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
923 ops->lcread = fsl_local_config_read;
924 ops->lcwrite = fsl_local_config_write;
925 ops->cread = fsl_rio_config_read;
926 ops->cwrite = fsl_rio_config_write;
927 ops->dsend = fsl_rio_doorbell_send;
929 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
933 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
935 printk(KERN_ERR "Can't alloc memory for 'priv'\n");
940 INIT_LIST_HEAD(&port->dbells);
941 port->iores.start = law_start;
942 port->iores.end = law_start + law_size;
943 port->iores.flags = IORESOURCE_MEM;
945 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
946 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
947 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
948 strcpy(port->name, "RIO0 mport");
951 port->host_deviceid = fsl_rio_get_hdid(port->id);
954 rio_register_mport(port);
956 priv->regs_win = ioremap(RIO_REGS_BASE, 0x20000);
957 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
958 + RIO_ATMU_REGS_OFFSET);
959 priv->maint_atmu_regs = priv->atmu_regs + 1;
960 priv->dbell_atmu_regs = priv->atmu_regs + 2;
961 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win
962 + RIO_MSG_REGS_OFFSET);
964 /* Configure maintenance transaction window */
965 out_be32(&priv->maint_atmu_regs->rowbar, 0x000c0000);
966 out_be32(&priv->maint_atmu_regs->rowar, 0x80077015);
968 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
970 /* Configure outbound doorbell window */
971 out_be32(&priv->dbell_atmu_regs->rowbar, 0x000c0400);
972 out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b);
973 fsl_rio_doorbell_init(port);
978 iounmap(priv->regs_win);