2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/bootmem.h>
26 #include <linux/memblock.h>
27 #include <linux/log2.h>
28 #include <linux/slab.h>
32 #include <asm/pci-bridge.h>
33 #include <asm/machdep.h>
34 #include <sysdev/fsl_soc.h>
35 #include <sysdev/fsl_pci.h>
37 static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
39 static void quirk_fsl_pcie_header(struct pci_dev *dev)
43 /* if we aren't a PCIe don't bother */
44 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
47 /* if we aren't in host mode don't bother */
48 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
49 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
52 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
53 fsl_pcie_bus_fixup = 1;
57 static int __init fsl_pcie_check_link(struct pci_controller *hose)
61 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
62 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
63 if (val < PCIE_LTSSM_L0)
66 struct ccsr_pci __iomem *pci = hose->private_data;
67 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
68 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
69 >> PEX_CSR0_LTSSM_SHIFT;
70 if (val != PEX_CSR0_LTSSM_L0)
77 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
79 #define MAX_PHYS_ADDR_BITS 40
80 static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
82 static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
84 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
88 * Fixup PCI devices that are able to DMA to above the physical
89 * address width of the SoC such that we can address any internal
90 * SoC address from across PCI if needed
92 if ((dev->bus == &pci_bus_type) &&
93 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
94 set_dma_ops(dev, &dma_direct_ops);
95 set_dma_offset(dev, pci64_dma_offset);
98 *dev->dma_mask = dma_mask;
102 static int setup_one_atmu(struct ccsr_pci __iomem *pci,
103 unsigned int index, const struct resource *res,
104 resource_size_t offset)
106 resource_size_t pci_addr = res->start - offset;
107 resource_size_t phys_addr = res->start;
108 resource_size_t size = resource_size(res);
109 u32 flags = 0x80044000; /* enable & mem R/W */
112 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
113 (u64)res->start, (u64)size);
115 if (res->flags & IORESOURCE_PREFETCH)
116 flags |= 0x10000000; /* enable relaxed ordering */
118 for (i = 0; size > 0; i++) {
119 unsigned int bits = min(ilog2(size),
120 __ffs(pci_addr | phys_addr));
125 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
126 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
127 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
128 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
130 pci_addr += (resource_size_t)1U << bits;
131 phys_addr += (resource_size_t)1U << bits;
132 size -= (resource_size_t)1U << bits;
138 /* atmu setup for fsl pci/pcie controller */
139 static void setup_pci_atmu(struct pci_controller *hose)
141 struct ccsr_pci __iomem *pci = hose->private_data;
142 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
143 u64 mem, sz, paddr_hi = 0;
144 u64 paddr_lo = ULLONG_MAX;
145 u32 pcicsrbar = 0, pcicsrbar_sz;
146 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
147 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
148 const char *name = hose->dn->full_name;
152 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
153 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
160 /* Disable all windows (except powar0 since it's ignored) */
161 for(i = 1; i < 5; i++)
162 out_be32(&pci->pow[i].powar, 0);
163 for (i = start_idx; i < end_idx; i++)
164 out_be32(&pci->piw[i].piwar, 0);
166 /* Setup outbound MEM window */
167 for(i = 0, j = 1; i < 3; i++) {
168 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
171 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
172 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
174 n = setup_one_atmu(pci, j, &hose->mem_resources[i],
175 hose->pci_mem_offset);
177 if (n < 0 || j >= 5) {
178 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
179 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
184 /* Setup outbound IO window */
185 if (hose->io_resource.flags & IORESOURCE_IO) {
187 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
189 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
190 "phy base 0x%016llx.\n",
191 (u64)hose->io_resource.start,
192 (u64)resource_size(&hose->io_resource),
193 (u64)hose->io_base_phys);
194 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
195 out_be32(&pci->pow[j].potear, 0);
196 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
198 out_be32(&pci->pow[j].powar, 0x80088000
199 | (ilog2(hose->io_resource.end
200 - hose->io_resource.start + 1) - 1));
204 /* convert to pci address space */
205 paddr_hi -= hose->pci_mem_offset;
206 paddr_lo -= hose->pci_mem_offset;
208 if (paddr_hi == paddr_lo) {
209 pr_err("%s: No outbound window space\n", name);
214 pr_err("%s: No space for inbound window\n", name);
218 /* setup PCSRBAR/PEXCSRBAR */
219 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
220 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
221 pcicsrbar_sz = ~pcicsrbar_sz + 1;
223 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
224 (paddr_lo > 0x100000000ull))
225 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
227 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
228 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
230 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
232 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
234 /* Setup inbound mem window */
235 mem = memblock_end_of_DRAM();
238 * The msi-address-64 property, if it exists, indicates the physical
239 * address of the MSIIR register. Normally, this register is located
240 * inside CCSR, so the ATMU that covers all of CCSR is used. But if
241 * this property exists, then we normally need to create a new ATMU
242 * for it. For now, however, we cheat. The only entity that creates
243 * this property is the Freescale hypervisor, and the address is
244 * specified in the partition configuration. Typically, the address
245 * is located in the page immediately after the end of DDR. If so, we
246 * can avoid allocating a new ATMU by extending the DDR ATMU by one
249 reg = of_get_property(hose->dn, "msi-address-64", &len);
250 if (reg && (len == sizeof(u64))) {
251 u64 address = be64_to_cpup(reg);
253 if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
254 pr_info("%s: extending DDR ATMU to cover MSIIR", name);
257 /* TODO: Create a new ATMU for MSIIR */
258 pr_warn("%s: msi-address-64 address of %llx is "
259 "unsupported\n", name, address);
263 sz = min(mem, paddr_lo);
266 /* PCIe can overmap inbound & outbound since RX & TX are separated */
267 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
268 /* Size window to exact size if power-of-two or one size up */
269 if ((1ull << mem_log) != mem) {
270 if ((1ull << mem_log) > mem)
271 pr_info("%s: Setting PCI inbound window "
272 "greater than memory size\n", name);
276 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
278 /* Setup inbound memory window */
279 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
280 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
281 out_be32(&pci->piw[win_idx].piwar, piwar);
284 hose->dma_window_base_cur = 0x00000000;
285 hose->dma_window_size = (resource_size_t)sz;
288 * if we have >4G of memory setup second PCI inbound window to
289 * let devices that are 64-bit address capable to work w/o
290 * SWIOTLB and access the full range of memory
293 mem_log = ilog2(mem);
295 /* Size window up if we dont fit in exact power-of-2 */
296 if ((1ull << mem_log) != mem)
299 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
301 /* Setup inbound memory window */
302 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
303 out_be32(&pci->piw[win_idx].piwbear,
304 pci64_dma_offset >> 44);
305 out_be32(&pci->piw[win_idx].piwbar,
306 pci64_dma_offset >> 12);
307 out_be32(&pci->piw[win_idx].piwar, piwar);
310 * install our own dma_set_mask handler to fixup dma_ops
313 ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
315 pr_info("%s: Setup 64-bit PCI DMA window\n", name);
320 /* Setup inbound memory window */
321 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
322 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
323 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
326 paddr += 1ull << mem_log;
327 sz -= 1ull << mem_log;
331 piwar |= (mem_log - 1);
333 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
334 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
335 out_be32(&pci->piw[win_idx].piwar, piwar);
338 paddr += 1ull << mem_log;
341 hose->dma_window_base_cur = 0x00000000;
342 hose->dma_window_size = (resource_size_t)paddr;
345 if (hose->dma_window_size < mem) {
346 #ifndef CONFIG_SWIOTLB
347 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
348 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
351 /* adjusting outbound windows could reclaim space in mem map */
352 if (paddr_hi < 0xffffffffull)
353 pr_warning("%s: WARNING: Outbound window cfg leaves "
354 "gaps in memory map. Adjusting the memory map "
355 "could reduce unnecessary bounce buffering.\n",
358 pr_info("%s: DMA window size is 0x%llx\n", name,
359 (u64)hose->dma_window_size);
366 static void __init setup_pci_cmd(struct pci_controller *hose)
371 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
372 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
374 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
376 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
378 int pci_x_cmd = cap_x + PCI_X_CMD;
379 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
380 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
381 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
383 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
387 void fsl_pcibios_fixup_bus(struct pci_bus *bus)
389 struct pci_controller *hose = pci_bus_to_host(bus);
390 int i, is_pcie = 0, no_link;
392 /* The root complex bridge comes up with bogus resources,
393 * we copy the PHB ones in.
395 * With the current generic PCI code, the PHB bus no longer
396 * has bus->resource[0..4] set, so things are a bit more
400 if (fsl_pcie_bus_fixup)
401 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
402 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
404 if (bus->parent == hose->bus && (is_pcie || no_link)) {
405 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
406 struct resource *res = bus->resource[i];
407 struct resource *par;
412 par = &hose->io_resource;
414 par = &hose->mem_resources[i-1];
417 res->start = par ? par->start : 0;
418 res->end = par ? par->end : 0;
419 res->flags = par ? par->flags : 0;
424 int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
427 struct pci_controller *hose;
428 struct resource rsrc;
429 const int *bus_range;
431 struct device_node *dev;
432 struct ccsr_pci __iomem *pci;
434 dev = pdev->dev.of_node;
436 if (!of_device_is_available(dev)) {
437 pr_warning("%s: disabled\n", dev->full_name);
441 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
443 /* Fetch host bridge registers address */
444 if (of_address_to_resource(dev, 0, &rsrc)) {
445 printk(KERN_WARNING "Can't get pci register base!");
449 /* Get bus range if any */
450 bus_range = of_get_property(dev, "bus-range", &len);
451 if (bus_range == NULL || len < 2 * sizeof(int))
452 printk(KERN_WARNING "Can't get bus-range for %s, assume"
453 " bus 0\n", dev->full_name);
455 pci_add_flags(PCI_REASSIGN_ALL_BUS);
456 hose = pcibios_alloc_controller(dev);
460 /* set platform device as the parent */
461 hose->parent = &pdev->dev;
462 hose->first_busno = bus_range ? bus_range[0] : 0x0;
463 hose->last_busno = bus_range ? bus_range[1] : 0xff;
465 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
466 (u64)rsrc.start, (u64)resource_size(&rsrc));
468 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
469 if (!hose->private_data)
472 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
473 PPC_INDIRECT_TYPE_BIG_ENDIAN);
475 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
476 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
478 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
479 /* For PCIE read HEADER_TYPE to identify controler mode */
480 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
481 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
485 /* For PCI read PROG to identify controller mode */
486 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
487 if ((progif & 1) == 1)
493 /* check PCI express link status */
494 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
495 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
496 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
497 if (fsl_pcie_check_link(hose))
498 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
501 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
502 "Firmware bus number: %d->%d\n",
503 (unsigned long long)rsrc.start, hose->first_busno,
506 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
507 hose, hose->cfg_addr, hose->cfg_data);
509 /* Interpret the "ranges" property */
510 /* This also maps the I/O region and sets isa_io/mem_base */
511 pci_process_bridge_OF_ranges(hose, dev, is_primary);
513 /* Setup PEX window registers */
514 setup_pci_atmu(hose);
519 iounmap(hose->private_data);
520 /* unmap cfg_data & cfg_addr separately if not on same page */
521 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
522 ((unsigned long)hose->cfg_addr & PAGE_MASK))
523 iounmap(hose->cfg_data);
524 iounmap(hose->cfg_addr);
525 pcibios_free_controller(hose);
528 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
530 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
532 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
533 struct mpc83xx_pcie_priv {
534 void __iomem *cfg_type0;
535 void __iomem *cfg_type1;
539 struct pex_inbound_window {
547 * With the convention of u-boot, the PCIE outbound window 0 serves
548 * as configuration transactions outbound.
550 #define PEX_OUTWIN0_BAR 0xCA4
551 #define PEX_OUTWIN0_TAL 0xCA8
552 #define PEX_OUTWIN0_TAH 0xCAC
553 #define PEX_RC_INWIN_BASE 0xE60
554 #define PEX_RCIWARn_EN 0x1
556 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
558 struct pci_controller *hose = pci_bus_to_host(bus);
560 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
561 return PCIBIOS_DEVICE_NOT_FOUND;
563 * Workaround for the HW bug: for Type 0 configure transactions the
564 * PCI-E controller does not check the device number bits and just
565 * assumes that the device number bits are 0.
567 if (bus->number == hose->first_busno ||
568 bus->primary == hose->first_busno) {
570 return PCIBIOS_DEVICE_NOT_FOUND;
573 if (ppc_md.pci_exclude_device) {
574 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
575 return PCIBIOS_DEVICE_NOT_FOUND;
578 return PCIBIOS_SUCCESSFUL;
581 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
582 unsigned int devfn, int offset)
584 struct pci_controller *hose = pci_bus_to_host(bus);
585 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
586 u32 dev_base = bus->number << 24 | devfn << 16;
589 ret = mpc83xx_pcie_exclude_device(bus, devfn);
596 if (bus->number == hose->first_busno)
597 return pcie->cfg_type0 + offset;
599 if (pcie->dev_base == dev_base)
602 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
604 pcie->dev_base = dev_base;
606 return pcie->cfg_type1 + offset;
609 static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
610 int offset, int len, u32 *val)
612 void __iomem *cfg_addr;
614 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
616 return PCIBIOS_DEVICE_NOT_FOUND;
620 *val = in_8(cfg_addr);
623 *val = in_le16(cfg_addr);
626 *val = in_le32(cfg_addr);
630 return PCIBIOS_SUCCESSFUL;
633 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
634 int offset, int len, u32 val)
636 struct pci_controller *hose = pci_bus_to_host(bus);
637 void __iomem *cfg_addr;
639 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
641 return PCIBIOS_DEVICE_NOT_FOUND;
643 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
644 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
649 out_8(cfg_addr, val);
652 out_le16(cfg_addr, val);
655 out_le32(cfg_addr, val);
659 return PCIBIOS_SUCCESSFUL;
662 static struct pci_ops mpc83xx_pcie_ops = {
663 .read = mpc83xx_pcie_read_config,
664 .write = mpc83xx_pcie_write_config,
667 static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
668 struct resource *reg)
670 struct mpc83xx_pcie_priv *pcie;
674 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
678 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
679 if (!pcie->cfg_type0)
682 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
684 /* PCI-E isn't configured. */
689 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
690 if (!pcie->cfg_type1)
693 WARN_ON(hose->dn->data);
694 hose->dn->data = pcie;
695 hose->ops = &mpc83xx_pcie_ops;
696 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
698 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
699 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
701 if (fsl_pcie_check_link(hose))
702 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
706 iounmap(pcie->cfg_type0);
713 int __init mpc83xx_add_bridge(struct device_node *dev)
717 struct pci_controller *hose;
718 struct resource rsrc_reg;
719 struct resource rsrc_cfg;
720 const int *bus_range;
725 if (!of_device_is_available(dev)) {
726 pr_warning("%s: disabled by the firmware.\n",
730 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
732 /* Fetch host bridge registers address */
733 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
734 printk(KERN_WARNING "Can't get pci register base!\n");
738 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
740 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
742 "No pci config register base in dev tree, "
745 * MPC83xx supports up to two host controllers
746 * one at 0x8500 has config space registers at 0x8300
747 * one at 0x8600 has config space registers at 0x8380
749 if ((rsrc_reg.start & 0xfffff) == 0x8500)
750 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
751 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
752 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
755 * Controller at offset 0x8500 is primary
757 if ((rsrc_reg.start & 0xfffff) == 0x8500)
762 /* Get bus range if any */
763 bus_range = of_get_property(dev, "bus-range", &len);
764 if (bus_range == NULL || len < 2 * sizeof(int)) {
765 printk(KERN_WARNING "Can't get bus-range for %s, assume"
766 " bus 0\n", dev->full_name);
769 pci_add_flags(PCI_REASSIGN_ALL_BUS);
770 hose = pcibios_alloc_controller(dev);
774 hose->first_busno = bus_range ? bus_range[0] : 0;
775 hose->last_busno = bus_range ? bus_range[1] : 0xff;
777 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
778 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
782 setup_indirect_pci(hose, rsrc_cfg.start,
783 rsrc_cfg.start + 4, 0);
786 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
787 "Firmware bus number: %d->%d\n",
788 (unsigned long long)rsrc_reg.start, hose->first_busno,
791 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
792 hose, hose->cfg_addr, hose->cfg_data);
794 /* Interpret the "ranges" property */
795 /* This also maps the I/O region and sets isa_io/mem_base */
796 pci_process_bridge_OF_ranges(hose, dev, primary);
800 pcibios_free_controller(hose);
803 #endif /* CONFIG_PPC_83xx */
805 u64 fsl_pci_immrbar_base(struct pci_controller *hose)
807 #ifdef CONFIG_PPC_83xx
808 if (is_mpc83xx_pci) {
809 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
810 struct pex_inbound_window *in;
813 /* Walk the Root Complex Inbound windows to match IMMR base */
814 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
815 for (i = 0; i < 4; i++) {
816 /* not enabled, skip */
817 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
820 if (get_immrbase() == in_le32(&in[i].tar))
821 return (u64)in_le32(&in[i].barh) << 32 |
822 in_le32(&in[i].barl);
825 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
829 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
830 if (!is_mpc83xx_pci) {
833 pci_bus_read_config_dword(hose->bus,
834 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
842 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
843 static const struct of_device_id pci_ids[] = {
844 { .compatible = "fsl,mpc8540-pci", },
845 { .compatible = "fsl,mpc8548-pcie", },
846 { .compatible = "fsl,mpc8610-pci", },
847 { .compatible = "fsl,mpc8641-pcie", },
848 { .compatible = "fsl,qoriq-pcie-v2.1", },
849 { .compatible = "fsl,qoriq-pcie-v2.2", },
850 { .compatible = "fsl,qoriq-pcie-v2.3", },
851 { .compatible = "fsl,qoriq-pcie-v2.4", },
852 { .compatible = "fsl,qoriq-pcie-v3.0", },
855 * The following entries are for compatibility with older device
858 { .compatible = "fsl,p1022-pcie", },
859 { .compatible = "fsl,p4080-pcie", },
864 struct device_node *fsl_pci_primary;
866 void fsl_pci_assign_primary(void)
868 struct device_node *np;
870 /* Callers can specify the primary bus using other means. */
874 /* If a PCI host bridge contains an ISA node, it's primary. */
875 np = of_find_node_by_type(NULL, "isa");
876 while ((fsl_pci_primary = of_get_parent(np))) {
878 np = fsl_pci_primary;
880 if (of_match_node(pci_ids, np) && of_device_is_available(np))
885 * If there's no PCI host bridge with ISA, arbitrarily
886 * designate one as primary. This can go away once
887 * various bugs with primary-less systems are fixed.
889 for_each_matching_node(np, pci_ids) {
890 if (of_device_is_available(np)) {
891 fsl_pci_primary = np;
898 static int fsl_pci_probe(struct platform_device *pdev)
901 struct device_node *node;
902 #ifdef CONFIG_SWIOTLB
903 struct pci_controller *hose;
906 node = pdev->dev.of_node;
907 ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
909 #ifdef CONFIG_SWIOTLB
911 hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
914 * if we couldn't map all of DRAM via the dma windows
915 * we need SWIOTLB to handle buffers located outside of
916 * dma capable memory region
918 if (memblock_end_of_DRAM() - 1 > hose->dma_window_base_cur +
919 hose->dma_window_size)
920 ppc_swiotlb_enable = 1;
924 mpc85xx_pci_err_probe(pdev);
930 static int fsl_pci_resume(struct device *dev)
932 struct pci_controller *hose;
933 struct resource pci_rsrc;
935 hose = pci_find_hose_for_OF_device(dev->of_node);
939 if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
940 dev_err(dev, "Get pci register base failed.");
944 setup_pci_atmu(hose, &pci_rsrc);
949 static const struct dev_pm_ops pci_pm_ops = {
950 .resume = fsl_pci_resume,
953 #define PCI_PM_OPS (&pci_pm_ops)
957 #define PCI_PM_OPS NULL
961 static struct platform_driver fsl_pci_driver = {
965 .of_match_table = pci_ids,
967 .probe = fsl_pci_probe,
970 static int __init fsl_pci_init(void)
972 return platform_driver_register(&fsl_pci_driver);
974 arch_initcall(fsl_pci_init);