2 * Support PCI/PCIe on PowerNV platforms
4 * Currently supports only P5IOC2
6 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/delay.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/bootmem.h>
20 #include <linux/irq.h>
22 #include <linux/msi.h>
23 #include <linux/iommu.h>
25 #include <asm/sections.h>
28 #include <asm/pci-bridge.h>
29 #include <asm/machdep.h>
30 #include <asm/msi_bitmap.h>
31 #include <asm/ppc-pci.h>
33 #include <asm/iommu.h>
35 #include <asm/firmware.h>
36 #include <asm/eeh_event.h>
43 #define PCI_RESET_DELAY_US 3000000
45 #define cfg_dbg(fmt...) do { } while(0)
46 //#define cfg_dbg(fmt...) printk(fmt)
49 static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
51 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
52 struct pnv_phb *phb = hose->private_data;
53 struct msi_desc *entry;
59 if (WARN_ON(!phb) || !phb->msi_bmp.bitmap)
62 if (pdev->no_64bit_msi && !phb->msi32_support)
65 list_for_each_entry(entry, &pdev->msi_list, list) {
66 if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
67 pr_warn("%s: Supports only 64-bit MSIs\n",
71 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
73 pr_warn("%s: Failed to find a free MSI\n",
77 virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
79 pr_warn("%s: Failed to map MSI to linux irq\n",
81 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
84 rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
85 virq, entry->msi_attrib.is_64, &msg);
87 pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
88 irq_dispose_mapping(virq);
89 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
92 irq_set_msi_desc(virq, entry);
93 write_msi_msg(virq, &msg);
98 static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
100 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
101 struct pnv_phb *phb = hose->private_data;
102 struct msi_desc *entry;
107 list_for_each_entry(entry, &pdev->msi_list, list) {
108 if (entry->irq == NO_IRQ)
110 irq_set_msi_desc(entry->irq, NULL);
111 msi_bitmap_free_hwirqs(&phb->msi_bmp,
112 virq_to_hw(entry->irq) - phb->msi_base, 1);
113 irq_dispose_mapping(entry->irq);
116 #endif /* CONFIG_PCI_MSI */
118 static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose,
119 struct OpalIoPhbErrorCommon *common)
121 struct OpalIoP7IOCPhbErrorData *data;
124 data = (struct OpalIoP7IOCPhbErrorData *)common;
125 pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n",
126 hose->global_number, be32_to_cpu(common->version));
129 pr_info("brdgCtl: %08x\n",
130 be32_to_cpu(data->brdgCtl));
131 if (data->portStatusReg || data->rootCmplxStatus ||
132 data->busAgentStatus)
133 pr_info("UtlSts: %08x %08x %08x\n",
134 be32_to_cpu(data->portStatusReg),
135 be32_to_cpu(data->rootCmplxStatus),
136 be32_to_cpu(data->busAgentStatus));
137 if (data->deviceStatus || data->slotStatus ||
138 data->linkStatus || data->devCmdStatus ||
140 pr_info("RootSts: %08x %08x %08x %08x %08x\n",
141 be32_to_cpu(data->deviceStatus),
142 be32_to_cpu(data->slotStatus),
143 be32_to_cpu(data->linkStatus),
144 be32_to_cpu(data->devCmdStatus),
145 be32_to_cpu(data->devSecStatus));
146 if (data->rootErrorStatus || data->uncorrErrorStatus ||
147 data->corrErrorStatus)
148 pr_info("RootErrSts: %08x %08x %08x\n",
149 be32_to_cpu(data->rootErrorStatus),
150 be32_to_cpu(data->uncorrErrorStatus),
151 be32_to_cpu(data->corrErrorStatus));
152 if (data->tlpHdr1 || data->tlpHdr2 ||
153 data->tlpHdr3 || data->tlpHdr4)
154 pr_info("RootErrLog: %08x %08x %08x %08x\n",
155 be32_to_cpu(data->tlpHdr1),
156 be32_to_cpu(data->tlpHdr2),
157 be32_to_cpu(data->tlpHdr3),
158 be32_to_cpu(data->tlpHdr4));
159 if (data->sourceId || data->errorClass ||
161 pr_info("RootErrLog1: %08x %016llx %016llx\n",
162 be32_to_cpu(data->sourceId),
163 be64_to_cpu(data->errorClass),
164 be64_to_cpu(data->correlator));
165 if (data->p7iocPlssr || data->p7iocCsr)
166 pr_info("PhbSts: %016llx %016llx\n",
167 be64_to_cpu(data->p7iocPlssr),
168 be64_to_cpu(data->p7iocCsr));
170 pr_info("Lem: %016llx %016llx %016llx\n",
171 be64_to_cpu(data->lemFir),
172 be64_to_cpu(data->lemErrorMask),
173 be64_to_cpu(data->lemWOF));
174 if (data->phbErrorStatus)
175 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n",
176 be64_to_cpu(data->phbErrorStatus),
177 be64_to_cpu(data->phbFirstErrorStatus),
178 be64_to_cpu(data->phbErrorLog0),
179 be64_to_cpu(data->phbErrorLog1));
180 if (data->mmioErrorStatus)
181 pr_info("OutErr: %016llx %016llx %016llx %016llx\n",
182 be64_to_cpu(data->mmioErrorStatus),
183 be64_to_cpu(data->mmioFirstErrorStatus),
184 be64_to_cpu(data->mmioErrorLog0),
185 be64_to_cpu(data->mmioErrorLog1));
186 if (data->dma0ErrorStatus)
187 pr_info("InAErr: %016llx %016llx %016llx %016llx\n",
188 be64_to_cpu(data->dma0ErrorStatus),
189 be64_to_cpu(data->dma0FirstErrorStatus),
190 be64_to_cpu(data->dma0ErrorLog0),
191 be64_to_cpu(data->dma0ErrorLog1));
192 if (data->dma1ErrorStatus)
193 pr_info("InBErr: %016llx %016llx %016llx %016llx\n",
194 be64_to_cpu(data->dma1ErrorStatus),
195 be64_to_cpu(data->dma1FirstErrorStatus),
196 be64_to_cpu(data->dma1ErrorLog0),
197 be64_to_cpu(data->dma1ErrorLog1));
199 for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
200 if ((data->pestA[i] >> 63) == 0 &&
201 (data->pestB[i] >> 63) == 0)
204 pr_info("PE[%3d] A/B: %016llx %016llx\n",
205 i, be64_to_cpu(data->pestA[i]),
206 be64_to_cpu(data->pestB[i]));
210 static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose,
211 struct OpalIoPhbErrorCommon *common)
213 struct OpalIoPhb3ErrorData *data;
216 data = (struct OpalIoPhb3ErrorData*)common;
217 pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n",
218 hose->global_number, be32_to_cpu(common->version));
220 pr_info("brdgCtl: %08x\n",
221 be32_to_cpu(data->brdgCtl));
222 if (data->portStatusReg || data->rootCmplxStatus ||
223 data->busAgentStatus)
224 pr_info("UtlSts: %08x %08x %08x\n",
225 be32_to_cpu(data->portStatusReg),
226 be32_to_cpu(data->rootCmplxStatus),
227 be32_to_cpu(data->busAgentStatus));
228 if (data->deviceStatus || data->slotStatus ||
229 data->linkStatus || data->devCmdStatus ||
231 pr_info("RootSts: %08x %08x %08x %08x %08x\n",
232 be32_to_cpu(data->deviceStatus),
233 be32_to_cpu(data->slotStatus),
234 be32_to_cpu(data->linkStatus),
235 be32_to_cpu(data->devCmdStatus),
236 be32_to_cpu(data->devSecStatus));
237 if (data->rootErrorStatus || data->uncorrErrorStatus ||
238 data->corrErrorStatus)
239 pr_info("RootErrSts: %08x %08x %08x\n",
240 be32_to_cpu(data->rootErrorStatus),
241 be32_to_cpu(data->uncorrErrorStatus),
242 be32_to_cpu(data->corrErrorStatus));
243 if (data->tlpHdr1 || data->tlpHdr2 ||
244 data->tlpHdr3 || data->tlpHdr4)
245 pr_info("RootErrLog: %08x %08x %08x %08x\n",
246 be32_to_cpu(data->tlpHdr1),
247 be32_to_cpu(data->tlpHdr2),
248 be32_to_cpu(data->tlpHdr3),
249 be32_to_cpu(data->tlpHdr4));
250 if (data->sourceId || data->errorClass ||
252 pr_info("RootErrLog1: %08x %016llx %016llx\n",
253 be32_to_cpu(data->sourceId),
254 be64_to_cpu(data->errorClass),
255 be64_to_cpu(data->correlator));
257 pr_info("nFir: %016llx %016llx %016llx\n",
258 be64_to_cpu(data->nFir),
259 be64_to_cpu(data->nFirMask),
260 be64_to_cpu(data->nFirWOF));
261 if (data->phbPlssr || data->phbCsr)
262 pr_info("PhbSts: %016llx %016llx\n",
263 be64_to_cpu(data->phbPlssr),
264 be64_to_cpu(data->phbCsr));
266 pr_info("Lem: %016llx %016llx %016llx\n",
267 be64_to_cpu(data->lemFir),
268 be64_to_cpu(data->lemErrorMask),
269 be64_to_cpu(data->lemWOF));
270 if (data->phbErrorStatus)
271 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n",
272 be64_to_cpu(data->phbErrorStatus),
273 be64_to_cpu(data->phbFirstErrorStatus),
274 be64_to_cpu(data->phbErrorLog0),
275 be64_to_cpu(data->phbErrorLog1));
276 if (data->mmioErrorStatus)
277 pr_info("OutErr: %016llx %016llx %016llx %016llx\n",
278 be64_to_cpu(data->mmioErrorStatus),
279 be64_to_cpu(data->mmioFirstErrorStatus),
280 be64_to_cpu(data->mmioErrorLog0),
281 be64_to_cpu(data->mmioErrorLog1));
282 if (data->dma0ErrorStatus)
283 pr_info("InAErr: %016llx %016llx %016llx %016llx\n",
284 be64_to_cpu(data->dma0ErrorStatus),
285 be64_to_cpu(data->dma0FirstErrorStatus),
286 be64_to_cpu(data->dma0ErrorLog0),
287 be64_to_cpu(data->dma0ErrorLog1));
288 if (data->dma1ErrorStatus)
289 pr_info("InBErr: %016llx %016llx %016llx %016llx\n",
290 be64_to_cpu(data->dma1ErrorStatus),
291 be64_to_cpu(data->dma1FirstErrorStatus),
292 be64_to_cpu(data->dma1ErrorLog0),
293 be64_to_cpu(data->dma1ErrorLog1));
295 for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) {
296 if ((be64_to_cpu(data->pestA[i]) >> 63) == 0 &&
297 (be64_to_cpu(data->pestB[i]) >> 63) == 0)
300 pr_info("PE[%3d] A/B: %016llx %016llx\n",
301 i, be64_to_cpu(data->pestA[i]),
302 be64_to_cpu(data->pestB[i]));
306 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
307 unsigned char *log_buff)
309 struct OpalIoPhbErrorCommon *common;
311 if (!hose || !log_buff)
314 common = (struct OpalIoPhbErrorCommon *)log_buff;
315 switch (be32_to_cpu(common->ioType)) {
316 case OPAL_PHB_ERROR_DATA_TYPE_P7IOC:
317 pnv_pci_dump_p7ioc_diag_data(hose, common);
319 case OPAL_PHB_ERROR_DATA_TYPE_PHB3:
320 pnv_pci_dump_phb3_diag_data(hose, common);
323 pr_warn("%s: Unrecognized ioType %d\n",
324 __func__, be32_to_cpu(common->ioType));
328 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
330 unsigned long flags, rc;
331 int has_diag, ret = 0;
333 spin_lock_irqsave(&phb->lock, flags);
335 /* Fetch PHB diag-data */
336 rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
337 PNV_PCI_DIAG_BUF_SIZE);
338 has_diag = (rc == OPAL_SUCCESS);
340 /* If PHB supports compound PE, to handle it */
341 if (phb->unfreeze_pe) {
342 ret = phb->unfreeze_pe(phb,
344 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
346 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
348 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
350 pr_warn("%s: Failure %ld clearing frozen "
352 __func__, rc, phb->hose->global_number,
359 * For now, let's only display the diag buffer when we fail to clear
360 * the EEH status. We'll do more sensible things later when we have
361 * proper EEH support. We need to make sure we don't pollute ourselves
362 * with the normal errors generated when probing empty slots
365 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob);
367 spin_unlock_irqrestore(&phb->lock, flags);
370 static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
371 struct device_node *dn)
379 * Get the PE#. During the PCI probe stage, we might not
380 * setup that yet. So all ER errors should be mapped to
383 pe_no = PCI_DN(dn)->pe_number;
384 if (pe_no == IODA_INVALID_PE) {
385 if (phb->type == PNV_PHB_P5IOC2)
388 pe_no = phb->ioda.reserved_pe;
392 * Fetch frozen state. If the PHB support compound PE,
393 * we need handle that case.
395 if (phb->get_pe_state) {
396 fstate = phb->get_pe_state(phb, pe_no);
398 rc = opal_pci_eeh_freeze_status(phb->opal_id,
404 pr_warn("%s: Failure %lld getting PHB#%x-PE#%x state\n",
405 __func__, rc, phb->hose->global_number, pe_no);
410 cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n",
411 (PCI_DN(dn)->busno << 8) | (PCI_DN(dn)->devfn),
414 /* Clear the frozen state if applicable */
415 if (fstate == OPAL_EEH_STOPPED_MMIO_FREEZE ||
416 fstate == OPAL_EEH_STOPPED_DMA_FREEZE ||
417 fstate == OPAL_EEH_STOPPED_MMIO_DMA_FREEZE) {
419 * If PHB supports compound PE, freeze it for
423 phb->freeze_pe(phb, pe_no);
425 pnv_pci_handle_eeh_config(phb, pe_no);
429 int pnv_pci_cfg_read(struct device_node *dn,
430 int where, int size, u32 *val)
432 struct pci_dn *pdn = PCI_DN(dn);
433 struct pnv_phb *phb = pdn->phb->private_data;
434 u32 bdfn = (pdn->busno << 8) | pdn->devfn;
440 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
441 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
446 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
448 *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff;
453 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
454 *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff;
458 return PCIBIOS_FUNC_NOT_SUPPORTED;
461 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
462 __func__, pdn->busno, pdn->devfn, where, size, *val);
463 return PCIBIOS_SUCCESSFUL;
466 int pnv_pci_cfg_write(struct device_node *dn,
467 int where, int size, u32 val)
469 struct pci_dn *pdn = PCI_DN(dn);
470 struct pnv_phb *phb = pdn->phb->private_data;
471 u32 bdfn = (pdn->busno << 8) | pdn->devfn;
473 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
474 pdn->busno, pdn->devfn, where, size, val);
477 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
480 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
483 opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
486 return PCIBIOS_FUNC_NOT_SUPPORTED;
489 return PCIBIOS_SUCCESSFUL;
493 static bool pnv_pci_cfg_check(struct pci_controller *hose,
494 struct device_node *dn)
496 struct eeh_dev *edev = NULL;
497 struct pnv_phb *phb = hose->private_data;
499 /* EEH not enabled ? */
500 if (!(phb->flags & PNV_PHB_FLAG_EEH))
503 /* PE reset or device removed ? */
504 edev = of_node_to_eeh_dev(dn);
507 (edev->pe->state & EEH_PE_CFG_BLOCKED))
510 if (edev->mode & EEH_DEV_REMOVED)
517 static inline pnv_pci_cfg_check(struct pci_controller *hose,
518 struct device_node *dn)
522 #endif /* CONFIG_EEH */
524 static int pnv_pci_read_config(struct pci_bus *bus,
526 int where, int size, u32 *val)
528 struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
535 for (dn = busdn->child; dn; dn = dn->sibling) {
537 if (pdn && pdn->devfn == devfn) {
538 phb = pdn->phb->private_data;
544 if (!found || !pnv_pci_cfg_check(pdn->phb, dn))
545 return PCIBIOS_DEVICE_NOT_FOUND;
547 ret = pnv_pci_cfg_read(dn, where, size, val);
548 if (phb->flags & PNV_PHB_FLAG_EEH) {
549 if (*val == EEH_IO_ERROR_VALUE(size) &&
550 eeh_dev_check_failure(of_node_to_eeh_dev(dn)))
551 return PCIBIOS_DEVICE_NOT_FOUND;
553 pnv_pci_config_check_eeh(phb, dn);
559 static int pnv_pci_write_config(struct pci_bus *bus,
561 int where, int size, u32 val)
563 struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
569 for (dn = busdn->child; dn; dn = dn->sibling) {
571 if (pdn && pdn->devfn == devfn) {
572 phb = pdn->phb->private_data;
578 if (!found || !pnv_pci_cfg_check(pdn->phb, dn))
579 return PCIBIOS_DEVICE_NOT_FOUND;
581 ret = pnv_pci_cfg_write(dn, where, size, val);
582 if (!(phb->flags & PNV_PHB_FLAG_EEH))
583 pnv_pci_config_check_eeh(phb, dn);
588 struct pci_ops pnv_pci_ops = {
589 .read = pnv_pci_read_config,
590 .write = pnv_pci_write_config,
593 static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
594 unsigned long uaddr, enum dma_data_direction direction,
595 struct dma_attrs *attrs, bool rm)
601 proto_tce = TCE_PCI_READ; // Read allowed
603 if (direction != DMA_TO_DEVICE)
604 proto_tce |= TCE_PCI_WRITE;
606 tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset;
607 rpn = __pa(uaddr) >> tbl->it_page_shift;
610 *(tcep++) = cpu_to_be64(proto_tce |
611 (rpn++ << tbl->it_page_shift));
613 /* Some implementations won't cache invalid TCEs and thus may not
614 * need that flush. We'll probably turn it_type into a bit mask
615 * of flags if that becomes the case
617 if (tbl->it_type & TCE_PCI_SWINV_CREATE)
618 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm);
623 static int pnv_tce_build_vm(struct iommu_table *tbl, long index, long npages,
625 enum dma_data_direction direction,
626 struct dma_attrs *attrs)
628 return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs,
632 static void pnv_tce_free(struct iommu_table *tbl, long index, long npages,
637 tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset;
640 *(tcep++) = cpu_to_be64(0);
642 if (tbl->it_type & TCE_PCI_SWINV_FREE)
643 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm);
646 static void pnv_tce_free_vm(struct iommu_table *tbl, long index, long npages)
648 pnv_tce_free(tbl, index, npages, false);
651 static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
653 return ((u64 *)tbl->it_base)[index - tbl->it_offset];
656 static int pnv_tce_build_rm(struct iommu_table *tbl, long index, long npages,
658 enum dma_data_direction direction,
659 struct dma_attrs *attrs)
661 return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, true);
664 static void pnv_tce_free_rm(struct iommu_table *tbl, long index, long npages)
666 pnv_tce_free(tbl, index, npages, true);
669 void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
670 void *tce_mem, u64 tce_size,
671 u64 dma_offset, unsigned page_shift)
673 tbl->it_blocksize = 16;
674 tbl->it_base = (unsigned long)tce_mem;
675 tbl->it_page_shift = page_shift;
676 tbl->it_offset = dma_offset >> tbl->it_page_shift;
678 tbl->it_size = tce_size >> 3;
680 tbl->it_type = TCE_PCI;
683 static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose)
685 struct iommu_table *tbl;
686 const __be64 *basep, *swinvp;
689 basep = of_get_property(hose->dn, "linux,tce-base", NULL);
690 sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
691 if (basep == NULL || sizep == NULL) {
692 pr_err("PCI: %s has missing tce entries !\n",
693 hose->dn->full_name);
696 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
699 pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
700 be32_to_cpup(sizep), 0, IOMMU_PAGE_SHIFT_4K);
701 iommu_init_table(tbl, hose->node);
702 iommu_register_group(tbl, pci_domain_nr(hose->bus), 0);
704 /* Deal with SW invalidated TCEs when needed (BML way) */
705 swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
708 tbl->it_busno = be64_to_cpu(swinvp[1]);
709 tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8);
710 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
715 static void pnv_pci_dma_fallback_setup(struct pci_controller *hose,
716 struct pci_dev *pdev)
718 struct device_node *np = pci_bus_to_OF_node(hose->bus);
724 if (!pdn->iommu_table)
725 pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
726 if (!pdn->iommu_table)
728 set_iommu_table_base_and_group(&pdev->dev, pdn->iommu_table);
731 static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
733 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
734 struct pnv_phb *phb = hose->private_data;
736 /* If we have no phb structure, try to setup a fallback based on
737 * the device-tree (RTAS PCI for example)
739 if (phb && phb->dma_dev_setup)
740 phb->dma_dev_setup(phb, pdev);
742 pnv_pci_dma_fallback_setup(hose, pdev);
745 int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
747 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
748 struct pnv_phb *phb = hose->private_data;
750 if (phb && phb->dma_set_mask)
751 return phb->dma_set_mask(phb, pdev, dma_mask);
752 return __dma_set_mask(&pdev->dev, dma_mask);
755 u64 pnv_pci_dma_get_required_mask(struct pci_dev *pdev)
757 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
758 struct pnv_phb *phb = hose->private_data;
760 if (phb && phb->dma_get_required_mask)
761 return phb->dma_get_required_mask(phb, pdev);
763 return __dma_get_required_mask(&pdev->dev);
766 void pnv_pci_shutdown(void)
768 struct pci_controller *hose;
770 list_for_each_entry(hose, &hose_list, list_node) {
771 struct pnv_phb *phb = hose->private_data;
773 if (phb && phb->shutdown)
778 /* Fixup wrong class code in p7ioc and p8 root complex */
779 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
781 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
783 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
785 static int pnv_pci_probe_mode(struct pci_bus *bus)
787 struct pci_controller *hose = pci_bus_to_host(bus);
788 const __be64 *tstamp;
792 /* We hijack this as a way to ensure we have waited long
793 * enough since the reset was lifted on the PCI bus
795 if (bus != hose->bus)
796 return PCI_PROBE_NORMAL;
797 tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL);
798 if (!tstamp || !*tstamp)
799 return PCI_PROBE_NORMAL;
801 now = mftb() / tb_ticks_per_usec;
802 target = (be64_to_cpup(tstamp) / tb_ticks_per_usec)
803 + PCI_RESET_DELAY_US;
805 pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n",
806 hose->global_number, target, now);
809 msleep((target - now + 999) / 1000);
811 return PCI_PROBE_NORMAL;
814 void __init pnv_pci_init(void)
816 struct device_node *np;
818 pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
820 /* OPAL absent, try POPAL first then RTAS detection of PHBs */
821 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
822 #ifdef CONFIG_PPC_POWERNV_RTAS
823 init_pci_config_tokens();
824 find_and_init_phbs();
825 #endif /* CONFIG_PPC_POWERNV_RTAS */
827 /* OPAL is here, do our normal stuff */
831 /* Look for IODA IO-Hubs. We don't support mixing IODA
832 * and p5ioc2 due to the need to change some global
835 for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
836 pnv_pci_init_ioda_hub(np);
840 /* Look for p5ioc2 IO-Hubs */
842 for_each_compatible_node(np, NULL, "ibm,p5ioc2")
843 pnv_pci_init_p5ioc2_hub(np);
845 /* Look for ioda2 built-in PHB3's */
846 for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
847 pnv_pci_init_ioda2_phb(np);
850 /* Setup the linkage between OF nodes and PHBs */
853 /* Configure IOMMU DMA hooks */
854 ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
855 ppc_md.tce_build = pnv_tce_build_vm;
856 ppc_md.tce_free = pnv_tce_free_vm;
857 ppc_md.tce_build_rm = pnv_tce_build_rm;
858 ppc_md.tce_free_rm = pnv_tce_free_rm;
859 ppc_md.tce_get = pnv_tce_get;
860 ppc_md.pci_probe_mode = pnv_pci_probe_mode;
861 set_pci_dma_ops(&dma_iommu_ops);
864 #ifdef CONFIG_PCI_MSI
865 ppc_md.setup_msi_irqs = pnv_setup_msi_irqs;
866 ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
870 static int tce_iommu_bus_notifier(struct notifier_block *nb,
871 unsigned long action, void *data)
873 struct device *dev = data;
876 case BUS_NOTIFY_ADD_DEVICE:
877 return iommu_add_device(dev);
878 case BUS_NOTIFY_DEL_DEVICE:
879 if (dev->iommu_group)
880 iommu_del_device(dev);
887 static struct notifier_block tce_iommu_bus_nb = {
888 .notifier_call = tce_iommu_bus_notifier,
891 static int __init tce_iommu_bus_notifier_init(void)
893 bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb);
896 machine_subsys_initcall_sync(powernv, tce_iommu_bus_notifier_init);