arch/powerpc/platforms/powernv/pci.c

   1
   2 /*
   3  * Support PCI/PCIe on PowerNV platforms
   4  *
   5  * Currently supports only P5IOC2
   6  *
   7  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/pci.h>
  17 #include <linux/delay.h>
  18 #include <linux/string.h>
  19 #include <linux/init.h>
  20 #include <linux/bootmem.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <linux/msi.h>
  24
  25 #include <asm/sections.h>
  26 #include <asm/io.h>
  27 #include <asm/prom.h>
  28 #include <asm/pci-bridge.h>
  29 #include <asm/machdep.h>
  30 #include <asm/msi_bitmap.h>
  31 #include <asm/ppc-pci.h>
  32 #include <asm/opal.h>
  33 #include <asm/iommu.h>
  34 #include <asm/tce.h>
  35 #include <asm/firmware.h>
  36
  37 #include "powernv.h"
  38 #include "pci.h"
  39
  40 /* Delay in usec */
  41 #define PCI_RESET_DELAY_US      3000000
  42
  43 #define cfg_dbg(fmt...) do { } while(0)
  44 //#define cfg_dbg(fmt...)       printk(fmt)
  45
  46 #ifdef CONFIG_PCI_MSI
  47 static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type)
  48 {
  49         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  50         struct pnv_phb *phb = hose->private_data;
  51
  52         if (pdev->no_64bit_msi && !phb->msi32_support)
  53                 return -ENODEV;
  54
  55         return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV;
  56 }
  57
  58 static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
  59 {
  60         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  61         struct pnv_phb *phb = hose->private_data;
  62         struct msi_desc *entry;
  63         struct msi_msg msg;
  64         int hwirq;
  65         unsigned int virq;
  66         int rc;
  67
  68         if (WARN_ON(!phb))
  69                 return -ENODEV;
  70
  71         list_for_each_entry(entry, &pdev->msi_list, list) {
  72                 if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
  73                         pr_warn("%s: Supports only 64-bit MSIs\n",
  74                                 pci_name(pdev));
  75                         return -ENXIO;
  76                 }
  77                 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
  78                 if (hwirq < 0) {
  79                         pr_warn("%s: Failed to find a free MSI\n",
  80                                 pci_name(pdev));
  81                         return -ENOSPC;
  82                 }
  83                 virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
  84                 if (virq == NO_IRQ) {
  85                         pr_warn("%s: Failed to map MSI to linux irq\n",
  86                                 pci_name(pdev));
  87                         msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
  88                         return -ENOMEM;
  89                 }
  90                 rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
  91                                     virq, entry->msi_attrib.is_64, &msg);
  92                 if (rc) {
  93                         pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
  94                         irq_dispose_mapping(virq);
  95                         msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
  96                         return rc;
  97                 }
  98                 irq_set_msi_desc(virq, entry);
  99                 write_msi_msg(virq, &msg);
 100         }
 101         return 0;
 102 }
 103
 104 static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
 105 {
 106         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 107         struct pnv_phb *phb = hose->private_data;
 108         struct msi_desc *entry;
 109         irq_hw_number_t hwirq;
 110
 111         if (WARN_ON(!phb))
 112                 return;
 113
 114         list_for_each_entry(entry, &pdev->msi_list, list) {
 115                 if (entry->irq == NO_IRQ)
 116                         continue;
 117                 hwirq = virq_to_hw(entry->irq);
 118                 irq_set_msi_desc(entry->irq, NULL);
 119                 irq_dispose_mapping(entry->irq);
 120                 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, 1);
 121         }
 122 }
 123 #endif /* CONFIG_PCI_MSI */
 124
 125 static void pnv_pci_dump_p7ioc_diag_data(struct pnv_phb *phb)
 126 {
 127         struct OpalIoP7IOCPhbErrorData *data = &phb->diag.p7ioc;
 128         int i;
 129
 130         pr_info("PHB %d diagnostic data:\n", phb->hose->global_number);
 131
 132         pr_info("  brdgCtl              = 0x%08x\n", data->brdgCtl);
 133
 134         pr_info("  portStatusReg        = 0x%08x\n", data->portStatusReg);
 135         pr_info("  rootCmplxStatus      = 0x%08x\n", data->rootCmplxStatus);
 136         pr_info("  busAgentStatus       = 0x%08x\n", data->busAgentStatus);
 137
 138         pr_info("  deviceStatus         = 0x%08x\n", data->deviceStatus);
 139         pr_info("  slotStatus           = 0x%08x\n", data->slotStatus);
 140         pr_info("  linkStatus           = 0x%08x\n", data->linkStatus);
 141         pr_info("  devCmdStatus         = 0x%08x\n", data->devCmdStatus);
 142         pr_info("  devSecStatus         = 0x%08x\n", data->devSecStatus);
 143
 144         pr_info("  rootErrorStatus      = 0x%08x\n", data->rootErrorStatus);
 145         pr_info("  uncorrErrorStatus    = 0x%08x\n", data->uncorrErrorStatus);
 146         pr_info("  corrErrorStatus      = 0x%08x\n", data->corrErrorStatus);
 147         pr_info("  tlpHdr1              = 0x%08x\n", data->tlpHdr1);
 148         pr_info("  tlpHdr2              = 0x%08x\n", data->tlpHdr2);
 149         pr_info("  tlpHdr3              = 0x%08x\n", data->tlpHdr3);
 150         pr_info("  tlpHdr4              = 0x%08x\n", data->tlpHdr4);
 151         pr_info("  sourceId             = 0x%08x\n", data->sourceId);
 152
 153         pr_info("  errorClass           = 0x%016llx\n", data->errorClass);
 154         pr_info("  correlator           = 0x%016llx\n", data->correlator);
 155
 156         pr_info("  p7iocPlssr           = 0x%016llx\n", data->p7iocPlssr);
 157         pr_info("  p7iocCsr             = 0x%016llx\n", data->p7iocCsr);
 158         pr_info("  lemFir               = 0x%016llx\n", data->lemFir);
 159         pr_info("  lemErrorMask         = 0x%016llx\n", data->lemErrorMask);
 160         pr_info("  lemWOF               = 0x%016llx\n", data->lemWOF);
 161         pr_info("  phbErrorStatus       = 0x%016llx\n", data->phbErrorStatus);
 162         pr_info("  phbFirstErrorStatus  = 0x%016llx\n", data->phbFirstErrorStatus);
 163         pr_info("  phbErrorLog0         = 0x%016llx\n", data->phbErrorLog0);
 164         pr_info("  phbErrorLog1         = 0x%016llx\n", data->phbErrorLog1);
 165         pr_info("  mmioErrorStatus      = 0x%016llx\n", data->mmioErrorStatus);
 166         pr_info("  mmioFirstErrorStatus = 0x%016llx\n", data->mmioFirstErrorStatus);
 167         pr_info("  mmioErrorLog0        = 0x%016llx\n", data->mmioErrorLog0);
 168         pr_info("  mmioErrorLog1        = 0x%016llx\n", data->mmioErrorLog1);
 169         pr_info("  dma0ErrorStatus      = 0x%016llx\n", data->dma0ErrorStatus);
 170         pr_info("  dma0FirstErrorStatus = 0x%016llx\n", data->dma0FirstErrorStatus);
 171         pr_info("  dma0ErrorLog0        = 0x%016llx\n", data->dma0ErrorLog0);
 172         pr_info("  dma0ErrorLog1        = 0x%016llx\n", data->dma0ErrorLog1);
 173         pr_info("  dma1ErrorStatus      = 0x%016llx\n", data->dma1ErrorStatus);
 174         pr_info("  dma1FirstErrorStatus = 0x%016llx\n", data->dma1FirstErrorStatus);
 175         pr_info("  dma1ErrorLog0        = 0x%016llx\n", data->dma1ErrorLog0);
 176         pr_info("  dma1ErrorLog1        = 0x%016llx\n", data->dma1ErrorLog1);
 177
 178         for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
 179                 if ((data->pestA[i] >> 63) == 0 &&
 180                     (data->pestB[i] >> 63) == 0)
 181                         continue;
 182                 pr_info("  PE[%3d] PESTA        = 0x%016llx\n", i, data->pestA[i]);
 183                 pr_info("          PESTB        = 0x%016llx\n", data->pestB[i]);
 184         }
 185 }
 186
 187 static void pnv_pci_dump_phb_diag_data(struct pnv_phb *phb)
 188 {
 189         switch(phb->model) {
 190         case PNV_PHB_MODEL_P7IOC:
 191                 pnv_pci_dump_p7ioc_diag_data(phb);
 192                 break;
 193         default:
 194                 pr_warning("PCI %d: Can't decode this PHB diag data\n",
 195                            phb->hose->global_number);
 196         }
 197 }
 198
 199 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
 200 {
 201         unsigned long flags, rc;
 202         int has_diag;
 203
 204         spin_lock_irqsave(&phb->lock, flags);
 205
 206         rc = opal_pci_get_phb_diag_data(phb->opal_id, phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
 207         has_diag = (rc == OPAL_SUCCESS);
 208
 209         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 210                                        OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 211         if (rc) {
 212                 pr_warning("PCI %d: Failed to clear EEH freeze state"
 213                            " for PE#%d, err %ld\n",
 214                            phb->hose->global_number, pe_no, rc);
 215
 216                 /* For now, let's only display the diag buffer when we fail to clear
 217                  * the EEH status. We'll do more sensible things later when we have
 218                  * proper EEH support. We need to make sure we don't pollute ourselves
 219                  * with the normal errors generated when probing empty slots
 220                  */
 221                 if (has_diag)
 222                         pnv_pci_dump_phb_diag_data(phb);
 223                 else
 224                         pr_warning("PCI %d: No diag data available\n",
 225                                    phb->hose->global_number);
 226         }
 227
 228         spin_unlock_irqrestore(&phb->lock, flags);
 229 }
 230
 231 static void pnv_pci_config_check_eeh(struct pnv_phb *phb, struct pci_bus *bus,
 232                                      u32 bdfn)
 233 {
 234         s64     rc;
 235         u8      fstate;
 236         u16     pcierr;
 237         u32     pe_no;
 238
 239         /* Get PE# if we support IODA */
 240         pe_no = phb->bdfn_to_pe ? phb->bdfn_to_pe(phb, bus, bdfn & 0xff) : 0;
 241
 242         /* Read freeze status */
 243         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr,
 244                                         NULL);
 245         if (rc) {
 246                 pr_warning("PCI %d: Failed to read EEH status for PE#%d,"
 247                            " err %lld\n", phb->hose->global_number, pe_no, rc);
 248                 return;
 249         }
 250         cfg_dbg(" -> EEH check, bdfn=%04x PE%d fstate=%x\n",
 251                 bdfn, pe_no, fstate);
 252         if (fstate != 0)
 253                 pnv_pci_handle_eeh_config(phb, pe_no);
 254 }
 255
 256 static int pnv_pci_read_config(struct pci_bus *bus,
 257                                unsigned int devfn,
 258                                int where, int size, u32 *val)
 259 {
 260         struct pci_controller *hose = pci_bus_to_host(bus);
 261         struct pnv_phb *phb = hose->private_data;
 262         u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;
 263         s64 rc;
 264
 265         if (hose == NULL)
 266                 return PCIBIOS_DEVICE_NOT_FOUND;
 267
 268         switch (size) {
 269         case 1: {
 270                 u8 v8;
 271                 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
 272                 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
 273                 break;
 274         }
 275         case 2: {
 276                 u16 v16;
 277                 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
 278                                                    &v16);
 279                 *val = (rc == OPAL_SUCCESS) ? v16 : 0xffff;
 280                 break;
 281         }
 282         case 4: {
 283                 u32 v32;
 284                 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
 285                 *val = (rc == OPAL_SUCCESS) ? v32 : 0xffffffff;
 286                 break;
 287         }
 288         default:
 289                 return PCIBIOS_FUNC_NOT_SUPPORTED;
 290         }
 291         cfg_dbg("pnv_pci_read_config bus: %x devfn: %x +%x/%x -> %08x\n",
 292                 bus->number, devfn, where, size, *val);
 293
 294         /* Check if the PHB got frozen due to an error (no response) */
 295         pnv_pci_config_check_eeh(phb, bus, bdfn);
 296
 297         return PCIBIOS_SUCCESSFUL;
 298 }
 299
 300 static int pnv_pci_write_config(struct pci_bus *bus,
 301                                 unsigned int devfn,
 302                                 int where, int size, u32 val)
 303 {
 304         struct pci_controller *hose = pci_bus_to_host(bus);
 305         struct pnv_phb *phb = hose->private_data;
 306         u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;
 307
 308         if (hose == NULL)
 309                 return PCIBIOS_DEVICE_NOT_FOUND;
 310
 311         cfg_dbg("pnv_pci_write_config bus: %x devfn: %x +%x/%x -> %08x\n",
 312                 bus->number, devfn, where, size, val);
 313         switch (size) {
 314         case 1:
 315                 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
 316                 break;
 317         case 2:
 318                 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
 319                 break;
 320         case 4:
 321                 opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
 322                 break;
 323         default:
 324                 return PCIBIOS_FUNC_NOT_SUPPORTED;
 325         }
 326         /* Check if the PHB got frozen due to an error (no response) */
 327         pnv_pci_config_check_eeh(phb, bus, bdfn);
 328
 329         return PCIBIOS_SUCCESSFUL;
 330 }
 331
 332 struct pci_ops pnv_pci_ops = {
 333         .read = pnv_pci_read_config,
 334         .write = pnv_pci_write_config,
 335 };
 336
 337 static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
 338                          unsigned long uaddr, enum dma_data_direction direction,
 339                          struct dma_attrs *attrs)
 340 {
 341         u64 proto_tce;
 342         u64 *tcep, *tces;
 343         u64 rpn;
 344
 345         proto_tce = TCE_PCI_READ; // Read allowed
 346
 347         if (direction != DMA_TO_DEVICE)
 348                 proto_tce |= TCE_PCI_WRITE;
 349
 350         tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
 351         rpn = __pa(uaddr) >> TCE_SHIFT;
 352
 353         while (npages--)
 354                 *(tcep++) = proto_tce | (rpn++ << TCE_RPN_SHIFT);
 355
 356         /* Some implementations won't cache invalid TCEs and thus may not
 357          * need that flush. We'll probably turn it_type into a bit mask
 358          * of flags if that becomes the case
 359          */
 360         if (tbl->it_type & TCE_PCI_SWINV_CREATE)
 361                 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
 362
 363         return 0;
 364 }
 365
 366 static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
 367 {
 368         u64 *tcep, *tces;
 369
 370         tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
 371
 372         while (npages--)
 373                 *(tcep++) = 0;
 374
 375         if (tbl->it_type & TCE_PCI_SWINV_FREE)
 376                 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
 377 }
 378
 379 static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
 380 {
 381         return ((u64 *)tbl->it_base)[index - tbl->it_offset];
 382 }
 383
 384 void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
 385                                void *tce_mem, u64 tce_size,
 386                                u64 dma_offset)
 387 {
 388         tbl->it_blocksize = 16;
 389         tbl->it_base = (unsigned long)tce_mem;
 390         tbl->it_offset = dma_offset >> IOMMU_PAGE_SHIFT;
 391         tbl->it_index = 0;
 392         tbl->it_size = tce_size >> 3;
 393         tbl->it_busno = 0;
 394         tbl->it_type = TCE_PCI;
 395 }
 396
 397 static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose)
 398 {
 399         struct iommu_table *tbl;
 400         const __be64 *basep, *swinvp;
 401         const __be32 *sizep;
 402
 403         basep = of_get_property(hose->dn, "linux,tce-base", NULL);
 404         sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
 405         if (basep == NULL || sizep == NULL) {
 406                 pr_err("PCI: %s has missing tce entries !\n",
 407                        hose->dn->full_name);
 408                 return NULL;
 409         }
 410         tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
 411         if (WARN_ON(!tbl))
 412                 return NULL;
 413         pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
 414                                   be32_to_cpup(sizep), 0);
 415         iommu_init_table(tbl, hose->node);
 416
 417         /* Deal with SW invalidated TCEs when needed (BML way) */
 418         swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
 419                                  NULL);
 420         if (swinvp) {
 421                 tbl->it_busno = swinvp[1];
 422                 tbl->it_index = (unsigned long)ioremap(swinvp[0], 8);
 423                 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
 424         }
 425         return tbl;
 426 }
 427
 428 static void pnv_pci_dma_fallback_setup(struct pci_controller *hose,
 429                                        struct pci_dev *pdev)
 430 {
 431         struct device_node *np = pci_bus_to_OF_node(hose->bus);
 432         struct pci_dn *pdn;
 433
 434         if (np == NULL)
 435                 return;
 436         pdn = PCI_DN(np);
 437         if (!pdn->iommu_table)
 438                 pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
 439         if (!pdn->iommu_table)
 440                 return;
 441         set_iommu_table_base(&pdev->dev, pdn->iommu_table);
 442 }
 443
 444 static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
 445 {
 446         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 447         struct pnv_phb *phb = hose->private_data;
 448
 449         /* If we have no phb structure, try to setup a fallback based on
 450          * the device-tree (RTAS PCI for example)
 451          */
 452         if (phb && phb->dma_dev_setup)
 453                 phb->dma_dev_setup(phb, pdev);
 454         else
 455                 pnv_pci_dma_fallback_setup(hose, pdev);
 456 }
 457
 458 void pnv_pci_shutdown(void)
 459 {
 460         struct pci_controller *hose;
 461
 462         list_for_each_entry(hose, &hose_list, list_node) {
 463                 struct pnv_phb *phb = hose->private_data;
 464
 465                 if (phb && phb->shutdown)
 466                         phb->shutdown(phb);
 467         }
 468 }
 469
 470 /* Fixup wrong class code in p7ioc and p8 root complex */
 471 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
 472 {
 473         dev->class = PCI_CLASS_BRIDGE_PCI << 8;
 474 }
 475 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
 476
 477 static int pnv_pci_probe_mode(struct pci_bus *bus)
 478 {
 479         struct pci_controller *hose = pci_bus_to_host(bus);
 480         const __be64 *tstamp;
 481         u64 now, target;
 482
 483
 484         /* We hijack this as a way to ensure we have waited long
 485          * enough since the reset was lifted on the PCI bus
 486          */
 487         if (bus != hose->bus)
 488                 return PCI_PROBE_NORMAL;
 489         tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL);
 490         if (!tstamp || !*tstamp)
 491                 return PCI_PROBE_NORMAL;
 492
 493         now = mftb() / tb_ticks_per_usec;
 494         target = (be64_to_cpup(tstamp) / tb_ticks_per_usec)
 495                 + PCI_RESET_DELAY_US;
 496
 497         pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n",
 498                  hose->global_number, target, now);
 499
 500         if (now < target)
 501                 msleep((target - now + 999) / 1000);
 502
 503         return PCI_PROBE_NORMAL;
 504 }
 505
 506 void __init pnv_pci_init(void)
 507 {
 508         struct device_node *np;
 509
 510         pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
 511
 512         /* OPAL absent, try POPAL first then RTAS detection of PHBs */
 513         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 514 #ifdef CONFIG_PPC_POWERNV_RTAS
 515                 init_pci_config_tokens();
 516                 find_and_init_phbs();
 517 #endif /* CONFIG_PPC_POWERNV_RTAS */
 518         }
 519         /* OPAL is here, do our normal stuff */
 520         else {
 521                 int found_ioda = 0;
 522
 523                 /* Look for IODA IO-Hubs. We don't support mixing IODA
 524                  * and p5ioc2 due to the need to change some global
 525                  * probing flags
 526                  */
 527                 for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
 528                         pnv_pci_init_ioda_hub(np);
 529                         found_ioda = 1;
 530                 }
 531
 532                 /* Look for p5ioc2 IO-Hubs */
 533                 if (!found_ioda)
 534                         for_each_compatible_node(np, NULL, "ibm,p5ioc2")
 535                                 pnv_pci_init_p5ioc2_hub(np);
 536
 537                 /* Look for ioda2 built-in PHB3's */
 538                 for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
 539                         pnv_pci_init_ioda2_phb(np);
 540         }
 541
 542         /* Setup the linkage between OF nodes and PHBs */
 543         pci_devs_phb_init();
 544
 545         /* Configure IOMMU DMA hooks */
 546         ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
 547         ppc_md.tce_build = pnv_tce_build;
 548         ppc_md.tce_free = pnv_tce_free;
 549         ppc_md.tce_get = pnv_tce_get;
 550         ppc_md.pci_probe_mode = pnv_pci_probe_mode;
 551         set_pci_dma_ops(&dma_iommu_ops);
 552
 553         /* Configure MSIs */
 554 #ifdef CONFIG_PCI_MSI
 555         ppc_md.msi_check_device = pnv_msi_check_device;
 556         ppc_md.setup_msi_irqs = pnv_setup_msi_irqs;
 557         ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
 558 #endif
 559 }