arch/powerpc/platforms/8xx/mpc885ads_setup.c

   1 /*
   2  * Platform setup for the Freescale mpc885ads board
   3  *
   4  * Vitaly Bordug <vbordug@ru.mvista.com>
   5  *
   6  * Copyright 2005 MontaVista Software Inc.
   7  *
   8  * Heavily modified by Scott Wood <scottwood@freescale.com>
   9  * Copyright 2007 Freescale Semiconductor, Inc.
  10  *
  11  * This file is licensed under the terms of the GNU General Public License
  12  * version 2. This program is licensed "as is" without any warranty of any
  13  * kind, whether express or implied.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/param.h>
  19 #include <linux/string.h>
  20 #include <linux/ioport.h>
  21 #include <linux/device.h>
  22 #include <linux/delay.h>
  23
  24 #include <linux/fs_enet_pd.h>
  25 #include <linux/fs_uart_pd.h>
  26 #include <linux/fsl_devices.h>
  27 #include <linux/mii.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_fdt.h>
  30 #include <linux/of_platform.h>
  31
  32 #include <asm/delay.h>
  33 #include <asm/io.h>
  34 #include <asm/machdep.h>
  35 #include <asm/page.h>
  36 #include <asm/processor.h>
  37 #include <asm/time.h>
  38 #include <asm/mpc8xx.h>
  39 #include <asm/8xx_immap.h>
  40 #include <asm/cpm1.h>
  41 #include <asm/fs_pd.h>
  42 #include <asm/udbg.h>
  43
  44 #include "mpc885ads.h"
  45 #include "mpc8xx.h"
  46
  47 static u32 __iomem *bcsr, *bcsr5;
  48
  49 #ifdef CONFIG_PCMCIA_M8XX
  50 static void pcmcia_hw_setup(int slot, int enable)
  51 {
  52         if (enable)
  53                 clrbits32(&bcsr[1], BCSR1_PCCEN);
  54         else
  55                 setbits32(&bcsr[1], BCSR1_PCCEN);
  56 }
  57
  58 static int pcmcia_set_voltage(int slot, int vcc, int vpp)
  59 {
  60         u32 reg = 0;
  61
  62         switch (vcc) {
  63         case 0:
  64                 break;
  65         case 33:
  66                 reg |= BCSR1_PCCVCC0;
  67                 break;
  68         case 50:
  69                 reg |= BCSR1_PCCVCC1;
  70                 break;
  71         default:
  72                 return 1;
  73         }
  74
  75         switch (vpp) {
  76         case 0:
  77                 break;
  78         case 33:
  79         case 50:
  80                 if (vcc == vpp)
  81                         reg |= BCSR1_PCCVPP1;
  82                 else
  83                         return 1;
  84                 break;
  85         case 120:
  86                 if ((vcc == 33) || (vcc == 50))
  87                         reg |= BCSR1_PCCVPP0;
  88                 else
  89                         return 1;
  90         default:
  91                 return 1;
  92         }
  93
  94         /* first, turn off all power */
  95         clrbits32(&bcsr[1], 0x00610000);
  96
  97         /* enable new powersettings */
  98         setbits32(&bcsr[1], reg);
  99
 100         return 0;
 101 }
 102 #endif
 103
 104 struct cpm_pin {
 105         int port, pin, flags;
 106 };
 107
 108 static struct cpm_pin mpc885ads_pins[] = {
 109         /* SMC1 */
 110         {CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
 111         {CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
 112
 113         /* SMC2 */
 114 #ifndef CONFIG_MPC8xx_SECOND_ETH_FEC2
 115         {CPM_PORTE, 21, CPM_PIN_INPUT}, /* RX */
 116         {CPM_PORTE, 20, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
 117 #endif
 118
 119         /* SCC3 */
 120         {CPM_PORTA, 9, CPM_PIN_INPUT}, /* RX */
 121         {CPM_PORTA, 8, CPM_PIN_INPUT}, /* TX */
 122         {CPM_PORTC, 4, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* RENA */
 123         {CPM_PORTC, 5, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CLSN */
 124         {CPM_PORTE, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
 125         {CPM_PORTE, 17, CPM_PIN_INPUT}, /* CLK5 */
 126         {CPM_PORTE, 16, CPM_PIN_INPUT}, /* CLK6 */
 127
 128         /* MII1 */
 129         {CPM_PORTA, 0, CPM_PIN_INPUT},
 130         {CPM_PORTA, 1, CPM_PIN_INPUT},
 131         {CPM_PORTA, 2, CPM_PIN_INPUT},
 132         {CPM_PORTA, 3, CPM_PIN_INPUT},
 133         {CPM_PORTA, 4, CPM_PIN_OUTPUT},
 134         {CPM_PORTA, 10, CPM_PIN_OUTPUT},
 135         {CPM_PORTA, 11, CPM_PIN_OUTPUT},
 136         {CPM_PORTB, 19, CPM_PIN_INPUT},
 137         {CPM_PORTB, 31, CPM_PIN_INPUT},
 138         {CPM_PORTC, 12, CPM_PIN_INPUT},
 139         {CPM_PORTC, 13, CPM_PIN_INPUT},
 140         {CPM_PORTE, 30, CPM_PIN_OUTPUT},
 141         {CPM_PORTE, 31, CPM_PIN_OUTPUT},
 142
 143         /* MII2 */
 144 #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
 145         {CPM_PORTE, 14, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 146         {CPM_PORTE, 15, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 147         {CPM_PORTE, 16, CPM_PIN_OUTPUT},
 148         {CPM_PORTE, 17, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 149         {CPM_PORTE, 18, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 150         {CPM_PORTE, 19, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 151         {CPM_PORTE, 20, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
 152         {CPM_PORTE, 21, CPM_PIN_OUTPUT},
 153         {CPM_PORTE, 22, CPM_PIN_OUTPUT},
 154         {CPM_PORTE, 23, CPM_PIN_OUTPUT},
 155         {CPM_PORTE, 24, CPM_PIN_OUTPUT},
 156         {CPM_PORTE, 25, CPM_PIN_OUTPUT},
 157         {CPM_PORTE, 26, CPM_PIN_OUTPUT},
 158         {CPM_PORTE, 27, CPM_PIN_OUTPUT},
 159         {CPM_PORTE, 28, CPM_PIN_OUTPUT},
 160         {CPM_PORTE, 29, CPM_PIN_OUTPUT},
 161 #endif
 162         /* I2C */
 163         {CPM_PORTB, 26, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
 164         {CPM_PORTB, 27, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
 165 };
 166
 167 static void __init init_ioports(void)
 168 {
 169         int i;
 170
 171         for (i = 0; i < ARRAY_SIZE(mpc885ads_pins); i++) {
 172                 struct cpm_pin *pin = &mpc885ads_pins[i];
 173                 cpm1_set_pin(pin->port, pin->pin, pin->flags);
 174         }
 175
 176         cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
 177         cpm1_clk_setup(CPM_CLK_SMC2, CPM_BRG2, CPM_CLK_RTX);
 178         cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_TX);
 179         cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_RX);
 180
 181         /* Set FEC1 and FEC2 to MII mode */
 182         clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
 183 }
 184
 185 static void __init mpc885ads_setup_arch(void)
 186 {
 187         struct device_node *np;
 188
 189         cpm_reset();
 190         init_ioports();
 191
 192         np = of_find_compatible_node(NULL, NULL, "fsl,mpc885ads-bcsr");
 193         if (!np) {
 194                 printk(KERN_CRIT "Could not find fsl,mpc885ads-bcsr node\n");
 195                 return;
 196         }
 197
 198         bcsr = of_iomap(np, 0);
 199         bcsr5 = of_iomap(np, 1);
 200         of_node_put(np);
 201
 202         if (!bcsr || !bcsr5) {
 203                 printk(KERN_CRIT "Could not remap BCSR\n");
 204                 return;
 205         }
 206
 207         clrbits32(&bcsr[1], BCSR1_RS232EN_1);
 208 #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
 209         setbits32(&bcsr[1], BCSR1_RS232EN_2);
 210 #else
 211         clrbits32(&bcsr[1], BCSR1_RS232EN_2);
 212 #endif
 213
 214         clrbits32(bcsr5, BCSR5_MII1_EN);
 215         setbits32(bcsr5, BCSR5_MII1_RST);
 216         udelay(1000);
 217         clrbits32(bcsr5, BCSR5_MII1_RST);
 218
 219 #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
 220         clrbits32(bcsr5, BCSR5_MII2_EN);
 221         setbits32(bcsr5, BCSR5_MII2_RST);
 222         udelay(1000);
 223         clrbits32(bcsr5, BCSR5_MII2_RST);
 224 #else
 225         setbits32(bcsr5, BCSR5_MII2_EN);
 226 #endif
 227
 228 #ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
 229         clrbits32(&bcsr[4], BCSR4_ETH10_RST);
 230         udelay(1000);
 231         setbits32(&bcsr[4], BCSR4_ETH10_RST);
 232
 233         setbits32(&bcsr[1], BCSR1_ETHEN);
 234
 235         np = of_find_node_by_path("/soc@ff000000/cpm@9c0/serial@a80");
 236 #else
 237         np = of_find_node_by_path("/soc@ff000000/cpm@9c0/ethernet@a40");
 238 #endif
 239
 240         /* The SCC3 enet registers overlap the SMC1 registers, so
 241          * one of the two must be removed from the device tree.
 242          */
 243
 244         if (np) {
 245                 of_detach_node(np);
 246                 of_node_put(np);
 247         }
 248
 249 #ifdef CONFIG_PCMCIA_M8XX
 250         /* Set up board specific hook-ups.*/
 251         m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup;
 252         m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage;
 253 #endif
 254 }
 255
 256 static int __init mpc885ads_probe(void)
 257 {
 258         unsigned long root = of_get_flat_dt_root();
 259         return of_flat_dt_is_compatible(root, "fsl,mpc885ads");
 260 }
 261
 262 static struct of_device_id __initdata of_bus_ids[] = {
 263         { .name = "soc", },
 264         { .name = "cpm", },
 265         { .name = "localbus", },
 266         {},
 267 };
 268
 269 static int __init declare_of_platform_devices(void)
 270 {
 271         /* Publish the QE devices */
 272         of_platform_bus_probe(NULL, of_bus_ids, NULL);
 273
 274         return 0;
 275 }
 276 machine_device_initcall(mpc885_ads, declare_of_platform_devices);
 277
 278 define_machine(mpc885_ads) {
 279         .name                   = "Freescale MPC885 ADS",
 280         .probe                  = mpc885ads_probe,
 281         .setup_arch             = mpc885ads_setup_arch,
 282         .init_IRQ               = mpc8xx_pics_init,
 283         .get_irq                = mpc8xx_get_irq,
 284         .restart                = mpc8xx_restart,
 285         .calibrate_decr         = mpc8xx_calibrate_decr,
 286         .set_rtc_time           = mpc8xx_set_rtc_time,
 287         .get_rtc_time           = mpc8xx_get_rtc_time,
 288         .progress               = udbg_progress,
 289 };