2 * Author: Andy Fleming <afleming@freescale.com>
3 * Kumar Gala <galak@kernel.crashing.org>
5 * Copyright 2006-2008, 2011-2012 Freescale Semiconductor Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/stddef.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/of_address.h>
19 #include <linux/kexec.h>
20 #include <linux/highmem.h>
21 #include <linux/cpu.h>
23 #include <asm/machdep.h>
24 #include <asm/pgtable.h>
27 #include <asm/cacheflush.h>
28 #include <asm/dbell.h>
29 #include <asm/fsl_guts.h>
31 #include <sysdev/fsl_soc.h>
32 #include <sysdev/mpic.h>
35 struct epapr_spin_table {
44 static struct ccsr_guts __iomem *guts;
49 static void mpc85xx_timebase_freeze(int freeze)
53 mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1;
55 setbits32(&guts->devdisr, mask);
57 clrbits32(&guts->devdisr, mask);
59 in_be32(&guts->devdisr);
62 static void mpc85xx_give_timebase(void)
66 local_irq_save(flags);
72 mpc85xx_timebase_freeze(1);
75 * e5500/e6500 have a workaround for erratum A-006958 in place
76 * that will reread the timebase until TBL is non-zero.
77 * That would be a bad thing when the timebase is frozen.
79 * Thus, we read it manually, and instead of checking that
80 * TBL is non-zero, we ensure that TB does not change. We don't
81 * do that for the main mftb implementation, because it requires
87 asm volatile("mfspr %0, %1" : "=r" (timebase) :
92 asm volatile("mfspr %0, %1" : "=r" (timebase) :
94 } while (prev != timebase);
105 mpc85xx_timebase_freeze(0);
107 local_irq_restore(flags);
110 static void mpc85xx_take_timebase(void)
114 local_irq_save(flags);
120 set_tb(timebase >> 32, timebase & 0xffffffff);
124 local_irq_restore(flags);
127 #ifdef CONFIG_HOTPLUG_CPU
128 static void smp_85xx_mach_cpu_die(void)
130 unsigned int cpu = smp_processor_id();
135 generic_set_cpu_dead(cpu);
140 __flush_disable_L1();
141 tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE|HID0_SLEEP)) | HID0_NAP;
142 mtspr(SPRN_HID0, tmp);
145 /* Enter NAP mode. */
157 static inline void flush_spin_table(void *spin_table)
159 flush_dcache_range((ulong)spin_table,
160 (ulong)spin_table + sizeof(struct epapr_spin_table));
163 static inline u32 read_spin_table_addr_l(void *spin_table)
165 flush_dcache_range((ulong)spin_table,
166 (ulong)spin_table + sizeof(struct epapr_spin_table));
167 return in_be32(&((struct epapr_spin_table *)spin_table)->addr_l);
170 static int smp_85xx_kick_cpu(int nr)
173 const u64 *cpu_rel_addr;
174 __iomem struct epapr_spin_table *spin_table;
175 struct device_node *np;
176 int hw_cpu = get_hard_smp_processor_id(nr);
180 WARN_ON(nr < 0 || nr >= NR_CPUS);
181 WARN_ON(hw_cpu < 0 || hw_cpu >= NR_CPUS);
183 pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr);
185 np = of_get_cpu_node(nr, NULL);
186 cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL);
188 if (cpu_rel_addr == NULL) {
189 printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr);
194 * A secondary core could be in a spinloop in the bootpage
195 * (0xfffff000), somewhere in highmem, or somewhere in lowmem.
196 * The bootpage and highmem can be accessed via ioremap(), but
197 * we need to directly access the spinloop if its in lowmem.
199 ioremappable = *cpu_rel_addr > virt_to_phys(high_memory);
201 /* Map the spin table */
203 spin_table = ioremap_prot(*cpu_rel_addr,
204 sizeof(struct epapr_spin_table), _PAGE_COHERENT);
206 spin_table = phys_to_virt(*cpu_rel_addr);
208 local_irq_save(flags);
210 #ifdef CONFIG_HOTPLUG_CPU
211 /* Corresponding to generic_set_cpu_dead() */
212 generic_set_cpu_up(nr);
214 if (system_state == SYSTEM_RUNNING) {
216 * To keep it compatible with old boot program which uses
217 * cache-inhibit spin table, we need to flush the cache
218 * before accessing spin table to invalidate any staled data.
219 * We also need to flush the cache after writing to spin
220 * table to push data out.
222 flush_spin_table(spin_table);
223 out_be32(&spin_table->addr_l, 0);
224 flush_spin_table(spin_table);
227 * We don't set the BPTR register here since it already points
228 * to the boot page properly.
233 * wait until core is ready...
234 * We need to invalidate the stale data, in case the boot
235 * loader uses a cache-inhibited spin table.
237 if (!spin_event_timeout(
238 read_spin_table_addr_l(spin_table) == 1,
240 pr_err("%s: timeout waiting for core %d to reset\n",
246 /* clear the acknowledge status */
247 __secondary_hold_acknowledge = -1;
250 flush_spin_table(spin_table);
251 out_be32(&spin_table->pir, hw_cpu);
252 out_be32(&spin_table->addr_l, __pa(__early_start));
253 flush_spin_table(spin_table);
255 /* Wait a bit for the CPU to ack. */
256 if (!spin_event_timeout(__secondary_hold_acknowledge == hw_cpu,
258 pr_err("%s: timeout waiting for core %d to ack\n",
265 smp_generic_kick_cpu(nr);
267 flush_spin_table(spin_table);
268 out_be32(&spin_table->pir, hw_cpu);
269 out_be64((u64 *)(&spin_table->addr_h),
270 __pa((u64)*((unsigned long long *)generic_secondary_smp_init)));
271 flush_spin_table(spin_table);
274 local_irq_restore(flags);
282 struct smp_ops_t smp_85xx_ops = {
283 .kick_cpu = smp_85xx_kick_cpu,
284 .cpu_bootable = smp_generic_cpu_bootable,
285 #ifdef CONFIG_HOTPLUG_CPU
286 .cpu_disable = generic_cpu_disable,
287 .cpu_die = generic_cpu_die,
290 .give_timebase = smp_generic_give_timebase,
291 .take_timebase = smp_generic_take_timebase,
296 atomic_t kexec_down_cpus = ATOMIC_INIT(0);
298 void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
303 atomic_inc(&kexec_down_cpus);
309 static void mpc85xx_smp_kexec_down(void *arg)
311 if (ppc_md.kexec_cpu_down)
312 ppc_md.kexec_cpu_down(0,1);
315 static void map_and_flush(unsigned long paddr)
317 struct page *page = pfn_to_page(paddr >> PAGE_SHIFT);
318 unsigned long kaddr = (unsigned long)kmap(page);
320 flush_dcache_range(kaddr, kaddr + PAGE_SIZE);
325 * Before we reset the other cores, we need to flush relevant cache
326 * out to memory so we don't get anything corrupted, some of these flushes
327 * are performed out of an overabundance of caution as interrupts are not
328 * disabled yet and we can switch cores
330 static void mpc85xx_smp_flush_dcache_kexec(struct kimage *image)
332 kimage_entry_t *ptr, entry;
336 if (image->type == KEXEC_TYPE_DEFAULT) {
337 /* normal kexec images are stored in temporary pages */
338 for (ptr = &image->head; (entry = *ptr) && !(entry & IND_DONE);
339 ptr = (entry & IND_INDIRECTION) ?
340 phys_to_virt(entry & PAGE_MASK) : ptr + 1) {
341 if (!(entry & IND_DESTINATION)) {
342 map_and_flush(entry);
345 /* flush out last IND_DONE page */
346 map_and_flush(entry);
348 /* crash type kexec images are copied to the crash region */
349 for (i = 0; i < image->nr_segments; i++) {
350 struct kexec_segment *seg = &image->segment[i];
351 for (paddr = seg->mem; paddr < seg->mem + seg->memsz;
352 paddr += PAGE_SIZE) {
353 map_and_flush(paddr);
358 /* also flush the kimage struct to be passed in as well */
359 flush_dcache_range((unsigned long)image,
360 (unsigned long)image + sizeof(*image));
363 static void mpc85xx_smp_machine_kexec(struct kimage *image)
365 int timeout = INT_MAX;
366 int i, num_cpus = num_present_cpus();
368 mpc85xx_smp_flush_dcache_kexec(image);
370 if (image->type == KEXEC_TYPE_DEFAULT)
371 smp_call_function(mpc85xx_smp_kexec_down, NULL, 0);
373 while ( (atomic_read(&kexec_down_cpus) != (num_cpus - 1)) &&
380 printk(KERN_ERR "Unable to bring down secondary cpu(s)");
382 for_each_online_cpu(i)
384 if ( i == smp_processor_id() ) continue;
388 default_machine_kexec(image);
390 #endif /* CONFIG_KEXEC */
392 static void smp_85xx_setup_cpu(int cpu_nr)
394 if (smp_85xx_ops.probe == smp_mpic_probe)
395 mpic_setup_this_cpu();
397 if (cpu_has_feature(CPU_FTR_DBELL))
398 doorbell_setup_this_cpu();
401 static const struct of_device_id mpc85xx_smp_guts_ids[] = {
402 { .compatible = "fsl,mpc8572-guts", },
403 { .compatible = "fsl,p1020-guts", },
404 { .compatible = "fsl,p1021-guts", },
405 { .compatible = "fsl,p1022-guts", },
406 { .compatible = "fsl,p1023-guts", },
407 { .compatible = "fsl,p2020-guts", },
411 void __init mpc85xx_smp_init(void)
413 struct device_node *np;
415 smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
417 np = of_find_node_by_type(NULL, "open-pic");
419 smp_85xx_ops.probe = smp_mpic_probe;
420 smp_85xx_ops.message_pass = smp_mpic_message_pass;
423 if (cpu_has_feature(CPU_FTR_DBELL)) {
425 * If left NULL, .message_pass defaults to
426 * smp_muxed_ipi_message_pass
428 smp_85xx_ops.message_pass = NULL;
429 smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
432 np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
434 guts = of_iomap(np, 0);
437 pr_err("%s: Could not map guts node address\n",
441 smp_85xx_ops.give_timebase = mpc85xx_give_timebase;
442 smp_85xx_ops.take_timebase = mpc85xx_take_timebase;
443 #ifdef CONFIG_HOTPLUG_CPU
444 ppc_md.cpu_die = smp_85xx_mach_cpu_die;
448 smp_ops = &smp_85xx_ops;
451 ppc_md.kexec_cpu_down = mpc85xx_smp_kexec_cpu_down;
452 ppc_md.machine_kexec = mpc85xx_smp_machine_kexec;