arch/powerpc/platforms/85xx/corenet_generic.c

   1 /*
   2  * Corenet based SoC DS Setup
   3  *
   4  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
   5  *
   6  * Copyright 2009-2011 Freescale Semiconductor Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/kdev_t.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19
  20 #include <asm/time.h>
  21 #include <asm/machdep.h>
  22 #include <asm/pci-bridge.h>
  23 #include <asm/ppc-pci.h>
  24 #include <mm/mmu_decl.h>
  25 #include <asm/prom.h>
  26 #include <asm/udbg.h>
  27 #include <asm/mpic.h>
  28 #include <asm/ehv_pic.h>
  29 #include <asm/qe_ic.h>
  30
  31 #include <linux/of_platform.h>
  32 #include <sysdev/fsl_soc.h>
  33 #include <sysdev/fsl_pci.h>
  34 #include "smp.h"
  35 #include "mpc85xx.h"
  36
  37 void __init corenet_gen_pic_init(void)
  38 {
  39         struct mpic *mpic;
  40         unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
  41                 MPIC_NO_RESET;
  42
  43         struct device_node *np;
  44
  45         if (ppc_md.get_irq == mpic_get_coreint_irq)
  46                 flags |= MPIC_ENABLE_COREINT;
  47
  48         mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC  ");
  49         BUG_ON(mpic == NULL);
  50
  51         mpic_init(mpic);
  52
  53         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
  54         if (np) {
  55                 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
  56                                 qe_ic_cascade_high_mpic);
  57                 of_node_put(np);
  58         }
  59 }
  60
  61 /*
  62  * Setup the architecture
  63  */
  64 void __init corenet_gen_setup_arch(void)
  65 {
  66         mpc85xx_smp_init();
  67
  68         swiotlb_detect_4g();
  69
  70         pr_info("%s board\n", ppc_md.name);
  71
  72         mpc85xx_qe_init();
  73 }
  74
  75 static const struct of_device_id of_device_ids[] = {
  76         {
  77                 .compatible     = "simple-bus"
  78         },
  79         {
  80                 .compatible     = "fsl,srio",
  81         },
  82         {
  83                 .compatible     = "fsl,p4080-pcie",
  84         },
  85         {
  86                 .compatible     = "fsl,qoriq-pcie-v2.2",
  87         },
  88         {
  89                 .compatible     = "fsl,qoriq-pcie-v2.3",
  90         },
  91         {
  92                 .compatible     = "fsl,qoriq-pcie-v2.4",
  93         },
  94         {
  95                 .compatible     = "fsl,qoriq-pcie-v3.0",
  96         },
  97         {
  98                 .compatible     = "fsl,qe",
  99         },
 100         /* The following two are for the Freescale hypervisor */
 101         {
 102                 .name           = "hypervisor",
 103         },
 104         {
 105                 .name           = "handles",
 106         },
 107         {}
 108 };
 109
 110 int __init corenet_gen_publish_devices(void)
 111 {
 112         return of_platform_bus_probe(NULL, of_device_ids, NULL);
 113 }
 114
 115 static const char * const boards[] __initconst = {
 116         "fsl,P2041RDB",
 117         "fsl,P3041DS",
 118         "fsl,OCA4080",
 119         "fsl,P4080DS",
 120         "fsl,P5020DS",
 121         "fsl,P5040DS",
 122         "fsl,T4240QDS",
 123         "fsl,B4860QDS",
 124         "fsl,B4420QDS",
 125         "fsl,B4220QDS",
 126         "fsl,T1040QDS",
 127         "fsl,T1042QDS",
 128         "keymile,kmcoge4",
 129         NULL
 130 };
 131
 132 static const char * const hv_boards[] __initconst = {
 133         "fsl,P2041RDB-hv",
 134         "fsl,P3041DS-hv",
 135         "fsl,OCA4080-hv",
 136         "fsl,P4080DS-hv",
 137         "fsl,P5020DS-hv",
 138         "fsl,P5040DS-hv",
 139         "fsl,T4240QDS-hv",
 140         "fsl,B4860QDS-hv",
 141         "fsl,B4420QDS-hv",
 142         "fsl,B4220QDS-hv",
 143         "fsl,T1040QDS-hv",
 144         "fsl,T1042QDS-hv",
 145         NULL
 146 };
 147
 148 /*
 149  * Called very early, device-tree isn't unflattened
 150  */
 151 static int __init corenet_generic_probe(void)
 152 {
 153         unsigned long root = of_get_flat_dt_root();
 154 #ifdef CONFIG_SMP
 155         extern struct smp_ops_t smp_85xx_ops;
 156 #endif
 157
 158         if (of_flat_dt_match(root, boards))
 159                 return 1;
 160
 161         /* Check if we're running under the Freescale hypervisor */
 162         if (of_flat_dt_match(root, hv_boards)) {
 163                 ppc_md.init_IRQ = ehv_pic_init;
 164                 ppc_md.get_irq = ehv_pic_get_irq;
 165                 ppc_md.restart = fsl_hv_restart;
 166                 ppc_md.power_off = fsl_hv_halt;
 167                 ppc_md.halt = fsl_hv_halt;
 168 #ifdef CONFIG_SMP
 169                 /*
 170                  * Disable the timebase sync operations because we can't write
 171                  * to the timebase registers under the hypervisor.
 172                   */
 173                 smp_85xx_ops.give_timebase = NULL;
 174                 smp_85xx_ops.take_timebase = NULL;
 175 #endif
 176                 return 1;
 177         }
 178
 179         return 0;
 180 }
 181
 182 define_machine(corenet_generic) {
 183         .name                   = "CoreNet Generic",
 184         .probe                  = corenet_generic_probe,
 185         .setup_arch             = corenet_gen_setup_arch,
 186         .init_IRQ               = corenet_gen_pic_init,
 187 #ifdef CONFIG_PCI
 188         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 189         .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 190 #endif
 191         .get_irq                = mpic_get_coreint_irq,
 192         .restart                = fsl_rstcr_restart,
 193         .calibrate_decr         = generic_calibrate_decr,
 194         .progress               = udbg_progress,
 195 #ifdef CONFIG_PPC64
 196         .power_save             = book3e_idle,
 197 #else
 198         .power_save             = e500_idle,
 199 #endif
 200 };
 201
 202 machine_arch_initcall(corenet_generic, corenet_gen_publish_devices);
 203
 204 #ifdef CONFIG_SWIOTLB
 205 machine_arch_initcall(corenet_generic, swiotlb_setup_bus_notifier);
 206 #endif