2 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
4 * Author: John Rigby <jrigby@freescale.com>
6 * Implements the clk api defined in include/linux/clk.h
8 * Original based on linux/arch/arm/mach-integrator/clock.c
10 * Copyright (C) 2004 ARM Limited.
11 * Written by Deep Blue Solutions Limited.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/errno.h>
20 #include <linux/err.h>
21 #include <linux/module.h>
22 #include <linux/string.h>
23 #include <linux/clk.h>
24 #include <linux/mutex.h>
27 #include <linux/of_platform.h>
28 #include <asm/mpc5xxx.h>
29 #include <asm/mpc5121.h>
30 #include <asm/clk_interface.h>
36 static int clocks_initialized;
38 #define CLK_HAS_RATE 0x1 /* has rate in MHz */
39 #define CLK_HAS_CTRL 0x2 /* has control reg and bit */
42 struct list_head node;
48 void (*calc) (struct clk *);
50 int reg, bit; /* CLK_HAS_CTRL */
51 int div_shift; /* only used by generic_div_clk_calc */
54 static LIST_HEAD(clocks);
55 static DEFINE_MUTEX(clocks_mutex);
57 static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
59 struct clk *p, *clk = ERR_PTR(-ENOENT);
63 if (dev == NULL || id == NULL)
66 mutex_lock(&clocks_mutex);
67 list_for_each_entry(p, &clocks, node) {
68 dev_match = id_match = 0;
72 if (strcmp(id, p->name) == 0)
74 if ((dev_match || id_match) && try_module_get(p->owner)) {
79 mutex_unlock(&clocks_mutex);
85 static void dump_clocks(void)
89 mutex_lock(&clocks_mutex);
90 printk(KERN_INFO "CLOCKS:\n");
91 list_for_each_entry(p, &clocks, node) {
92 pr_info(" %s=%ld", p->name, p->rate);
94 pr_cont(" %s=%ld", p->parent->name,
96 if (p->flags & CLK_HAS_CTRL)
97 pr_cont(" reg/bit=%d/%d", p->reg, p->bit);
100 mutex_unlock(&clocks_mutex);
102 #define DEBUG_CLK_DUMP() dump_clocks()
104 #define DEBUG_CLK_DUMP()
108 static void mpc5121_clk_put(struct clk *clk)
110 module_put(clk->owner);
115 struct mpc512x_clockctl {
116 u32 spmr; /* System PLL Mode Reg */
117 u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
118 u32 scfr1; /* System Clk Freq Reg 1 */
119 u32 scfr2; /* System Clk Freq Reg 2 */
121 u32 bcr; /* Bread Crumb Reg */
122 u32 pccr[NRPSC]; /* PSC Clk Ctrl Reg 0-11 */
123 u32 spccr; /* SPDIF Clk Ctrl Reg */
124 u32 cccr; /* CFM Clk Ctrl Reg */
125 u32 dccr; /* DIU Clk Cnfg Reg */
128 static struct mpc512x_clockctl __iomem *clockctl;
130 static int mpc5121_clk_enable(struct clk *clk)
134 if (clk->flags & CLK_HAS_CTRL) {
135 mask = in_be32(&clockctl->sccr[clk->reg]);
136 mask |= 1 << clk->bit;
137 out_be32(&clockctl->sccr[clk->reg], mask);
142 static void mpc5121_clk_disable(struct clk *clk)
146 if (clk->flags & CLK_HAS_CTRL) {
147 mask = in_be32(&clockctl->sccr[clk->reg]);
148 mask &= ~(1 << clk->bit);
149 out_be32(&clockctl->sccr[clk->reg], mask);
153 static unsigned long mpc5121_clk_get_rate(struct clk *clk)
155 if (clk->flags & CLK_HAS_RATE)
161 static long mpc5121_clk_round_rate(struct clk *clk, unsigned long rate)
166 static int mpc5121_clk_set_rate(struct clk *clk, unsigned long rate)
171 static int clk_register(struct clk *clk)
173 mutex_lock(&clocks_mutex);
174 list_add(&clk->node, &clocks);
175 mutex_unlock(&clocks_mutex);
179 static unsigned long spmf_mult(void)
182 * Convert spmf to multiplier
184 static int spmf_to_mult[] = {
190 int spmf = (in_be32(&clockctl->spmr) >> 24) & 0xf;
191 return spmf_to_mult[spmf];
194 static unsigned long sysdiv_div_x_2(void)
197 * Convert sysdiv to divisor x 2
198 * Some divisors have fractional parts so
199 * multiply by 2 then divide by this value
201 static int sysdiv_to_div_x_2[] = {
212 int sysdiv = (in_be32(&clockctl->scfr2) >> 26) & 0x3f;
213 return sysdiv_to_div_x_2[sysdiv];
216 static unsigned long ref_to_sys(unsigned long rate)
220 rate /= sysdiv_div_x_2();
225 static unsigned long sys_to_ref(unsigned long rate)
227 rate *= sysdiv_div_x_2();
234 static long ips_to_ref(unsigned long rate)
236 int ips_div = (in_be32(&clockctl->scfr1) >> 23) & 0x7;
238 rate *= ips_div; /* csb_clk = ips_clk * ips_div */
239 rate *= 2; /* sys_clk = csb_clk * 2 */
240 return sys_to_ref(rate);
243 static unsigned long devtree_getfreq(char *clockname)
245 struct device_node *np;
246 const unsigned int *prop;
247 unsigned int val = 0;
249 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
251 prop = of_get_property(np, clockname, NULL);
259 static void ref_clk_calc(struct clk *clk)
263 rate = devtree_getfreq("bus-frequency");
265 printk(KERN_ERR "No bus-frequency in dev tree\n");
269 clk->rate = ips_to_ref(rate);
272 static struct clk ref_clk = {
274 .calc = ref_clk_calc,
278 static void sys_clk_calc(struct clk *clk)
280 clk->rate = ref_to_sys(ref_clk.rate);
283 static struct clk sys_clk = {
285 .calc = sys_clk_calc,
288 static void diu_clk_calc(struct clk *clk)
290 int diudiv_x_2 = in_be32(&clockctl->scfr1) & 0xff;
301 static void viu_clk_calc(struct clk *clk)
310 static void half_clk_calc(struct clk *clk)
312 clk->rate = clk->parent->rate / 2;
315 static void generic_div_clk_calc(struct clk *clk)
317 int div = (in_be32(&clockctl->scfr1) >> clk->div_shift) & 0x7;
319 clk->rate = clk->parent->rate / div;
322 static void unity_clk_calc(struct clk *clk)
324 clk->rate = clk->parent->rate;
327 static struct clk csb_clk = {
329 .calc = half_clk_calc,
333 static void e300_clk_calc(struct clk *clk)
335 int spmf = (in_be32(&clockctl->spmr) >> 16) & 0xf;
336 int ratex2 = clk->parent->rate * spmf;
338 clk->rate = ratex2 / 2;
341 static struct clk e300_clk = {
343 .calc = e300_clk_calc,
347 static struct clk ips_clk = {
349 .calc = generic_div_clk_calc,
355 * Clocks controlled by SCCR1 (.reg = 0)
357 static struct clk lpc_clk = {
359 .flags = CLK_HAS_CTRL,
362 .calc = generic_div_clk_calc,
367 static struct clk nfc_clk = {
369 .flags = CLK_HAS_CTRL,
372 .calc = generic_div_clk_calc,
377 static struct clk pata_clk = {
379 .flags = CLK_HAS_CTRL,
382 .calc = unity_clk_calc,
387 * PSC clocks (bits 27 - 16)
388 * are setup elsewhere
391 static struct clk sata_clk = {
393 .flags = CLK_HAS_CTRL,
396 .calc = unity_clk_calc,
400 static struct clk fec_clk = {
402 .flags = CLK_HAS_CTRL,
405 .calc = unity_clk_calc,
409 static struct clk pci_clk = {
411 .flags = CLK_HAS_CTRL,
414 .calc = generic_div_clk_calc,
420 * Clocks controlled by SCCR2 (.reg = 1)
422 static struct clk diu_clk = {
424 .flags = CLK_HAS_CTRL,
427 .calc = diu_clk_calc,
430 static struct clk viu_clk = {
432 .flags = CLK_HAS_CTRL,
435 .calc = viu_clk_calc,
438 static struct clk axe_clk = {
440 .flags = CLK_HAS_CTRL,
443 .calc = unity_clk_calc,
447 static struct clk usb1_clk = {
449 .flags = CLK_HAS_CTRL,
452 .calc = unity_clk_calc,
456 static struct clk usb2_clk = {
458 .flags = CLK_HAS_CTRL,
461 .calc = unity_clk_calc,
465 static struct clk i2c_clk = {
467 .flags = CLK_HAS_CTRL,
470 .calc = unity_clk_calc,
474 static struct clk mscan_clk = {
476 .flags = CLK_HAS_CTRL,
479 .calc = unity_clk_calc,
483 static struct clk sdhc_clk = {
485 .flags = CLK_HAS_CTRL,
488 .calc = unity_clk_calc,
492 static struct clk mbx_bus_clk = {
493 .name = "mbx_bus_clk",
494 .flags = CLK_HAS_CTRL,
497 .calc = half_clk_calc,
501 static struct clk mbx_clk = {
503 .flags = CLK_HAS_CTRL,
506 .calc = unity_clk_calc,
510 static struct clk mbx_3d_clk = {
511 .name = "mbx_3d_clk",
512 .flags = CLK_HAS_CTRL,
515 .calc = generic_div_clk_calc,
516 .parent = &mbx_bus_clk,
520 static void psc_mclk_in_calc(struct clk *clk)
522 clk->rate = devtree_getfreq("psc_mclk_in");
524 clk->rate = 25000000;
527 static struct clk psc_mclk_in = {
528 .name = "psc_mclk_in",
529 .calc = psc_mclk_in_calc,
532 static struct clk spdif_txclk = {
533 .name = "spdif_txclk",
534 .flags = CLK_HAS_CTRL,
539 static struct clk spdif_rxclk = {
540 .name = "spdif_rxclk",
541 .flags = CLK_HAS_CTRL,
546 static void ac97_clk_calc(struct clk *clk)
548 /* ac97 bit clock is always 24.567 MHz */
549 clk->rate = 24567000;
552 static struct clk ac97_clk = {
553 .name = "ac97_clk_in",
554 .calc = ac97_clk_calc,
557 static struct clk *rate_clks[] = {
587 static void rate_clk_init(struct clk *clk)
591 clk->flags |= CLK_HAS_RATE;
595 "Could not initialize clk %s without a calc routine\n",
600 static void rate_clks_init(void)
602 struct clk **cpp, *clk;
605 while ((clk = *cpp++))
610 * There are two clk enable registers with 32 enable bits each
611 * psc clocks and device clocks are all stored in dev_clks
613 static struct clk dev_clks[2][32];
616 * Given a psc number return the dev_clk
619 static struct clk *psc_dev_clk(int pscnum)
627 clk = &dev_clks[reg][bit];
634 * PSC clock rate calculation
636 static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
638 unsigned long mclk_src = sys_clk.rate;
639 unsigned long mclk_div;
642 * Can only change value of mclk divider
643 * when the divider is disabled.
645 * Zero is not a valid divider so minimum
648 * disable/set divider/enable
650 out_be32(&clockctl->pccr[pscnum], 0);
651 out_be32(&clockctl->pccr[pscnum], 0x00020000);
652 out_be32(&clockctl->pccr[pscnum], 0x00030000);
654 if (in_be32(&clockctl->pccr[pscnum]) & 0x80) {
655 clk->rate = spdif_rxclk.rate;
659 switch ((in_be32(&clockctl->pccr[pscnum]) >> 14) & 0x3) {
661 mclk_src = sys_clk.rate;
664 mclk_src = ref_clk.rate;
667 mclk_src = psc_mclk_in.rate;
670 mclk_src = spdif_txclk.rate;
674 mclk_div = ((in_be32(&clockctl->pccr[pscnum]) >> 17) & 0x7fff) + 1;
675 clk->rate = mclk_src / mclk_div;
679 * Find all psc nodes in device tree and assign a clock
680 * with name "psc%d_mclk" and dev pointing at the device
681 * returned from of_find_device_by_node
683 static void psc_clks_init(void)
685 struct device_node *np;
686 struct platform_device *ofdev;
688 const char *psc_compat;
690 psc_compat = mpc512x_select_psc_compat();
694 for_each_compatible_node(np, NULL, psc_compat) {
695 if (!of_property_read_u32(np, "reg", ®)) {
696 int pscnum = (reg & 0xf00) >> 8;
697 struct clk *clk = psc_dev_clk(pscnum);
699 clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL;
700 ofdev = of_find_device_by_node(np);
701 clk->dev = &ofdev->dev;
703 * AC97 is special rate clock does
704 * not go through normal path
706 if (of_device_is_compatible(np, "fsl,mpc5121-psc-ac97"))
707 clk->rate = ac97_clk.rate;
709 psc_calc_rate(clk, pscnum, np);
710 sprintf(clk->name, "psc%d_mclk", pscnum);
717 static struct clk_interface mpc5121_clk_functions = {
718 .clk_get = mpc5121_clk_get,
719 .clk_enable = mpc5121_clk_enable,
720 .clk_disable = mpc5121_clk_disable,
721 .clk_get_rate = mpc5121_clk_get_rate,
722 .clk_put = mpc5121_clk_put,
723 .clk_round_rate = mpc5121_clk_round_rate,
724 .clk_set_rate = mpc5121_clk_set_rate,
725 .clk_set_parent = NULL,
726 .clk_get_parent = NULL,
729 int __init mpc5121_clk_init(void)
731 struct device_node *np;
733 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
735 clockctl = of_iomap(np, 0);
740 printk(KERN_ERR "Could not map clock control registers\n");
747 /* leave clockctl mapped forever */
748 /*iounmap(clockctl); */
750 clocks_initialized++;
751 clk_functions = mpc5121_clk_functions;