2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
17 * Author: Varun Sethi <varun.sethi@freescale.com>
18 * Author: Scott Wood <scotwood@freescale.com>
19 * Author: Mihai Caraman <mihai.caraman@freescale.com>
21 * This file is derived from arch/powerpc/kvm/booke_interrupts.S
24 #include <asm/ppc_asm.h>
25 #include <asm/kvm_asm.h>
28 #include <asm/asm-compat.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/bitsperlong.h>
33 #include <asm/exception-64e.h>
34 #include <asm/hw_irq.h>
35 #include <asm/irqflags.h>
37 #include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
40 #define LONGBYTES (BITS_PER_LONG / 8)
42 #define VCPU_GUEST_SPRG(n) (VCPU_GUEST_SPRGS + (n * LONGBYTES))
44 /* The host stack layout: */
45 #define HOST_R1 0 /* Implied by stwu. */
46 #define HOST_CALLEE_LR PPC_LR_STKOFF
47 #define HOST_RUN (HOST_CALLEE_LR + LONGBYTES)
49 * r2 is special: it holds 'current', and it made nonvolatile in the
50 * kernel with the -ffixed-r2 gcc option.
52 #define HOST_R2 (HOST_RUN + LONGBYTES)
53 #define HOST_CR (HOST_R2 + LONGBYTES)
54 #define HOST_NV_GPRS (HOST_CR + LONGBYTES)
55 #define __HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
56 #define HOST_NV_GPR(n) __HOST_NV_GPR(__REG_##n)
57 #define HOST_MIN_STACK_SIZE (HOST_NV_GPR(R31) + LONGBYTES)
58 #define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */
59 /* LR in caller stack frame. */
60 #define HOST_STACK_LR (HOST_STACK_SIZE + PPC_LR_STKOFF)
62 #define NEED_EMU 0x00000001 /* emulation -- save nv regs */
63 #define NEED_DEAR 0x00000002 /* save faulting DEAR */
64 #define NEED_ESR 0x00000004 /* save faulting ESR */
68 * r4 = vcpu, r5 = srr0, r6 = srr1
69 * saved in vcpu: cr, ctr, r3-r13
71 .macro kvm_handler_common intno, srr0, flags
72 /* Restore host stack pointer */
73 PPC_STL r1, VCPU_GPR(R1)(r4)
74 PPC_STL r2, VCPU_GPR(R2)(r4)
75 PPC_LL r1, VCPU_HOST_STACK(r4)
76 PPC_LL r2, HOST_R2(r1)
79 lwz r8, VCPU_HOST_PID(r4)
80 PPC_LL r11, VCPU_SHARED(r4)
81 PPC_STL r14, VCPU_GPR(R14)(r4) /* We need a non-volatile GPR. */
84 stw r10, VCPU_GUEST_PID(r4)
87 #ifdef CONFIG_KVM_EXIT_TIMING
89 1: mfspr r7, SPRN_TBRU
93 stw r8, VCPU_TIMING_EXIT_TBL(r4)
95 stw r9, VCPU_TIMING_EXIT_TBU(r4)
99 PPC_STD(r6, VCPU_SHARED_MSR, r11)
100 ori r8, r8, MSR_ME | MSR_RI
101 PPC_STL r5, VCPU_PC(r4)
104 * Make sure CE/ME/RI are set (if appropriate for exception type)
105 * whether or not the guest had it set. Since mfmsr/mtmsr are
106 * somewhat expensive, skip in the common case where the guest
107 * had all these bits set (and thus they're still set if
108 * appropriate for the exception type).
113 .if \srr0 != SPRN_MCSRR0 && \srr0 != SPRN_CSRR0
114 oris r7, r7, MSR_CE@h
116 .if \srr0 != SPRN_MCSRR0
117 ori r7, r7, MSR_ME | MSR_RI
122 .if \flags & NEED_EMU
123 PPC_STL r15, VCPU_GPR(R15)(r4)
124 PPC_STL r16, VCPU_GPR(R16)(r4)
125 PPC_STL r17, VCPU_GPR(R17)(r4)
126 PPC_STL r18, VCPU_GPR(R18)(r4)
127 PPC_STL r19, VCPU_GPR(R19)(r4)
128 PPC_STL r20, VCPU_GPR(R20)(r4)
129 PPC_STL r21, VCPU_GPR(R21)(r4)
130 PPC_STL r22, VCPU_GPR(R22)(r4)
131 PPC_STL r23, VCPU_GPR(R23)(r4)
132 PPC_STL r24, VCPU_GPR(R24)(r4)
133 PPC_STL r25, VCPU_GPR(R25)(r4)
134 PPC_STL r26, VCPU_GPR(R26)(r4)
135 PPC_STL r27, VCPU_GPR(R27)(r4)
136 PPC_STL r28, VCPU_GPR(R28)(r4)
137 PPC_STL r29, VCPU_GPR(R29)(r4)
138 PPC_STL r30, VCPU_GPR(R30)(r4)
139 PPC_STL r31, VCPU_GPR(R31)(r4)
142 * We don't use external PID support. lwepx faults would need to be
143 * handled by KVM and this implies aditional code in DO_KVM (for
144 * DTB_MISS, DSI and LRAT) to check ESR[EPID] and EPLC[EGS] which
145 * is too intrusive for the host. Get last instuction in
146 * kvmppc_get_last_inst().
148 li r9, KVM_INST_FETCH_FAILED
149 stw r9, VCPU_LAST_INST(r4)
152 .if \flags & NEED_ESR
154 PPC_STL r8, VCPU_FAULT_ESR(r4)
157 .if \flags & NEED_DEAR
159 PPC_STL r9, VCPU_FAULT_DEAR(r4)
166 /* Exception types */
175 * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
177 .macro kvm_handler intno type scratch, paca_ex, ex_r10, ex_r11, srr0, srr1, flags
178 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
181 * Get vcpu from Paca: paca->__current.thread->kvm_vcpu
183 PPC_LL r4, PACACURRENT(r13)
184 PPC_LL r4, (THREAD + THREAD_KVM_VCPU)(r4)
186 PPC_STL r11, VCPU_GPR(R4)(r4)
187 PPC_STL r5, VCPU_GPR(R5)(r4)
188 PPC_STL r6, VCPU_GPR(R6)(r4)
189 PPC_STL r8, VCPU_GPR(R8)(r4)
190 PPC_STL r9, VCPU_GPR(R9)(r4)
192 PPC_LL r5, EX_TLB_R13(r12)
193 PPC_LL r6, EX_TLB_R10(r12)
194 PPC_LL r8, EX_TLB_R11(r12)
198 PPC_LL r6, (\paca_ex + \ex_r10)(r13)
199 PPC_LL r8, (\paca_ex + \ex_r11)(r13)
201 PPC_STL r5, VCPU_GPR(R13)(r4)
202 PPC_STL r3, VCPU_GPR(R3)(r4)
203 PPC_STL r7, VCPU_GPR(R7)(r4)
204 PPC_STL r12, VCPU_GPR(R12)(r4)
205 PPC_STL r6, VCPU_GPR(R10)(r4)
206 PPC_STL r8, VCPU_GPR(R11)(r4)
208 PPC_STL r5, VCPU_CTR(r4)
211 kvm_handler_common \intno, \srr0, \flags
214 #define EX_PARAMS(type) \
216 SPRN_SPRG_##type##_SCRATCH, \
221 #define EX_PARAMS_TLB \
223 SPRN_SPRG_GEN_SCRATCH, \
228 kvm_handler BOOKE_INTERRUPT_CRITICAL, EX_PARAMS(CRIT), \
229 SPRN_CSRR0, SPRN_CSRR1, 0
230 kvm_handler BOOKE_INTERRUPT_MACHINE_CHECK, EX_PARAMS(MC), \
231 SPRN_MCSRR0, SPRN_MCSRR1, 0
232 kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, EX_PARAMS(GEN), \
233 SPRN_SRR0, SPRN_SRR1,(NEED_EMU | NEED_DEAR | NEED_ESR)
234 kvm_handler BOOKE_INTERRUPT_INST_STORAGE, EX_PARAMS(GEN), \
235 SPRN_SRR0, SPRN_SRR1, NEED_ESR
236 kvm_handler BOOKE_INTERRUPT_EXTERNAL, EX_PARAMS(GEN), \
237 SPRN_SRR0, SPRN_SRR1, 0
238 kvm_handler BOOKE_INTERRUPT_ALIGNMENT, EX_PARAMS(GEN), \
239 SPRN_SRR0, SPRN_SRR1,(NEED_DEAR | NEED_ESR)
240 kvm_handler BOOKE_INTERRUPT_PROGRAM, EX_PARAMS(GEN), \
241 SPRN_SRR0, SPRN_SRR1,NEED_ESR
242 kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, EX_PARAMS(GEN), \
243 SPRN_SRR0, SPRN_SRR1, 0
244 kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, EX_PARAMS(GEN), \
245 SPRN_SRR0, SPRN_SRR1, 0
246 kvm_handler BOOKE_INTERRUPT_DECREMENTER, EX_PARAMS(GEN), \
247 SPRN_SRR0, SPRN_SRR1, 0
248 kvm_handler BOOKE_INTERRUPT_FIT, EX_PARAMS(GEN), \
249 SPRN_SRR0, SPRN_SRR1, 0
250 kvm_handler BOOKE_INTERRUPT_WATCHDOG, EX_PARAMS(CRIT),\
251 SPRN_CSRR0, SPRN_CSRR1, 0
253 * Only bolted TLB miss exception handlers are supported for now
255 kvm_handler BOOKE_INTERRUPT_DTLB_MISS, EX_PARAMS_TLB, \
256 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
257 kvm_handler BOOKE_INTERRUPT_ITLB_MISS, EX_PARAMS_TLB, \
258 SPRN_SRR0, SPRN_SRR1, 0
259 kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, EX_PARAMS(GEN), \
260 SPRN_SRR0, SPRN_SRR1, 0
261 kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, EX_PARAMS(GEN), \
262 SPRN_SRR0, SPRN_SRR1, 0
263 kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, EX_PARAMS(GEN), \
264 SPRN_SRR0, SPRN_SRR1, 0
265 kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, EX_PARAMS(GEN), \
266 SPRN_SRR0, SPRN_SRR1, 0
267 kvm_handler BOOKE_INTERRUPT_DOORBELL, EX_PARAMS(GEN), \
268 SPRN_SRR0, SPRN_SRR1, 0
269 kvm_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, EX_PARAMS(CRIT), \
270 SPRN_CSRR0, SPRN_CSRR1, 0
271 kvm_handler BOOKE_INTERRUPT_HV_PRIV, EX_PARAMS(GEN), \
272 SPRN_SRR0, SPRN_SRR1, NEED_EMU
273 kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, EX_PARAMS(GEN), \
274 SPRN_SRR0, SPRN_SRR1, 0
275 kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, EX_PARAMS(GDBELL), \
276 SPRN_GSRR0, SPRN_GSRR1, 0
277 kvm_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, EX_PARAMS(CRIT), \
278 SPRN_CSRR0, SPRN_CSRR1, 0
279 kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(DBG), \
280 SPRN_DSRR0, SPRN_DSRR1, 0
281 kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(CRIT), \
282 SPRN_CSRR0, SPRN_CSRR1, 0
283 kvm_handler BOOKE_INTERRUPT_LRAT_ERROR, EX_PARAMS(GEN), \
284 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
287 * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
289 .macro kvm_handler intno srr0, srr1, flags
290 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
291 PPC_LL r11, THREAD_KVM_VCPU(r10)
292 PPC_STL r3, VCPU_GPR(R3)(r11)
293 mfspr r3, SPRN_SPRG_RSCRATCH0
294 PPC_STL r4, VCPU_GPR(R4)(r11)
295 PPC_LL r4, THREAD_NORMSAVE(0)(r10)
296 PPC_STL r5, VCPU_GPR(R5)(r11)
297 stw r13, VCPU_CR(r11)
299 PPC_STL r3, VCPU_GPR(R10)(r11)
300 PPC_LL r3, THREAD_NORMSAVE(2)(r10)
301 PPC_STL r6, VCPU_GPR(R6)(r11)
302 PPC_STL r4, VCPU_GPR(R11)(r11)
304 PPC_STL r7, VCPU_GPR(R7)(r11)
305 PPC_STL r8, VCPU_GPR(R8)(r11)
306 PPC_STL r9, VCPU_GPR(R9)(r11)
307 PPC_STL r3, VCPU_GPR(R13)(r11)
309 PPC_STL r12, VCPU_GPR(R12)(r11)
310 PPC_STL r7, VCPU_CTR(r11)
312 kvm_handler_common \intno, \srr0, \flags
315 .macro kvm_lvl_handler intno scratch srr0, srr1, flags
316 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
317 mfspr r10, SPRN_SPRG_THREAD
318 PPC_LL r11, THREAD_KVM_VCPU(r10)
319 PPC_STL r3, VCPU_GPR(R3)(r11)
321 PPC_STL r4, VCPU_GPR(R4)(r11)
323 PPC_STL r5, VCPU_GPR(R5)(r11)
326 PPC_STL r3, VCPU_GPR(R8)(r11)
328 PPC_STL r6, VCPU_GPR(R6)(r11)
329 PPC_STL r4, VCPU_GPR(R9)(r11)
332 PPC_STL r7, VCPU_GPR(R7)(r11)
333 PPC_STL r3, VCPU_GPR(R10)(r11)
335 PPC_STL r12, VCPU_GPR(R12)(r11)
336 PPC_STL r13, VCPU_GPR(R13)(r11)
337 PPC_STL r4, VCPU_GPR(R11)(r11)
338 PPC_STL r7, VCPU_CTR(r11)
340 kvm_handler_common \intno, \srr0, \flags
343 kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \
344 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
345 kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \
346 SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0
347 kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \
348 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
349 kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR
350 kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0
351 kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \
352 SPRN_SRR0, SPRN_SRR1, (NEED_DEAR | NEED_ESR)
353 kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, NEED_ESR
354 kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
355 kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
356 kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
357 kvm_handler BOOKE_INTERRUPT_DECREMENTER, SPRN_SRR0, SPRN_SRR1, 0
358 kvm_handler BOOKE_INTERRUPT_FIT, SPRN_SRR0, SPRN_SRR1, 0
359 kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \
360 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
361 kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \
362 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
363 kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0
364 kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
365 kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, SPRN_SRR0, SPRN_SRR1, 0
366 kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, SPRN_SRR0, SPRN_SRR1, 0
367 kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, SPRN_SRR1, 0
368 kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0
369 kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \
370 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
371 kvm_handler BOOKE_INTERRUPT_HV_PRIV, SPRN_SRR0, SPRN_SRR1, NEED_EMU
372 kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
373 kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, SPRN_GSRR0, SPRN_GSRR1, 0
374 kvm_lvl_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, \
375 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
376 kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
377 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
378 kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
379 SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0
383 * SPRG_SCRATCH0: guest r10
385 * r11: vcpu->arch.shared
386 * r14: KVM exit number
388 _GLOBAL(kvmppc_resume_host)
389 /* Save remaining volatile guest register state to vcpu. */
390 mfspr r3, SPRN_VRSAVE
391 PPC_STL r0, VCPU_GPR(R0)(r4)
394 PPC_STL r5, VCPU_LR(r4)
396 stw r3, VCPU_VRSAVE(r4)
398 PPC_LL r3, PACA_SPRG_VDSO(r13)
401 PPC_STD(r6, VCPU_SHARED_SPRG4, r11)
403 PPC_STD(r7, VCPU_SHARED_SPRG5, r11)
406 mtspr SPRN_SPRG_VDSO_WRITE, r3
408 PPC_STD(r5, VCPU_SPRG9, r4)
409 PPC_STD(r8, VCPU_SHARED_SPRG6, r11)
411 PPC_STD(r9, VCPU_SHARED_SPRG7, r11)
413 /* save guest MAS registers and restore host mas4 & mas6 */
415 PPC_STL r3, VCPU_XER(r4)
417 stw r5, VCPU_SHARED_MAS0(r11)
419 stw r6, VCPU_SHARED_MAS1(r11)
420 PPC_STD(r7, VCPU_SHARED_MAS2, r11)
423 stw r5, VCPU_SHARED_MAS7_3+4(r11)
425 stw r6, VCPU_SHARED_MAS4(r11)
427 lwz r6, VCPU_HOST_MAS4(r4)
428 stw r7, VCPU_SHARED_MAS6(r11)
429 lwz r8, VCPU_HOST_MAS6(r4)
431 stw r5, VCPU_SHARED_MAS7_3+0(r11)
433 /* Enable MAS register updates via exception */
435 rlwinm r3, r3, 0, ~SPRN_EPCR_DMIUH
441 * We enter with interrupts disabled in hardware, but
442 * we need to call RECONCILE_IRQ_STATE to ensure
443 * that the software state is kept in sync.
445 RECONCILE_IRQ_STATE(r3,r5)
448 /* Switch to kernel stack and jump to handler. */
449 PPC_LL r3, HOST_RUN(r1)
450 mr r5, r14 /* intno */
451 mr r14, r4 /* Save vcpu pointer. */
452 bl kvmppc_handle_exit
454 /* Restore vcpu pointer and the nonvolatiles we used. */
456 PPC_LL r14, VCPU_GPR(R14)(r4)
458 andi. r5, r3, RESUME_FLAG_NV
460 PPC_LL r15, VCPU_GPR(R15)(r4)
461 PPC_LL r16, VCPU_GPR(R16)(r4)
462 PPC_LL r17, VCPU_GPR(R17)(r4)
463 PPC_LL r18, VCPU_GPR(R18)(r4)
464 PPC_LL r19, VCPU_GPR(R19)(r4)
465 PPC_LL r20, VCPU_GPR(R20)(r4)
466 PPC_LL r21, VCPU_GPR(R21)(r4)
467 PPC_LL r22, VCPU_GPR(R22)(r4)
468 PPC_LL r23, VCPU_GPR(R23)(r4)
469 PPC_LL r24, VCPU_GPR(R24)(r4)
470 PPC_LL r25, VCPU_GPR(R25)(r4)
471 PPC_LL r26, VCPU_GPR(R26)(r4)
472 PPC_LL r27, VCPU_GPR(R27)(r4)
473 PPC_LL r28, VCPU_GPR(R28)(r4)
474 PPC_LL r29, VCPU_GPR(R29)(r4)
475 PPC_LL r30, VCPU_GPR(R30)(r4)
476 PPC_LL r31, VCPU_GPR(R31)(r4)
478 /* Should we return to the guest? */
479 andi. r5, r3, RESUME_FLAG_HOST
482 srawi r3, r3, 2 /* Shift -ERR back down. */
485 /* Not returning to guest. */
486 PPC_LL r5, HOST_STACK_LR(r1)
490 * We already saved guest volatile register state; now save the
494 PPC_STL r15, VCPU_GPR(R15)(r4)
495 PPC_STL r16, VCPU_GPR(R16)(r4)
496 PPC_STL r17, VCPU_GPR(R17)(r4)
497 PPC_STL r18, VCPU_GPR(R18)(r4)
498 PPC_STL r19, VCPU_GPR(R19)(r4)
499 PPC_STL r20, VCPU_GPR(R20)(r4)
500 PPC_STL r21, VCPU_GPR(R21)(r4)
501 PPC_STL r22, VCPU_GPR(R22)(r4)
502 PPC_STL r23, VCPU_GPR(R23)(r4)
503 PPC_STL r24, VCPU_GPR(R24)(r4)
504 PPC_STL r25, VCPU_GPR(R25)(r4)
505 PPC_STL r26, VCPU_GPR(R26)(r4)
506 PPC_STL r27, VCPU_GPR(R27)(r4)
507 PPC_STL r28, VCPU_GPR(R28)(r4)
508 PPC_STL r29, VCPU_GPR(R29)(r4)
509 PPC_STL r30, VCPU_GPR(R30)(r4)
510 PPC_STL r31, VCPU_GPR(R31)(r4)
512 /* Load host non-volatile register state from host stack. */
513 PPC_LL r14, HOST_NV_GPR(R14)(r1)
514 PPC_LL r15, HOST_NV_GPR(R15)(r1)
515 PPC_LL r16, HOST_NV_GPR(R16)(r1)
516 PPC_LL r17, HOST_NV_GPR(R17)(r1)
517 PPC_LL r18, HOST_NV_GPR(R18)(r1)
518 PPC_LL r19, HOST_NV_GPR(R19)(r1)
519 PPC_LL r20, HOST_NV_GPR(R20)(r1)
520 PPC_LL r21, HOST_NV_GPR(R21)(r1)
521 PPC_LL r22, HOST_NV_GPR(R22)(r1)
522 PPC_LL r23, HOST_NV_GPR(R23)(r1)
523 PPC_LL r24, HOST_NV_GPR(R24)(r1)
524 PPC_LL r25, HOST_NV_GPR(R25)(r1)
525 PPC_LL r26, HOST_NV_GPR(R26)(r1)
526 PPC_LL r27, HOST_NV_GPR(R27)(r1)
527 PPC_LL r28, HOST_NV_GPR(R28)(r1)
528 PPC_LL r29, HOST_NV_GPR(R29)(r1)
529 PPC_LL r30, HOST_NV_GPR(R30)(r1)
530 PPC_LL r31, HOST_NV_GPR(R31)(r1)
532 /* Return to kvm_vcpu_run(). */
535 addi r1, r1, HOST_STACK_SIZE
536 /* r3 still contains the return code from kvmppc_handle_exit(). */
540 * r3: kvm_run pointer
543 _GLOBAL(__kvmppc_vcpu_run)
544 stwu r1, -HOST_STACK_SIZE(r1)
545 PPC_STL r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */
547 /* Save host state to stack. */
548 PPC_STL r3, HOST_RUN(r1)
551 PPC_STL r3, HOST_STACK_LR(r1)
555 /* Save host non-volatile register state to stack. */
556 PPC_STL r14, HOST_NV_GPR(R14)(r1)
557 PPC_STL r15, HOST_NV_GPR(R15)(r1)
558 PPC_STL r16, HOST_NV_GPR(R16)(r1)
559 PPC_STL r17, HOST_NV_GPR(R17)(r1)
560 PPC_STL r18, HOST_NV_GPR(R18)(r1)
561 PPC_STL r19, HOST_NV_GPR(R19)(r1)
562 PPC_STL r20, HOST_NV_GPR(R20)(r1)
563 PPC_STL r21, HOST_NV_GPR(R21)(r1)
564 PPC_STL r22, HOST_NV_GPR(R22)(r1)
565 PPC_STL r23, HOST_NV_GPR(R23)(r1)
566 PPC_STL r24, HOST_NV_GPR(R24)(r1)
567 PPC_STL r25, HOST_NV_GPR(R25)(r1)
568 PPC_STL r26, HOST_NV_GPR(R26)(r1)
569 PPC_STL r27, HOST_NV_GPR(R27)(r1)
570 PPC_STL r28, HOST_NV_GPR(R28)(r1)
571 PPC_STL r29, HOST_NV_GPR(R29)(r1)
572 PPC_STL r30, HOST_NV_GPR(R30)(r1)
573 PPC_STL r31, HOST_NV_GPR(R31)(r1)
575 /* Load guest non-volatiles. */
576 PPC_LL r14, VCPU_GPR(R14)(r4)
577 PPC_LL r15, VCPU_GPR(R15)(r4)
578 PPC_LL r16, VCPU_GPR(R16)(r4)
579 PPC_LL r17, VCPU_GPR(R17)(r4)
580 PPC_LL r18, VCPU_GPR(R18)(r4)
581 PPC_LL r19, VCPU_GPR(R19)(r4)
582 PPC_LL r20, VCPU_GPR(R20)(r4)
583 PPC_LL r21, VCPU_GPR(R21)(r4)
584 PPC_LL r22, VCPU_GPR(R22)(r4)
585 PPC_LL r23, VCPU_GPR(R23)(r4)
586 PPC_LL r24, VCPU_GPR(R24)(r4)
587 PPC_LL r25, VCPU_GPR(R25)(r4)
588 PPC_LL r26, VCPU_GPR(R26)(r4)
589 PPC_LL r27, VCPU_GPR(R27)(r4)
590 PPC_LL r28, VCPU_GPR(R28)(r4)
591 PPC_LL r29, VCPU_GPR(R29)(r4)
592 PPC_LL r30, VCPU_GPR(R30)(r4)
593 PPC_LL r31, VCPU_GPR(R31)(r4)
597 PPC_STL r2, HOST_R2(r1)
600 stw r3, VCPU_HOST_PID(r4)
601 lwz r3, VCPU_GUEST_PID(r4)
604 PPC_LL r11, VCPU_SHARED(r4)
605 /* Disable MAS register updates via exception */
607 oris r3, r3, SPRN_EPCR_DMIUH@h
610 /* Save host mas4 and mas6 and load guest MAS registers */
612 stw r3, VCPU_HOST_MAS4(r4)
614 stw r3, VCPU_HOST_MAS6(r4)
615 lwz r3, VCPU_SHARED_MAS0(r11)
616 lwz r5, VCPU_SHARED_MAS1(r11)
617 PPC_LD(r6, VCPU_SHARED_MAS2, r11)
618 lwz r7, VCPU_SHARED_MAS7_3+4(r11)
619 lwz r8, VCPU_SHARED_MAS4(r11)
625 lwz r3, VCPU_SHARED_MAS6(r11)
626 lwz r5, VCPU_SHARED_MAS7_3+0(r11)
631 * Host interrupt handlers may have clobbered these guest-readable
632 * SPRGs, so we need to reload them here with the guest's values.
634 lwz r3, VCPU_VRSAVE(r4)
635 PPC_LD(r5, VCPU_SHARED_SPRG4, r11)
636 mtspr SPRN_VRSAVE, r3
637 PPC_LD(r6, VCPU_SHARED_SPRG5, r11)
638 mtspr SPRN_SPRG4W, r5
639 PPC_LD(r7, VCPU_SHARED_SPRG6, r11)
640 mtspr SPRN_SPRG5W, r6
641 PPC_LD(r8, VCPU_SHARED_SPRG7, r11)
642 mtspr SPRN_SPRG6W, r7
643 PPC_LD(r5, VCPU_SPRG9, r4)
644 mtspr SPRN_SPRG7W, r8
647 /* Load some guest volatiles. */
648 PPC_LL r3, VCPU_LR(r4)
649 PPC_LL r5, VCPU_XER(r4)
650 PPC_LL r6, VCPU_CTR(r4)
652 PPC_LL r8, VCPU_PC(r4)
653 PPC_LD(r9, VCPU_SHARED_MSR, r11)
654 PPC_LL r0, VCPU_GPR(R0)(r4)
655 PPC_LL r1, VCPU_GPR(R1)(r4)
656 PPC_LL r2, VCPU_GPR(R2)(r4)
657 PPC_LL r10, VCPU_GPR(R10)(r4)
658 PPC_LL r11, VCPU_GPR(R11)(r4)
659 PPC_LL r12, VCPU_GPR(R12)(r4)
660 PPC_LL r13, VCPU_GPR(R13)(r4)
667 #ifdef CONFIG_KVM_EXIT_TIMING
668 /* save enter time */
674 stw r9, VCPU_TIMING_LAST_ENTER_TBL(r4)
676 stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
680 * Don't execute any instruction which can change CR after
685 /* Finish loading guest volatiles and jump to guest. */
686 PPC_LL r5, VCPU_GPR(R5)(r4)
687 PPC_LL r6, VCPU_GPR(R6)(r4)
688 PPC_LL r7, VCPU_GPR(R7)(r4)
689 PPC_LL r8, VCPU_GPR(R8)(r4)
690 PPC_LL r9, VCPU_GPR(R9)(r4)
692 PPC_LL r3, VCPU_GPR(R3)(r4)
693 PPC_LL r4, VCPU_GPR(R4)(r4)