2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
33 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
35 /* Values in HSTATE_NAPPING(r13) */
36 #define NAPPING_CEDE 1
37 #define NAPPING_NOVCPU 2
40 * Call kvmppc_hv_entry in real mode.
41 * Must be called with interrupts hard-disabled.
45 * LR = return address to continue at after eventually re-enabling MMU
47 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
49 std r0, PPC_LR_STKOFF(r1)
52 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
57 mtmsrd r0,1 /* clear RI in MSR */
63 ld r4, HSTATE_KVM_VCPU(r13)
66 /* Back from guest - restore host state and return to caller */
69 /* Restore host DABR and DABRX */
70 ld r5,HSTATE_DABR(r13)
74 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
77 ld r3,PACA_SPRG_VDSO(r13)
78 mtspr SPRN_SPRG_VDSO_WRITE,r3
80 /* Reload the host's PMU registers */
81 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
82 lbz r4, LPPACA_PMCINUSE(r3)
84 beq 23f /* skip if not */
86 ld r3, HSTATE_MMCR0(r13)
87 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
90 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
91 lwz r3, HSTATE_PMC1(r13)
92 lwz r4, HSTATE_PMC2(r13)
93 lwz r5, HSTATE_PMC3(r13)
94 lwz r6, HSTATE_PMC4(r13)
95 lwz r8, HSTATE_PMC5(r13)
96 lwz r9, HSTATE_PMC6(r13)
103 ld r3, HSTATE_MMCR0(r13)
104 ld r4, HSTATE_MMCR1(r13)
105 ld r5, HSTATE_MMCRA(r13)
106 ld r6, HSTATE_SIAR(r13)
107 ld r7, HSTATE_SDAR(r13)
113 ld r8, HSTATE_MMCR2(r13)
114 ld r9, HSTATE_SIER(r13)
117 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
123 * Reload DEC. HDEC interrupts were disabled when
124 * we reloaded the host's LPCR value.
126 ld r3, HSTATE_DECEXP(r13)
132 * For external and machine check interrupts, we need
133 * to call the Linux handler to process the interrupt.
134 * We do that by jumping to absolute address 0x500 for
135 * external interrupts, or the machine_check_fwnmi label
136 * for machine checks (since firmware might have patched
137 * the vector area at 0x200). The [h]rfid at the end of the
138 * handler will return to the book3s_hv_interrupts.S code.
139 * For other interrupts we do the rfid to get back
140 * to the book3s_hv_interrupts.S code here.
142 ld r8, 112+PPC_LR_STKOFF(r1)
144 ld r7, HSTATE_HOST_MSR(r13)
146 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
147 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
149 cmpwi cr2, r12, BOOK3S_INTERRUPT_HMI
150 beq cr2, 14f /* HMI check */
152 /* RFI into the highmem handler, or branch to interrupt handler */
156 mtmsrd r6, 1 /* Clear RI in MSR */
159 beq cr1, 13f /* machine check */
162 /* On POWER7, we have external interrupts set to use HSRR0/1 */
163 11: mtspr SPRN_HSRR0, r8
167 13: b machine_check_fwnmi
169 14: mtspr SPRN_HSRR0, r8
171 b hmi_exception_after_realmode
173 kvmppc_primary_no_guest:
174 /* We handle this much like a ceded vcpu */
175 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
179 * Make sure the primary has finished the MMU switch.
180 * We should never get here on a secondary thread, but
181 * check it for robustness' sake.
183 ld r5, HSTATE_KVM_VCORE(r13)
184 65: lbz r0, VCORE_IN_GUEST(r5)
191 /* set our bit in napping_threads */
192 ld r5, HSTATE_KVM_VCORE(r13)
193 lbz r7, HSTATE_PTID(r13)
196 addi r6, r5, VCORE_NAPPING_THREADS
201 /* order napping_threads update vs testing entry_exit_map */
204 lwz r7, VCORE_ENTRY_EXIT(r5)
206 bge kvm_novcpu_exit /* another thread already exiting */
207 li r3, NAPPING_NOVCPU
208 stb r3, HSTATE_NAPPING(r13)
210 li r3, 0 /* Don't wake on privileged (OS) doorbell */
214 ld r1, HSTATE_HOST_R1(r13)
215 ld r5, HSTATE_KVM_VCORE(r13)
217 stb r0, HSTATE_NAPPING(r13)
218 stb r0, HSTATE_HWTHREAD_REQ(r13)
220 /* check the wake reason */
221 bl kvmppc_check_wake_reason
223 /* see if any other thread is already exiting */
224 lwz r0, VCORE_ENTRY_EXIT(r5)
228 /* clear our bit in napping_threads */
229 lbz r7, HSTATE_PTID(r13)
232 addi r6, r5, VCORE_NAPPING_THREADS
238 /* See if the wake reason means we need to exit */
242 /* See if our timeslice has expired (HDEC is negative) */
244 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
248 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
249 ld r4, HSTATE_KVM_VCPU(r13)
251 beq kvmppc_primary_no_guest
253 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
254 addi r3, r4, VCPU_TB_RMENTRY
255 bl kvmhv_start_timing
260 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
261 ld r4, HSTATE_KVM_VCPU(r13)
264 addi r3, r4, VCPU_TB_RMEXIT
265 bl kvmhv_accumulate_time
269 bl kvmhv_commence_exit
272 b kvmhv_switch_to_host
275 * We come in here when wakened from nap mode.
276 * Relocation is off and most register values are lost.
277 * r13 points to the PACA.
279 .globl kvm_start_guest
282 /* Set runlatch bit the minute you wake up from nap */
289 li r0,KVM_HWTHREAD_IN_KVM
290 stb r0,HSTATE_HWTHREAD_STATE(r13)
292 /* NV GPR values from power7_idle() will no longer be valid */
294 stb r0,PACA_NAPSTATELOST(r13)
296 /* were we napping due to cede? */
297 lbz r0,HSTATE_NAPPING(r13)
298 cmpwi r0,NAPPING_CEDE
300 cmpwi r0,NAPPING_NOVCPU
301 beq kvm_novcpu_wakeup
303 ld r1,PACAEMERGSP(r13)
304 subi r1,r1,STACK_FRAME_OVERHEAD
307 * We weren't napping due to cede, so this must be a secondary
308 * thread being woken up to run a guest, or being woken up due
309 * to a stray IPI. (Or due to some machine check or hypervisor
310 * maintenance interrupt while the core is in KVM.)
313 /* Check the wake reason in SRR1 to see why we got here */
314 bl kvmppc_check_wake_reason
318 /* get vcpu pointer, NULL if we have no vcpu to run */
319 ld r4,HSTATE_KVM_VCPU(r13)
321 /* if we have no vcpu to run, go back to sleep */
324 kvm_secondary_got_guest:
326 /* Set HSTATE_DSCR(r13) to something sensible */
327 ld r6, PACA_DSCR_DEFAULT(r13)
328 std r6, HSTATE_DSCR(r13)
330 /* Order load of vcore, ptid etc. after load of vcpu */
334 /* Back from the guest, go back to nap */
335 /* Clear our vcpu pointer so we don't come back in early */
338 * Once we clear HSTATE_KVM_VCPU(r13), the code in
339 * kvmppc_run_core() is going to assume that all our vcpu
340 * state is visible in memory. This lwsync makes sure
344 std r0, HSTATE_KVM_VCPU(r13)
347 * At this point we have finished executing in the guest.
348 * We need to wait for hwthread_req to become zero, since
349 * we may not turn on the MMU while hwthread_req is non-zero.
350 * While waiting we also need to check if we get given a vcpu to run.
353 lbz r3, HSTATE_HWTHREAD_REQ(r13)
357 li r0, KVM_HWTHREAD_IN_KERNEL
358 stb r0, HSTATE_HWTHREAD_STATE(r13)
359 /* need to recheck hwthread_req after a barrier, to avoid race */
361 lbz r3, HSTATE_HWTHREAD_REQ(r13)
365 * We jump to power7_wakeup_loss, which will return to the caller
366 * of power7_nap in the powernv cpu offline loop. The value we
367 * put in r3 becomes the return value for power7_nap.
371 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
377 ld r4, HSTATE_KVM_VCPU(r13)
381 b kvm_secondary_got_guest
383 54: li r0, KVM_HWTHREAD_IN_KVM
384 stb r0, HSTATE_HWTHREAD_STATE(r13)
387 /******************************************************************************
391 *****************************************************************************/
393 .global kvmppc_hv_entry
398 * R4 = vcpu pointer (or NULL)
403 * all other volatile GPRS = free
406 std r0, PPC_LR_STKOFF(r1)
409 /* Save R1 in the PACA */
410 std r1, HSTATE_HOST_R1(r13)
412 li r6, KVM_GUEST_MODE_HOST_HV
413 stb r6, HSTATE_IN_GUEST(r13)
415 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
416 /* Store initial timestamp */
419 addi r3, r4, VCPU_TB_RMENTRY
420 bl kvmhv_start_timing
430 * POWER7/POWER8 host -> guest partition switch code.
431 * We don't have to lock against concurrent tlbies,
432 * but we do have to coordinate across hardware threads.
434 /* Set bit in entry map iff exit map is zero. */
435 ld r5, HSTATE_KVM_VCORE(r13)
437 lbz r6, HSTATE_PTID(r13)
439 addi r9, r5, VCORE_ENTRY_EXIT
441 cmpwi r3, 0x100 /* any threads starting to exit? */
442 bge secondary_too_late /* if so we're too late to the party */
447 /* Primary thread switches to guest partition. */
448 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
453 li r0,LPID_RSVD /* switch to reserved LPID */
456 mtspr SPRN_SDR1,r6 /* switch to partition page table */
460 /* See if we need to flush the TLB */
461 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
462 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
463 srdi r6,r6,6 /* doubleword number */
464 sldi r6,r6,3 /* address offset */
466 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
472 23: ldarx r7,0,r6 /* if set, clear the bit */
476 /* Flush the TLB of any entries for this LPID */
477 /* use arch 2.07S as a proxy for POWER8 */
479 li r6,512 /* POWER8 has 512 sets */
481 li r6,128 /* POWER7 has 128 sets */
482 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
484 li r7,0x800 /* IS field = 0b10 */
491 /* Add timebase offset onto timebase */
492 22: ld r8,VCORE_TB_OFFSET(r5)
495 mftb r6 /* current host timebase */
497 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
498 mftb r7 /* check if lower 24 bits overflowed */
503 addis r8,r8,0x100 /* if so, increment upper 40 bits */
506 /* Load guest PCR value to select appropriate compat mode */
507 37: ld r7, VCORE_PCR(r5)
514 /* DPDES is shared between threads */
515 ld r8, VCORE_DPDES(r5)
517 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
520 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
522 /* Do we have a guest vcpu to run? */
524 beq kvmppc_primary_no_guest
527 /* Load up guest SLB entries */
528 lwz r5,VCPU_SLB_MAX(r4)
533 1: ld r8,VCPU_SLB_E(r6)
536 addi r6,r6,VCPU_SLB_SIZE
539 /* Increment yield count if they have a VPA */
543 li r6, LPPACA_YIELDCOUNT
548 stb r6, VCPU_VPA_DIRTY(r4)
551 /* Save purr/spurr */
554 std r5,HSTATE_PURR(r13)
555 std r6,HSTATE_SPURR(r13)
562 /* Set partition DABR */
563 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
564 lwz r5,VCPU_DABRX(r4)
569 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
571 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
574 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
576 /* Turn on TM/FP/VSX/VMX so we can restore them. */
582 oris r5, r5, (MSR_VEC | MSR_VSX)@h
586 * The user may change these outside of a transaction, so they must
587 * always be context switched.
589 ld r5, VCPU_TFHAR(r4)
590 ld r6, VCPU_TFIAR(r4)
591 ld r7, VCPU_TEXASR(r4)
594 mtspr SPRN_TEXASR, r7
597 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
598 beq skip_tm /* TM not active in guest */
600 /* Make sure the failure summary is set, otherwise we'll program check
601 * when we trechkpt. It's possible that this might have been not set
602 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
605 oris r7, r7, (TEXASR_FS)@h
606 mtspr SPRN_TEXASR, r7
609 * We need to load up the checkpointed state for the guest.
610 * We need to do this early as it will blow away any GPRs, VSRs and
615 addi r3, r31, VCPU_FPRS_TM
617 addi r3, r31, VCPU_VRS_TM
620 lwz r7, VCPU_VRSAVE_TM(r4)
621 mtspr SPRN_VRSAVE, r7
623 ld r5, VCPU_LR_TM(r4)
624 lwz r6, VCPU_CR_TM(r4)
625 ld r7, VCPU_CTR_TM(r4)
626 ld r8, VCPU_AMR_TM(r4)
627 ld r9, VCPU_TAR_TM(r4)
635 * Load up PPR and DSCR values but don't put them in the actual SPRs
636 * till the last moment to avoid running with userspace PPR and DSCR for
639 ld r29, VCPU_DSCR_TM(r4)
640 ld r30, VCPU_PPR_TM(r4)
642 std r2, PACATMSCRATCH(r13) /* Save TOC */
644 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
648 /* Load GPRs r0-r28 */
651 ld reg, VCPU_GPRS_TM(reg)(r31)
658 /* Load final GPRs */
659 ld 29, VCPU_GPRS_TM(29)(r31)
660 ld 30, VCPU_GPRS_TM(30)(r31)
661 ld 31, VCPU_GPRS_TM(31)(r31)
663 /* TM checkpointed state is now setup. All GPRs are now volatile. */
666 /* Now let's get back the state we need. */
669 ld r29, HSTATE_DSCR(r13)
671 ld r4, HSTATE_KVM_VCPU(r13)
672 ld r1, HSTATE_HOST_R1(r13)
673 ld r2, PACATMSCRATCH(r13)
675 /* Set the MSR RI since we have our registers back. */
681 /* Load guest PMU registers */
682 /* R4 is live here (vcpu pointer) */
684 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
685 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
689 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
692 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
693 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
694 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
695 lwz r6, VCPU_PMC + 8(r4)
696 lwz r7, VCPU_PMC + 12(r4)
697 lwz r8, VCPU_PMC + 16(r4)
698 lwz r9, VCPU_PMC + 20(r4)
706 ld r5, VCPU_MMCR + 8(r4)
707 ld r6, VCPU_MMCR + 16(r4)
715 ld r5, VCPU_MMCR + 24(r4)
717 lwz r7, VCPU_PMC + 24(r4)
718 lwz r8, VCPU_PMC + 28(r4)
719 ld r9, VCPU_MMCR + 32(r4)
725 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
729 /* Load up FP, VMX and VSX registers */
732 ld r14, VCPU_GPR(R14)(r4)
733 ld r15, VCPU_GPR(R15)(r4)
734 ld r16, VCPU_GPR(R16)(r4)
735 ld r17, VCPU_GPR(R17)(r4)
736 ld r18, VCPU_GPR(R18)(r4)
737 ld r19, VCPU_GPR(R19)(r4)
738 ld r20, VCPU_GPR(R20)(r4)
739 ld r21, VCPU_GPR(R21)(r4)
740 ld r22, VCPU_GPR(R22)(r4)
741 ld r23, VCPU_GPR(R23)(r4)
742 ld r24, VCPU_GPR(R24)(r4)
743 ld r25, VCPU_GPR(R25)(r4)
744 ld r26, VCPU_GPR(R26)(r4)
745 ld r27, VCPU_GPR(R27)(r4)
746 ld r28, VCPU_GPR(R28)(r4)
747 ld r29, VCPU_GPR(R29)(r4)
748 ld r30, VCPU_GPR(R30)(r4)
749 ld r31, VCPU_GPR(R31)(r4)
751 /* Switch DSCR to guest value */
756 /* Skip next section on POWER7 */
758 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
759 /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
762 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
765 /* Load up POWER8-specific registers */
767 lwz r6, VCPU_PSPB(r4)
773 ld r6, VCPU_DAWRX(r4)
774 ld r7, VCPU_CIABR(r4)
784 ld r8, VCPU_EBBHR(r4)
786 ld r5, VCPU_EBBRR(r4)
787 ld r6, VCPU_BESCR(r4)
788 ld r7, VCPU_CSIGR(r4)
794 ld r5, VCPU_TCSCR(r4)
796 lwz r7, VCPU_GUEST_PID(r4)
805 * Set the decrementer to the guest decrementer.
807 ld r8,VCPU_DEC_EXPIRES(r4)
808 /* r8 is a host timebase value here, convert to guest TB */
809 ld r5,HSTATE_KVM_VCORE(r13)
810 ld r6,VCORE_TB_OFFSET(r5)
817 ld r5, VCPU_SPRG0(r4)
818 ld r6, VCPU_SPRG1(r4)
819 ld r7, VCPU_SPRG2(r4)
820 ld r8, VCPU_SPRG3(r4)
826 /* Load up DAR and DSISR */
828 lwz r6, VCPU_DSISR(r4)
832 /* Restore AMR and UAMOR, set AMOR to all 1s */
840 /* Restore state of CTRL run bit; assume 1 on entry */
848 /* Secondary threads wait for primary to have done partition switch */
849 ld r5, HSTATE_KVM_VCORE(r13)
850 lbz r6, HSTATE_PTID(r13)
853 lbz r0, VCORE_IN_GUEST(r5)
857 20: lbz r0, VCORE_IN_GUEST(r5)
867 /* Check if HDEC expires soon */
869 cmpwi r3, 512 /* 1 microsecond */
878 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
886 deliver_guest_interrupt:
887 /* r11 = vcpu->arch.msr & ~MSR_HV */
888 rldicl r11, r11, 63 - MSR_HV_LG, 1
889 rotldi r11, r11, 1 + MSR_HV_LG
892 /* Check if we can deliver an external or decrementer interrupt now */
893 ld r0, VCPU_PENDING_EXC(r4)
894 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
896 andi. r8, r11, MSR_EE
898 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
899 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
903 li r0, BOOK3S_INTERRUPT_EXTERNAL
907 li r0, BOOK3S_INTERRUPT_DECREMENTER
910 12: mtspr SPRN_SRR0, r10
914 bl kvmppc_msr_interrupt
920 * R10: value for HSRR0
921 * R11: value for HSRR1
926 stb r0,VCPU_CEDED(r4) /* cancel cede */
930 /* Activate guest mode, so faults get handled by KVM */
931 li r9, KVM_GUEST_MODE_GUEST_HV
932 stb r9, HSTATE_IN_GUEST(r13)
934 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
935 /* Accumulate timing */
936 addi r3, r4, VCPU_TB_GUEST
937 bl kvmhv_accumulate_time
945 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
948 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
955 ld r1, VCPU_GPR(R1)(r4)
956 ld r2, VCPU_GPR(R2)(r4)
957 ld r3, VCPU_GPR(R3)(r4)
958 ld r5, VCPU_GPR(R5)(r4)
959 ld r6, VCPU_GPR(R6)(r4)
960 ld r7, VCPU_GPR(R7)(r4)
961 ld r8, VCPU_GPR(R8)(r4)
962 ld r9, VCPU_GPR(R9)(r4)
963 ld r10, VCPU_GPR(R10)(r4)
964 ld r11, VCPU_GPR(R11)(r4)
965 ld r12, VCPU_GPR(R12)(r4)
966 ld r13, VCPU_GPR(R13)(r4)
970 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
971 ld r0, VCPU_GPR(R0)(r4)
972 ld r4, VCPU_GPR(R4)(r4)
981 stw r12, VCPU_TRAP(r4)
982 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
983 addi r3, r4, VCPU_TB_RMEXIT
984 bl kvmhv_accumulate_time
986 11: b kvmhv_switch_to_host
989 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
990 stw r12, VCPU_TRAP(r4)
992 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
993 addi r3, r4, VCPU_TB_RMEXIT
994 bl kvmhv_accumulate_time
998 /******************************************************************************
1002 *****************************************************************************/
1005 * We come here from the first-level interrupt handlers.
1007 .globl kvmppc_interrupt_hv
1008 kvmppc_interrupt_hv:
1010 * Register contents:
1011 * R12 = interrupt vector
1013 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
1014 * guest R13 saved in SPRN_SCRATCH0
1016 std r9, HSTATE_SCRATCH2(r13)
1018 lbz r9, HSTATE_IN_GUEST(r13)
1019 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1020 beq kvmppc_bad_host_intr
1021 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1022 cmpwi r9, KVM_GUEST_MODE_GUEST
1023 ld r9, HSTATE_SCRATCH2(r13)
1024 beq kvmppc_interrupt_pr
1026 /* We're now back in the host but in guest MMU context */
1027 li r9, KVM_GUEST_MODE_HOST_HV
1028 stb r9, HSTATE_IN_GUEST(r13)
1030 ld r9, HSTATE_KVM_VCPU(r13)
1032 /* Save registers */
1034 std r0, VCPU_GPR(R0)(r9)
1035 std r1, VCPU_GPR(R1)(r9)
1036 std r2, VCPU_GPR(R2)(r9)
1037 std r3, VCPU_GPR(R3)(r9)
1038 std r4, VCPU_GPR(R4)(r9)
1039 std r5, VCPU_GPR(R5)(r9)
1040 std r6, VCPU_GPR(R6)(r9)
1041 std r7, VCPU_GPR(R7)(r9)
1042 std r8, VCPU_GPR(R8)(r9)
1043 ld r0, HSTATE_SCRATCH2(r13)
1044 std r0, VCPU_GPR(R9)(r9)
1045 std r10, VCPU_GPR(R10)(r9)
1046 std r11, VCPU_GPR(R11)(r9)
1047 ld r3, HSTATE_SCRATCH0(r13)
1048 lwz r4, HSTATE_SCRATCH1(r13)
1049 std r3, VCPU_GPR(R12)(r9)
1052 ld r3, HSTATE_CFAR(r13)
1053 std r3, VCPU_CFAR(r9)
1054 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1056 ld r4, HSTATE_PPR(r13)
1057 std r4, VCPU_PPR(r9)
1058 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1060 /* Restore R1/R2 so we can handle faults */
1061 ld r1, HSTATE_HOST_R1(r13)
1064 mfspr r10, SPRN_SRR0
1065 mfspr r11, SPRN_SRR1
1066 std r10, VCPU_SRR0(r9)
1067 std r11, VCPU_SRR1(r9)
1068 andi. r0, r12, 2 /* need to read HSRR0/1? */
1070 mfspr r10, SPRN_HSRR0
1071 mfspr r11, SPRN_HSRR1
1073 1: std r10, VCPU_PC(r9)
1074 std r11, VCPU_MSR(r9)
1078 std r3, VCPU_GPR(R13)(r9)
1081 stw r12,VCPU_TRAP(r9)
1083 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1084 addi r3, r9, VCPU_TB_RMINTR
1086 bl kvmhv_accumulate_time
1087 ld r5, VCPU_GPR(R5)(r9)
1088 ld r6, VCPU_GPR(R6)(r9)
1089 ld r7, VCPU_GPR(R7)(r9)
1090 ld r8, VCPU_GPR(R8)(r9)
1093 /* Save HEIR (HV emulation assist reg) in emul_inst
1094 if this is an HEI (HV emulation interrupt, e40) */
1095 li r3,KVM_INST_FETCH_FAILED
1096 stw r3,VCPU_LAST_INST(r9)
1097 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1100 11: stw r3,VCPU_HEIR(r9)
1102 /* these are volatile across C function calls */
1105 std r3, VCPU_CTR(r9)
1106 stw r4, VCPU_XER(r9)
1108 /* If this is a page table miss then see if it's theirs or ours */
1109 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1111 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1114 /* See if this is a leftover HDEC interrupt */
1115 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1120 bge fast_guest_return
1122 /* See if this is an hcall we can handle in real mode */
1123 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1124 beq hcall_try_real_mode
1126 /* Hypervisor doorbell - exit only if host IPI flag set */
1127 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1129 lbz r0, HSTATE_HOST_IPI(r13)
1133 /* External interrupt ? */
1134 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1135 bne+ guest_exit_cont
1137 /* External interrupt, first check for host_ipi. If this is
1138 * set, we know the host wants us out so let's do it now
1144 /* Check if any CPU is heading out to the host, if so head out too */
1145 4: ld r5, HSTATE_KVM_VCORE(r13)
1146 lwz r0, VCORE_ENTRY_EXIT(r5)
1149 blt deliver_guest_interrupt
1151 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1152 /* Save more register state */
1155 std r6, VCPU_DAR(r9)
1156 stw r7, VCPU_DSISR(r9)
1157 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1158 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1160 std r6, VCPU_FAULT_DAR(r9)
1161 stw r7, VCPU_FAULT_DSISR(r9)
1163 /* See if it is a machine check */
1164 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1165 beq machine_check_realmode
1167 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1168 addi r3, r9, VCPU_TB_RMEXIT
1170 bl kvmhv_accumulate_time
1173 /* Increment exit count, poke other threads to exit */
1174 bl kvmhv_commence_exit
1176 ld r9, HSTATE_KVM_VCPU(r13)
1177 lwz r12, VCPU_TRAP(r9)
1179 /* Save guest CTRL register, set runlatch to 1 */
1181 stw r6,VCPU_CTRL(r9)
1187 /* Read the guest SLB and save it away */
1188 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1194 andis. r0,r8,SLB_ESID_V@h
1196 add r8,r8,r6 /* put index in */
1198 std r8,VCPU_SLB_E(r7)
1199 std r3,VCPU_SLB_V(r7)
1200 addi r7,r7,VCPU_SLB_SIZE
1204 stw r5,VCPU_SLB_MAX(r9)
1207 * Save the guest PURR/SPURR
1212 ld r8,VCPU_SPURR(r9)
1213 std r5,VCPU_PURR(r9)
1214 std r6,VCPU_SPURR(r9)
1219 * Restore host PURR/SPURR and add guest times
1220 * so that the time in the guest gets accounted.
1222 ld r3,HSTATE_PURR(r13)
1223 ld r4,HSTATE_SPURR(r13)
1234 /* r5 is a guest timebase value here, convert to host TB */
1235 ld r3,HSTATE_KVM_VCORE(r13)
1236 ld r4,VCORE_TB_OFFSET(r3)
1238 std r5,VCPU_DEC_EXPIRES(r9)
1242 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1243 /* Save POWER8-specific registers */
1247 std r5, VCPU_IAMR(r9)
1248 stw r6, VCPU_PSPB(r9)
1249 std r7, VCPU_FSCR(r9)
1254 std r6, VCPU_VTB(r9)
1255 std r7, VCPU_TAR(r9)
1256 mfspr r8, SPRN_EBBHR
1257 std r8, VCPU_EBBHR(r9)
1258 mfspr r5, SPRN_EBBRR
1259 mfspr r6, SPRN_BESCR
1260 mfspr r7, SPRN_CSIGR
1262 std r5, VCPU_EBBRR(r9)
1263 std r6, VCPU_BESCR(r9)
1264 std r7, VCPU_CSIGR(r9)
1265 std r8, VCPU_TACR(r9)
1266 mfspr r5, SPRN_TCSCR
1270 std r5, VCPU_TCSCR(r9)
1271 std r6, VCPU_ACOP(r9)
1272 stw r7, VCPU_GUEST_PID(r9)
1273 std r8, VCPU_WORT(r9)
1276 /* Save and reset AMR and UAMOR before turning on the MMU */
1280 std r6,VCPU_UAMOR(r9)
1284 /* Switch DSCR back to host value */
1286 ld r7, HSTATE_DSCR(r13)
1287 std r8, VCPU_DSCR(r9)
1290 /* Save non-volatile GPRs */
1291 std r14, VCPU_GPR(R14)(r9)
1292 std r15, VCPU_GPR(R15)(r9)
1293 std r16, VCPU_GPR(R16)(r9)
1294 std r17, VCPU_GPR(R17)(r9)
1295 std r18, VCPU_GPR(R18)(r9)
1296 std r19, VCPU_GPR(R19)(r9)
1297 std r20, VCPU_GPR(R20)(r9)
1298 std r21, VCPU_GPR(R21)(r9)
1299 std r22, VCPU_GPR(R22)(r9)
1300 std r23, VCPU_GPR(R23)(r9)
1301 std r24, VCPU_GPR(R24)(r9)
1302 std r25, VCPU_GPR(R25)(r9)
1303 std r26, VCPU_GPR(R26)(r9)
1304 std r27, VCPU_GPR(R27)(r9)
1305 std r28, VCPU_GPR(R28)(r9)
1306 std r29, VCPU_GPR(R29)(r9)
1307 std r30, VCPU_GPR(R30)(r9)
1308 std r31, VCPU_GPR(R31)(r9)
1311 mfspr r3, SPRN_SPRG0
1312 mfspr r4, SPRN_SPRG1
1313 mfspr r5, SPRN_SPRG2
1314 mfspr r6, SPRN_SPRG3
1315 std r3, VCPU_SPRG0(r9)
1316 std r4, VCPU_SPRG1(r9)
1317 std r5, VCPU_SPRG2(r9)
1318 std r6, VCPU_SPRG3(r9)
1324 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1327 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
1331 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
1335 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
1336 beq 1f /* TM not active in guest. */
1338 li r3, TM_CAUSE_KVM_RESCHED
1340 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
1344 /* All GPRs are volatile at this point. */
1347 /* Temporarily store r13 and r9 so we have some regs to play with */
1350 std r9, PACATMSCRATCH(r13)
1351 ld r9, HSTATE_KVM_VCPU(r13)
1353 /* Get a few more GPRs free. */
1354 std r29, VCPU_GPRS_TM(29)(r9)
1355 std r30, VCPU_GPRS_TM(30)(r9)
1356 std r31, VCPU_GPRS_TM(31)(r9)
1358 /* Save away PPR and DSCR soon so don't run with user values. */
1361 mfspr r30, SPRN_DSCR
1362 ld r29, HSTATE_DSCR(r13)
1363 mtspr SPRN_DSCR, r29
1365 /* Save all but r9, r13 & r29-r31 */
1368 .if (reg != 9) && (reg != 13)
1369 std reg, VCPU_GPRS_TM(reg)(r9)
1373 /* ... now save r13 */
1375 std r4, VCPU_GPRS_TM(13)(r9)
1376 /* ... and save r9 */
1377 ld r4, PACATMSCRATCH(r13)
1378 std r4, VCPU_GPRS_TM(9)(r9)
1380 /* Reload stack pointer and TOC. */
1381 ld r1, HSTATE_HOST_R1(r13)
1384 /* Set MSR RI now we have r1 and r13 back. */
1388 /* Save away checkpinted SPRs. */
1389 std r31, VCPU_PPR_TM(r9)
1390 std r30, VCPU_DSCR_TM(r9)
1396 std r5, VCPU_LR_TM(r9)
1397 stw r6, VCPU_CR_TM(r9)
1398 std r7, VCPU_CTR_TM(r9)
1399 std r8, VCPU_AMR_TM(r9)
1400 std r10, VCPU_TAR_TM(r9)
1402 /* Restore r12 as trap number. */
1403 lwz r12, VCPU_TRAP(r9)
1406 addi r3, r9, VCPU_FPRS_TM
1408 addi r3, r9, VCPU_VRS_TM
1410 mfspr r6, SPRN_VRSAVE
1411 stw r6, VCPU_VRSAVE_TM(r9)
1414 * We need to save these SPRs after the treclaim so that the software
1415 * error code is recorded correctly in the TEXASR. Also the user may
1416 * change these outside of a transaction, so they must always be
1419 mfspr r5, SPRN_TFHAR
1420 mfspr r6, SPRN_TFIAR
1421 mfspr r7, SPRN_TEXASR
1422 std r5, VCPU_TFHAR(r9)
1423 std r6, VCPU_TFIAR(r9)
1424 std r7, VCPU_TEXASR(r9)
1428 /* Increment yield count if they have a VPA */
1429 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1432 li r4, LPPACA_YIELDCOUNT
1437 stb r3, VCPU_VPA_DIRTY(r9)
1439 /* Save PMU registers if requested */
1440 /* r8 and cr0.eq are live here */
1443 * POWER8 seems to have a hardware bug where setting
1444 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1445 * when some counters are already negative doesn't seem
1446 * to cause a performance monitor alert (and hence interrupt).
1447 * The effect of this is that when saving the PMU state,
1448 * if there is no PMU alert pending when we read MMCR0
1449 * before freezing the counters, but one becomes pending
1450 * before we read the counters, we lose it.
1451 * To work around this, we need a way to freeze the counters
1452 * before reading MMCR0. Normally, freezing the counters
1453 * is done by writing MMCR0 (to set MMCR0[FC]) which
1454 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1455 * we can also freeze the counters using MMCR2, by writing
1456 * 1s to all the counter freeze condition bits (there are
1457 * 9 bits each for 6 counters).
1459 li r3, -1 /* set all freeze bits */
1461 mfspr r10, SPRN_MMCR2
1462 mtspr SPRN_MMCR2, r3
1464 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1466 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1467 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1468 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1469 mfspr r6, SPRN_MMCRA
1470 /* Clear MMCRA in order to disable SDAR updates */
1472 mtspr SPRN_MMCRA, r7
1474 beq 21f /* if no VPA, save PMU stuff anyway */
1475 lbz r7, LPPACA_PMCINUSE(r8)
1476 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1478 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1480 21: mfspr r5, SPRN_MMCR1
1483 std r4, VCPU_MMCR(r9)
1484 std r5, VCPU_MMCR + 8(r9)
1485 std r6, VCPU_MMCR + 16(r9)
1487 std r10, VCPU_MMCR + 24(r9)
1488 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1489 std r7, VCPU_SIAR(r9)
1490 std r8, VCPU_SDAR(r9)
1497 stw r3, VCPU_PMC(r9)
1498 stw r4, VCPU_PMC + 4(r9)
1499 stw r5, VCPU_PMC + 8(r9)
1500 stw r6, VCPU_PMC + 12(r9)
1501 stw r7, VCPU_PMC + 16(r9)
1502 stw r8, VCPU_PMC + 20(r9)
1505 mfspr r6, SPRN_SPMC1
1506 mfspr r7, SPRN_SPMC2
1507 mfspr r8, SPRN_MMCRS
1508 std r5, VCPU_SIER(r9)
1509 stw r6, VCPU_PMC + 24(r9)
1510 stw r7, VCPU_PMC + 28(r9)
1511 std r8, VCPU_MMCR + 32(r9)
1513 mtspr SPRN_MMCRS, r4
1514 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1523 * POWER7/POWER8 guest -> host partition switch code.
1524 * We don't have to lock against tlbies but we do
1525 * have to coordinate the hardware threads.
1527 kvmhv_switch_to_host:
1528 /* Secondary threads wait for primary to do partition switch */
1529 ld r5,HSTATE_KVM_VCORE(r13)
1530 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1531 lbz r3,HSTATE_PTID(r13)
1535 13: lbz r3,VCORE_IN_GUEST(r5)
1541 /* Primary thread waits for all the secondaries to exit guest */
1542 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1549 /* Primary thread switches back to host partition */
1550 ld r6,KVM_HOST_SDR1(r4)
1551 lwz r7,KVM_HOST_LPID(r4)
1552 li r8,LPID_RSVD /* switch to reserved LPID */
1555 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1560 /* DPDES is shared between threads */
1561 mfspr r7, SPRN_DPDES
1562 std r7, VCORE_DPDES(r5)
1563 /* clear DPDES so we don't get guest doorbells in the host */
1565 mtspr SPRN_DPDES, r8
1566 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1568 /* Subtract timebase offset from timebase */
1569 ld r8,VCORE_TB_OFFSET(r5)
1572 mftb r6 /* current guest timebase */
1574 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1575 mftb r7 /* check if lower 24 bits overflowed */
1580 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1584 17: ld r0, VCORE_PCR(r5)
1590 /* Signal secondary CPUs to continue */
1591 stb r0,VCORE_IN_GUEST(r5)
1592 lis r8,0x7fff /* MAX_INT@h */
1595 16: ld r8,KVM_HOST_LPCR(r4)
1599 /* load host SLB entries */
1600 ld r8,PACA_SLBSHADOWPTR(r13)
1602 .rept SLB_NUM_BOLTED
1603 li r3, SLBSHADOW_SAVEAREA
1607 andis. r7,r5,SLB_ESID_V@h
1613 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1614 /* Finish timing, if we have a vcpu */
1615 ld r4, HSTATE_KVM_VCPU(r13)
1619 bl kvmhv_accumulate_time
1622 /* Unset guest mode */
1623 li r0, KVM_GUEST_MODE_NONE
1624 stb r0, HSTATE_IN_GUEST(r13)
1626 ld r0, 112+PPC_LR_STKOFF(r1)
1632 * Check whether an HDSI is an HPTE not found fault or something else.
1633 * If it is an HPTE not found fault that is due to the guest accessing
1634 * a page that they have mapped but which we have paged out, then
1635 * we continue on with the guest exit path. In all other cases,
1636 * reflect the HDSI to the guest as a DSI.
1640 mfspr r6, SPRN_HDSISR
1641 /* HPTE not found fault or protection fault? */
1642 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1643 beq 1f /* if not, send it to the guest */
1644 andi. r0, r11, MSR_DR /* data relocation enabled? */
1647 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1648 bne 1f /* if no SLB entry found */
1649 4: std r4, VCPU_FAULT_DAR(r9)
1650 stw r6, VCPU_FAULT_DSISR(r9)
1652 /* Search the hash table. */
1653 mr r3, r9 /* vcpu pointer */
1654 li r7, 1 /* data fault */
1655 bl kvmppc_hpte_hv_fault
1656 ld r9, HSTATE_KVM_VCPU(r13)
1658 ld r11, VCPU_MSR(r9)
1659 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1660 cmpdi r3, 0 /* retry the instruction */
1662 cmpdi r3, -1 /* handle in kernel mode */
1664 cmpdi r3, -2 /* MMIO emulation; need instr word */
1667 /* Synthesize a DSI for the guest */
1668 ld r4, VCPU_FAULT_DAR(r9)
1670 1: mtspr SPRN_DAR, r4
1671 mtspr SPRN_DSISR, r6
1672 mtspr SPRN_SRR0, r10
1673 mtspr SPRN_SRR1, r11
1674 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1675 bl kvmppc_msr_interrupt
1676 fast_interrupt_c_return:
1677 6: ld r7, VCPU_CTR(r9)
1678 lwz r8, VCPU_XER(r9)
1684 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1685 ld r5, KVM_VRMA_SLB_V(r5)
1688 /* If this is for emulated MMIO, load the instruction word */
1689 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1691 /* Set guest mode to 'jump over instruction' so if lwz faults
1692 * we'll just continue at the next IP. */
1693 li r0, KVM_GUEST_MODE_SKIP
1694 stb r0, HSTATE_IN_GUEST(r13)
1696 /* Do the access with MSR:DR enabled */
1698 ori r4, r3, MSR_DR /* Enable paging for data */
1703 /* Store the result */
1704 stw r8, VCPU_LAST_INST(r9)
1706 /* Unset guest mode. */
1707 li r0, KVM_GUEST_MODE_HOST_HV
1708 stb r0, HSTATE_IN_GUEST(r13)
1712 * Similarly for an HISI, reflect it to the guest as an ISI unless
1713 * it is an HPTE not found fault for a page that we have paged out.
1716 andis. r0, r11, SRR1_ISI_NOPT@h
1718 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1721 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1722 bne 1f /* if no SLB entry found */
1724 /* Search the hash table. */
1725 mr r3, r9 /* vcpu pointer */
1728 li r7, 0 /* instruction fault */
1729 bl kvmppc_hpte_hv_fault
1730 ld r9, HSTATE_KVM_VCPU(r13)
1732 ld r11, VCPU_MSR(r9)
1733 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1734 cmpdi r3, 0 /* retry the instruction */
1735 beq fast_interrupt_c_return
1736 cmpdi r3, -1 /* handle in kernel mode */
1739 /* Synthesize an ISI for the guest */
1741 1: mtspr SPRN_SRR0, r10
1742 mtspr SPRN_SRR1, r11
1743 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1744 bl kvmppc_msr_interrupt
1745 b fast_interrupt_c_return
1747 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1748 ld r5, KVM_VRMA_SLB_V(r6)
1752 * Try to handle an hcall in real mode.
1753 * Returns to the guest if we handle it, or continues on up to
1754 * the kernel if we can't (i.e. if we don't have a handler for
1755 * it, or if the handler returns H_TOO_HARD).
1757 * r5 - r8 contain hcall args,
1758 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
1760 hcall_try_real_mode:
1761 ld r3,VCPU_GPR(R3)(r9)
1763 /* sc 1 from userspace - reflect to guest syscall */
1764 bne sc_1_fast_return
1766 cmpldi r3,hcall_real_table_end - hcall_real_table
1768 /* See if this hcall is enabled for in-kernel handling */
1770 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
1771 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
1773 ld r0, KVM_ENABLED_HCALLS(r4)
1774 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
1778 /* Get pointer to handler, if any, and call it */
1779 LOAD_REG_ADDR(r4, hcall_real_table)
1785 mr r3,r9 /* get vcpu pointer */
1786 ld r4,VCPU_GPR(R4)(r9)
1789 beq hcall_real_fallback
1790 ld r4,HSTATE_KVM_VCPU(r13)
1791 std r3,VCPU_GPR(R3)(r4)
1799 li r10, BOOK3S_INTERRUPT_SYSCALL
1800 bl kvmppc_msr_interrupt
1804 /* We've attempted a real mode hcall, but it's punted it back
1805 * to userspace. We need to restore some clobbered volatiles
1806 * before resuming the pass-it-to-qemu path */
1807 hcall_real_fallback:
1808 li r12,BOOK3S_INTERRUPT_SYSCALL
1809 ld r9, HSTATE_KVM_VCPU(r13)
1813 .globl hcall_real_table
1815 .long 0 /* 0 - unused */
1816 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
1817 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
1818 .long DOTSYM(kvmppc_h_read) - hcall_real_table
1819 .long 0 /* 0x10 - H_CLEAR_MOD */
1820 .long 0 /* 0x14 - H_CLEAR_REF */
1821 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
1822 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
1823 .long DOTSYM(kvmppc_h_put_tce) - hcall_real_table
1824 .long 0 /* 0x24 - H_SET_SPRG0 */
1825 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
1840 #ifdef CONFIG_KVM_XICS
1841 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
1842 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
1843 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
1844 .long 0 /* 0x70 - H_IPOLL */
1845 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
1847 .long 0 /* 0x64 - H_EOI */
1848 .long 0 /* 0x68 - H_CPPR */
1849 .long 0 /* 0x6c - H_IPI */
1850 .long 0 /* 0x70 - H_IPOLL */
1851 .long 0 /* 0x74 - H_XIRR */
1879 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
1880 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
1896 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
1900 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2015 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2016 .globl hcall_real_table_end
2017 hcall_real_table_end:
2019 _GLOBAL(kvmppc_h_set_xdabr)
2020 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2022 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2025 6: li r3, H_PARAMETER
2028 _GLOBAL(kvmppc_h_set_dabr)
2029 li r5, DABRX_USER | DABRX_KERNEL
2033 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2034 std r4,VCPU_DABR(r3)
2035 stw r5, VCPU_DABRX(r3)
2036 mtspr SPRN_DABRX, r5
2037 /* Work around P7 bug where DABR can get corrupted on mtspr */
2038 1: mtspr SPRN_DABR,r4
2046 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2047 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2048 rlwimi r5, r4, 1, DAWRX_WT
2050 std r4, VCPU_DAWR(r3)
2051 std r5, VCPU_DAWRX(r3)
2053 mtspr SPRN_DAWRX, r5
2057 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2059 std r11,VCPU_MSR(r3)
2061 stb r0,VCPU_CEDED(r3)
2062 sync /* order setting ceded vs. testing prodded */
2063 lbz r5,VCPU_PRODDED(r3)
2065 bne kvm_cede_prodded
2066 li r12,0 /* set trap to 0 to say hcall is handled */
2067 stw r12,VCPU_TRAP(r3)
2069 std r0,VCPU_GPR(R3)(r3)
2072 * Set our bit in the bitmask of napping threads unless all the
2073 * other threads are already napping, in which case we send this
2076 ld r5,HSTATE_KVM_VCORE(r13)
2077 lbz r6,HSTATE_PTID(r13)
2078 lwz r8,VCORE_ENTRY_EXIT(r5)
2082 addi r6,r5,VCORE_NAPPING_THREADS
2089 /* order napping_threads update vs testing entry_exit_map */
2092 stb r0,HSTATE_NAPPING(r13)
2093 lwz r7,VCORE_ENTRY_EXIT(r5)
2095 bge 33f /* another thread already exiting */
2098 * Although not specifically required by the architecture, POWER7
2099 * preserves the following registers in nap mode, even if an SMT mode
2100 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2101 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2103 /* Save non-volatile GPRs */
2104 std r14, VCPU_GPR(R14)(r3)
2105 std r15, VCPU_GPR(R15)(r3)
2106 std r16, VCPU_GPR(R16)(r3)
2107 std r17, VCPU_GPR(R17)(r3)
2108 std r18, VCPU_GPR(R18)(r3)
2109 std r19, VCPU_GPR(R19)(r3)
2110 std r20, VCPU_GPR(R20)(r3)
2111 std r21, VCPU_GPR(R21)(r3)
2112 std r22, VCPU_GPR(R22)(r3)
2113 std r23, VCPU_GPR(R23)(r3)
2114 std r24, VCPU_GPR(R24)(r3)
2115 std r25, VCPU_GPR(R25)(r3)
2116 std r26, VCPU_GPR(R26)(r3)
2117 std r27, VCPU_GPR(R27)(r3)
2118 std r28, VCPU_GPR(R28)(r3)
2119 std r29, VCPU_GPR(R29)(r3)
2120 std r30, VCPU_GPR(R30)(r3)
2121 std r31, VCPU_GPR(R31)(r3)
2127 * Set DEC to the smaller of DEC and HDEC, so that we wake
2128 * no later than the end of our timeslice (HDEC interrupts
2129 * don't wake us from nap).
2138 /* save expiry time of guest decrementer */
2141 ld r4, HSTATE_KVM_VCPU(r13)
2142 ld r5, HSTATE_KVM_VCORE(r13)
2143 ld r6, VCORE_TB_OFFSET(r5)
2144 subf r3, r6, r3 /* convert to host TB value */
2145 std r3, VCPU_DEC_EXPIRES(r4)
2147 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2148 ld r4, HSTATE_KVM_VCPU(r13)
2149 addi r3, r4, VCPU_TB_CEDE
2150 bl kvmhv_accumulate_time
2153 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2156 * Take a nap until a decrementer or external or doobell interrupt
2157 * occurs, with PECE1 and PECE0 set in LPCR.
2158 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2159 * Also clear the runlatch bit before napping.
2162 mfspr r0, SPRN_CTRLF
2164 mtspr SPRN_CTRLT, r0
2167 stb r0,HSTATE_HWTHREAD_REQ(r13)
2169 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2171 ori r5, r5, LPCR_PECEDH
2172 rlwimi r5, r3, 0, LPCR_PECEDP
2173 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2177 std r0, HSTATE_SCRATCH0(r13)
2179 ld r0, HSTATE_SCRATCH0(r13)
2191 /* get vcpu pointer */
2192 ld r4, HSTATE_KVM_VCPU(r13)
2194 /* Woken by external or decrementer interrupt */
2195 ld r1, HSTATE_HOST_R1(r13)
2197 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2198 addi r3, r4, VCPU_TB_RMINTR
2199 bl kvmhv_accumulate_time
2202 /* load up FP state */
2205 /* Restore guest decrementer */
2206 ld r3, VCPU_DEC_EXPIRES(r4)
2207 ld r5, HSTATE_KVM_VCORE(r13)
2208 ld r6, VCORE_TB_OFFSET(r5)
2209 add r3, r3, r6 /* convert host TB to guest TB value */
2215 ld r14, VCPU_GPR(R14)(r4)
2216 ld r15, VCPU_GPR(R15)(r4)
2217 ld r16, VCPU_GPR(R16)(r4)
2218 ld r17, VCPU_GPR(R17)(r4)
2219 ld r18, VCPU_GPR(R18)(r4)
2220 ld r19, VCPU_GPR(R19)(r4)
2221 ld r20, VCPU_GPR(R20)(r4)
2222 ld r21, VCPU_GPR(R21)(r4)
2223 ld r22, VCPU_GPR(R22)(r4)
2224 ld r23, VCPU_GPR(R23)(r4)
2225 ld r24, VCPU_GPR(R24)(r4)
2226 ld r25, VCPU_GPR(R25)(r4)
2227 ld r26, VCPU_GPR(R26)(r4)
2228 ld r27, VCPU_GPR(R27)(r4)
2229 ld r28, VCPU_GPR(R28)(r4)
2230 ld r29, VCPU_GPR(R29)(r4)
2231 ld r30, VCPU_GPR(R30)(r4)
2232 ld r31, VCPU_GPR(R31)(r4)
2234 /* Check the wake reason in SRR1 to see why we got here */
2235 bl kvmppc_check_wake_reason
2237 /* clear our bit in vcore->napping_threads */
2238 34: ld r5,HSTATE_KVM_VCORE(r13)
2239 lbz r7,HSTATE_PTID(r13)
2242 addi r6,r5,VCORE_NAPPING_THREADS
2248 stb r0,HSTATE_NAPPING(r13)
2250 /* See if the wake reason means we need to exit */
2251 stw r12, VCPU_TRAP(r4)
2256 /* see if any other thread is already exiting */
2257 lwz r0,VCORE_ENTRY_EXIT(r5)
2261 b kvmppc_cede_reentry /* if not go back to guest */
2263 /* cede when already previously prodded case */
2266 stb r0,VCPU_PRODDED(r3)
2267 sync /* order testing prodded vs. clearing ceded */
2268 stb r0,VCPU_CEDED(r3)
2272 /* we've ceded but we want to give control to the host */
2274 ld r9, HSTATE_KVM_VCPU(r13)
2277 /* Try to handle a machine check in real mode */
2278 machine_check_realmode:
2279 mr r3, r9 /* get vcpu pointer */
2280 bl kvmppc_realmode_machine_check
2282 cmpdi r3, 0 /* Did we handle MCE ? */
2283 ld r9, HSTATE_KVM_VCPU(r13)
2284 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2286 * Deliver unhandled/fatal (e.g. UE) MCE errors to guest through
2287 * machine check interrupt (set HSRR0 to 0x200). And for handled
2288 * errors (no-fatal), just go back to guest execution with current
2289 * HSRR0 instead of exiting guest. This new approach will inject
2290 * machine check to guest for fatal error causing guest to crash.
2292 * The old code used to return to host for unhandled errors which
2293 * was causing guest to hang with soft lockups inside guest and
2294 * makes it difficult to recover guest instance.
2297 ld r11, VCPU_MSR(r9)
2298 bne 2f /* Continue guest execution. */
2299 /* If not, deliver a machine check. SRR0/1 are already set */
2300 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2301 ld r11, VCPU_MSR(r9)
2302 bl kvmppc_msr_interrupt
2303 2: b fast_interrupt_c_return
2306 * Check the reason we woke from nap, and take appropriate action.
2308 * 0 if nothing needs to be done
2309 * 1 if something happened that needs to be handled by the host
2310 * -1 if there was a guest wakeup (IPI or msgsnd)
2312 * Also sets r12 to the interrupt vector for any interrupt that needs
2313 * to be handled now by the host (0x500 for external interrupt), or zero.
2314 * Modifies r0, r6, r7, r8.
2316 kvmppc_check_wake_reason:
2319 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2321 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2322 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2323 cmpwi r6, 8 /* was it an external interrupt? */
2324 li r12, BOOK3S_INTERRUPT_EXTERNAL
2325 beq kvmppc_read_intr /* if so, see what it was */
2328 cmpwi r6, 6 /* was it the decrementer? */
2331 cmpwi r6, 5 /* privileged doorbell? */
2333 cmpwi r6, 3 /* hypervisor doorbell? */
2335 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2336 li r3, 1 /* anything else, return 1 */
2339 /* hypervisor doorbell */
2340 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2341 /* see if it's a host IPI */
2343 lbz r0, HSTATE_HOST_IPI(r13)
2346 /* if not, clear it and return -1 */
2347 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2353 * Determine what sort of external interrupt is pending (if any).
2355 * 0 if no interrupt is pending
2356 * 1 if an interrupt is pending that needs to be handled by the host
2357 * -1 if there was a guest wakeup IPI (which has now been cleared)
2358 * Modifies r0, r6, r7, r8, returns value in r3.
2361 /* see if a host IPI is pending */
2363 lbz r0, HSTATE_HOST_IPI(r13)
2367 /* Now read the interrupt from the ICP */
2368 ld r6, HSTATE_XICS_PHYS(r13)
2374 * Save XIRR for later. Since we get in in reverse endian on LE
2375 * systems, save it byte reversed and fetch it back in host endian.
2377 li r3, HSTATE_SAVED_XIRR
2379 #ifdef __LITTLE_ENDIAN__
2380 lwz r3, HSTATE_SAVED_XIRR(r13)
2384 rlwinm. r3, r3, 0, 0xffffff
2386 beq 1f /* if nothing pending in the ICP */
2388 /* We found something in the ICP...
2390 * If it's not an IPI, stash it in the PACA and return to
2391 * the host, we don't (yet) handle directing real external
2392 * interrupts directly to the guest
2394 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
2397 /* It's an IPI, clear the MFRR and EOI it */
2400 stbcix r3, r6, r8 /* clear the IPI */
2401 stwcix r0, r6, r7 /* EOI it */
2404 /* We need to re-check host IPI now in case it got set in the
2405 * meantime. If it's clear, we bounce the interrupt to the
2408 lbz r0, HSTATE_HOST_IPI(r13)
2412 /* OK, it's an IPI for us */
2417 42: /* It's not an IPI and it's for the host. We saved a copy of XIRR in
2418 * the PACA earlier, it will be picked up by the host ICP driver
2423 43: /* We raced with the host, we need to resend that IPI, bummer */
2425 stbcix r0, r6, r8 /* set the IPI */
2431 * Save away FP, VMX and VSX registers.
2433 * N.B. r30 and r31 are volatile across this function,
2434 * thus it is not callable from C.
2441 #ifdef CONFIG_ALTIVEC
2443 oris r8,r8,MSR_VEC@h
2444 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2448 oris r8,r8,MSR_VSX@h
2449 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2452 addi r3,r3,VCPU_FPRS
2454 #ifdef CONFIG_ALTIVEC
2456 addi r3,r31,VCPU_VRS
2458 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2460 mfspr r6,SPRN_VRSAVE
2461 stw r6,VCPU_VRSAVE(r31)
2466 * Load up FP, VMX and VSX registers
2468 * N.B. r30 and r31 are volatile across this function,
2469 * thus it is not callable from C.
2476 #ifdef CONFIG_ALTIVEC
2478 oris r8,r8,MSR_VEC@h
2479 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2483 oris r8,r8,MSR_VSX@h
2484 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2487 addi r3,r4,VCPU_FPRS
2489 #ifdef CONFIG_ALTIVEC
2491 addi r3,r31,VCPU_VRS
2493 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2495 lwz r7,VCPU_VRSAVE(r31)
2496 mtspr SPRN_VRSAVE,r7
2502 * We come here if we get any exception or interrupt while we are
2503 * executing host real mode code while in guest MMU context.
2504 * For now just spin, but we should do something better.
2506 kvmppc_bad_host_intr:
2510 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
2511 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
2512 * r11 has the guest MSR value (in/out)
2513 * r9 has a vcpu pointer (in)
2514 * r0 is used as a scratch register
2516 kvmppc_msr_interrupt:
2517 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
2518 cmpwi r0, 2 /* Check if we are in transactional state.. */
2519 ld r11, VCPU_INTR_MSR(r9)
2521 /* ... if transactional, change to suspended */
2523 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
2527 * This works around a hardware bug on POWER8E processors, where
2528 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
2529 * performance monitor interrupt. Instead, when we need to have
2530 * an interrupt pending, we have to arrange for a counter to overflow.
2534 mtspr SPRN_MMCR2, r3
2535 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
2536 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
2537 mtspr SPRN_MMCR0, r3
2544 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2546 * Start timing an activity
2547 * r3 = pointer to time accumulation struct, r4 = vcpu
2550 ld r5, HSTATE_KVM_VCORE(r13)
2551 lbz r6, VCORE_IN_GUEST(r5)
2553 beq 5f /* if in guest, need to */
2554 ld r6, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
2557 std r3, VCPU_CUR_ACTIVITY(r4)
2558 std r5, VCPU_ACTIVITY_START(r4)
2562 * Accumulate time to one activity and start another.
2563 * r3 = pointer to new time accumulation struct, r4 = vcpu
2565 kvmhv_accumulate_time:
2566 ld r5, HSTATE_KVM_VCORE(r13)
2567 lbz r8, VCORE_IN_GUEST(r5)
2569 beq 4f /* if in guest, need to */
2570 ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
2571 4: ld r5, VCPU_CUR_ACTIVITY(r4)
2572 ld r6, VCPU_ACTIVITY_START(r4)
2573 std r3, VCPU_CUR_ACTIVITY(r4)
2576 std r7, VCPU_ACTIVITY_START(r4)
2580 ld r8, TAS_SEQCOUNT(r5)
2583 std r8, TAS_SEQCOUNT(r5)
2585 ld r7, TAS_TOTAL(r5)
2587 std r7, TAS_TOTAL(r5)
2593 3: std r3, TAS_MIN(r5)
2599 std r8, TAS_SEQCOUNT(r5)