2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
32 #ifdef __LITTLE_ENDIAN__
33 #error Need to fix lppaca and SLB shadow accesses in little endian mode
36 /*****************************************************************************
38 * Real Mode handlers that need to be in the linear mapping *
40 ****************************************************************************/
42 .globl kvmppc_skip_interrupt
43 kvmppc_skip_interrupt:
51 .globl kvmppc_skip_Hinterrupt
52 kvmppc_skip_Hinterrupt:
61 * Call kvmppc_hv_entry in real mode.
62 * Must be called with interrupts hard-disabled.
66 * LR = return address to continue at after eventually re-enabling MMU
68 _GLOBAL(kvmppc_hv_entry_trampoline)
70 LOAD_REG_ADDR(r5, kvmppc_hv_entry)
75 mtmsrd r0,1 /* clear RI in MSR */
80 /******************************************************************************
84 *****************************************************************************/
87 * We come in here when wakened from nap mode on a secondary hw thread.
88 * Relocation is off and most register values are lost.
89 * r13 points to the PACA.
91 .globl kvm_start_guest
93 ld r1,PACAEMERGSP(r13)
94 subi r1,r1,STACK_FRAME_OVERHEAD
97 li r0,KVM_HWTHREAD_IN_KVM
98 stb r0,HSTATE_HWTHREAD_STATE(r13)
100 /* NV GPR values from power7_idle() will no longer be valid */
102 stb r0,PACA_NAPSTATELOST(r13)
104 /* were we napping due to cede? */
105 lbz r0,HSTATE_NAPPING(r13)
110 * We weren't napping due to cede, so this must be a secondary
111 * thread being woken up to run a guest, or being woken up due
112 * to a stray IPI. (Or due to some machine check or hypervisor
113 * maintenance interrupt while the core is in KVM.)
116 /* Check the wake reason in SRR1 to see why we got here */
118 rlwinm r3,r3,44-31,0x7 /* extract wake reason field */
119 cmpwi r3,4 /* was it an external interrupt? */
121 ld r5,HSTATE_XICS_PHYS(r13)
122 li r7,XICS_XIRR /* if it was an external interrupt, */
123 lwzcix r8,r5,r7 /* get and ack the interrupt */
125 clrldi. r9,r8,40 /* get interrupt source ID. */
126 beq 28f /* none there? */
127 cmpwi r9,XICS_IPI /* was it an IPI? */
131 stbcix r0,r5,r6 /* clear IPI */
132 stwcix r8,r5,r7 /* EOI the interrupt */
133 sync /* order loading of vcpu after that */
135 /* get vcpu pointer, NULL if we have no vcpu to run */
136 ld r4,HSTATE_KVM_VCPU(r13)
138 /* if we have no vcpu to run, go back to sleep */
142 27: /* XXX should handle hypervisor maintenance interrupts etc. here */
144 28: /* SRR1 said external but ICP said nope?? */
146 29: /* External non-IPI interrupt to offline secondary thread? help?? */
147 stw r8,HSTATE_SAVED_XIRR(r13)
150 .global kvmppc_hv_entry
159 * all other volatile GPRS = free
162 std r0, HSTATE_VMHANDLER(r13)
164 /* Set partition DABR */
165 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
172 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
174 /* Load guest PMU registers */
175 /* R4 is live here (vcpu pointer) */
177 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
178 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
180 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
181 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
182 lwz r6, VCPU_PMC + 8(r4)
183 lwz r7, VCPU_PMC + 12(r4)
184 lwz r8, VCPU_PMC + 16(r4)
185 lwz r9, VCPU_PMC + 20(r4)
187 lwz r10, VCPU_PMC + 24(r4)
188 lwz r11, VCPU_PMC + 28(r4)
189 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
199 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
201 ld r5, VCPU_MMCR + 8(r4)
202 ld r6, VCPU_MMCR + 16(r4)
212 /* Load up FP, VMX and VSX registers */
215 ld r14, VCPU_GPR(R14)(r4)
216 ld r15, VCPU_GPR(R15)(r4)
217 ld r16, VCPU_GPR(R16)(r4)
218 ld r17, VCPU_GPR(R17)(r4)
219 ld r18, VCPU_GPR(R18)(r4)
220 ld r19, VCPU_GPR(R19)(r4)
221 ld r20, VCPU_GPR(R20)(r4)
222 ld r21, VCPU_GPR(R21)(r4)
223 ld r22, VCPU_GPR(R22)(r4)
224 ld r23, VCPU_GPR(R23)(r4)
225 ld r24, VCPU_GPR(R24)(r4)
226 ld r25, VCPU_GPR(R25)(r4)
227 ld r26, VCPU_GPR(R26)(r4)
228 ld r27, VCPU_GPR(R27)(r4)
229 ld r28, VCPU_GPR(R28)(r4)
230 ld r29, VCPU_GPR(R29)(r4)
231 ld r30, VCPU_GPR(R30)(r4)
232 ld r31, VCPU_GPR(R31)(r4)
235 /* Switch DSCR to guest value */
238 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
241 * Set the decrementer to the guest decrementer.
243 ld r8,VCPU_DEC_EXPIRES(r4)
249 ld r5, VCPU_SPRG0(r4)
250 ld r6, VCPU_SPRG1(r4)
251 ld r7, VCPU_SPRG2(r4)
252 ld r8, VCPU_SPRG3(r4)
258 /* Save R1 in the PACA */
259 std r1, HSTATE_HOST_R1(r13)
261 /* Increment yield count if they have a VPA */
265 lwz r5, LPPACA_YIELDCOUNT(r3)
267 stw r5, LPPACA_YIELDCOUNT(r3)
269 stb r6, VCPU_VPA_DIRTY(r4)
271 /* Load up DAR and DSISR */
273 lwz r6, VCPU_DSISR(r4)
278 /* Restore AMR and UAMOR, set AMOR to all 1s */
285 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
295 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
297 * POWER7 host -> guest partition switch code.
298 * We don't have to lock against concurrent tlbies,
299 * but we do have to coordinate across hardware threads.
301 /* Increment entry count iff exit count is zero. */
302 ld r5,HSTATE_KVM_VCORE(r13)
303 addi r9,r5,VCORE_ENTRY_EXIT
305 cmpwi r3,0x100 /* any threads starting to exit? */
306 bge secondary_too_late /* if so we're too late to the party */
311 /* Primary thread switches to guest partition. */
312 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
318 li r0,LPID_RSVD /* switch to reserved LPID */
321 mtspr SPRN_SDR1,r6 /* switch to partition page table */
325 /* See if we need to flush the TLB */
326 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
327 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
328 srdi r6,r6,6 /* doubleword number */
329 sldi r6,r6,3 /* address offset */
331 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
337 23: ldarx r7,0,r6 /* if set, clear the bit */
341 li r6,128 /* and flush the TLB */
343 li r7,0x800 /* IS field = 0b10 */
350 /* Add timebase offset onto timebase */
351 22: ld r8,VCORE_TB_OFFSET(r5)
354 mftb r6 /* current host timebase */
356 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
357 mftb r7 /* check if lower 24 bits overflowed */
362 addis r8,r8,0x100 /* if so, increment upper 40 bits */
366 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
369 /* Secondary threads wait for primary to have done partition switch */
370 20: lbz r0,VCORE_IN_GUEST(r5)
374 /* Set LPCR and RMOR. */
375 10: ld r8,KVM_LPCR(r9)
381 /* Check if HDEC expires soon */
384 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
388 /* Save purr/spurr */
391 std r5,HSTATE_PURR(r13)
392 std r6,HSTATE_SPURR(r13)
400 * PPC970 host -> guest partition switch code.
401 * We have to lock against concurrent tlbies,
402 * using native_tlbie_lock to lock against host tlbies
403 * and kvm->arch.tlbie_lock to lock against guest tlbies.
404 * We also have to invalidate the TLB since its
405 * entries aren't tagged with the LPID.
407 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
409 /* first take native_tlbie_lock */
412 .tc native_tlbie_lock[TC],native_tlbie_lock
414 ld r3,toc_tlbie_lock@toc(2)
415 #ifdef __BIG_ENDIAN__
416 lwz r8,PACA_LOCK_TOKEN(r13)
418 lwz r8,PACAPACAINDEX(r13)
427 ld r7,KVM_LPCR(r9) /* use kvm->arch.lpcr to store HID4 */
429 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
433 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
436 stw r0,0(r3) /* drop native_tlbie_lock */
438 /* invalidate the whole TLB */
447 /* Take the guest's tlbie_lock */
448 addi r3,r9,KVM_TLBIE_LOCK
456 mtspr SPRN_SDR1,r6 /* switch to partition page table */
458 /* Set up HID4 with the guest's LPID etc. */
463 /* drop the guest's tlbie_lock */
467 /* Check if HDEC expires soon */
470 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
474 /* Enable HDEC interrupts */
477 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
487 /* Load up guest SLB entries */
488 31: lwz r5,VCPU_SLB_MAX(r4)
493 1: ld r8,VCPU_SLB_E(r6)
496 addi r6,r6,VCPU_SLB_SIZE
500 /* Restore state of CTRL run bit; assume 1 on entry */
516 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
520 /* r11 = vcpu->arch.msr & ~MSR_HV */
521 rldicl r11, r11, 63 - MSR_HV_LG, 1
522 rotldi r11, r11, 1 + MSR_HV_LG
525 /* Check if we can deliver an external or decrementer interrupt now */
526 ld r0,VCPU_PENDING_EXC(r4)
527 lis r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
537 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
539 li r0,BOOK3S_INTERRUPT_EXTERNAL
543 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
549 li r0,BOOK3S_INTERRUPT_DECREMENTER
552 /* Move SRR0 and SRR1 into the respective regs */
553 5: mtspr SPRN_SRR0, r6
558 stb r0,VCPU_CEDED(r4) /* cancel cede */
562 /* Activate guest mode, so faults get handled by KVM */
563 li r9, KVM_GUEST_MODE_GUEST
564 stb r9, HSTATE_IN_GUEST(r13)
571 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
578 ld r0, VCPU_GPR(R0)(r4)
579 ld r1, VCPU_GPR(R1)(r4)
580 ld r2, VCPU_GPR(R2)(r4)
581 ld r3, VCPU_GPR(R3)(r4)
582 ld r5, VCPU_GPR(R5)(r4)
583 ld r6, VCPU_GPR(R6)(r4)
584 ld r7, VCPU_GPR(R7)(r4)
585 ld r8, VCPU_GPR(R8)(r4)
586 ld r9, VCPU_GPR(R9)(r4)
587 ld r10, VCPU_GPR(R10)(r4)
588 ld r11, VCPU_GPR(R11)(r4)
589 ld r12, VCPU_GPR(R12)(r4)
590 ld r13, VCPU_GPR(R13)(r4)
592 ld r4, VCPU_GPR(R4)(r4)
597 /******************************************************************************
601 *****************************************************************************/
604 * We come here from the first-level interrupt handlers.
606 .globl kvmppc_interrupt
610 * R12 = interrupt vector
612 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
613 * guest R13 saved in SPRN_SCRATCH0
615 /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */
616 std r9, HSTATE_HOST_R2(r13)
617 ld r9, HSTATE_KVM_VCPU(r13)
621 std r0, VCPU_GPR(R0)(r9)
622 std r1, VCPU_GPR(R1)(r9)
623 std r2, VCPU_GPR(R2)(r9)
624 std r3, VCPU_GPR(R3)(r9)
625 std r4, VCPU_GPR(R4)(r9)
626 std r5, VCPU_GPR(R5)(r9)
627 std r6, VCPU_GPR(R6)(r9)
628 std r7, VCPU_GPR(R7)(r9)
629 std r8, VCPU_GPR(R8)(r9)
630 ld r0, HSTATE_HOST_R2(r13)
631 std r0, VCPU_GPR(R9)(r9)
632 std r10, VCPU_GPR(R10)(r9)
633 std r11, VCPU_GPR(R11)(r9)
634 ld r3, HSTATE_SCRATCH0(r13)
635 lwz r4, HSTATE_SCRATCH1(r13)
636 std r3, VCPU_GPR(R12)(r9)
639 ld r3, HSTATE_CFAR(r13)
640 std r3, VCPU_CFAR(r9)
641 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
643 /* Restore R1/R2 so we can handle faults */
644 ld r1, HSTATE_HOST_R1(r13)
649 std r10, VCPU_SRR0(r9)
650 std r11, VCPU_SRR1(r9)
651 andi. r0, r12, 2 /* need to read HSRR0/1? */
653 mfspr r10, SPRN_HSRR0
654 mfspr r11, SPRN_HSRR1
656 1: std r10, VCPU_PC(r9)
657 std r11, VCPU_MSR(r9)
661 std r3, VCPU_GPR(R13)(r9)
664 /* Unset guest mode */
665 li r0, KVM_GUEST_MODE_NONE
666 stb r0, HSTATE_IN_GUEST(r13)
668 stw r12,VCPU_TRAP(r9)
670 /* Save HEIR (HV emulation assist reg) in last_inst
671 if this is an HEI (HV emulation interrupt, e40) */
672 li r3,KVM_INST_FETCH_FAILED
674 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
677 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
678 11: stw r3,VCPU_LAST_INST(r9)
680 /* these are volatile across C function calls */
687 /* If this is a page table miss then see if it's theirs or ours */
688 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
690 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
692 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
694 /* See if this is a leftover HDEC interrupt */
695 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
701 /* See if this is an hcall we can handle in real mode */
702 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
703 beq hcall_try_real_mode
705 /* Only handle external interrupts here on arch 206 and later */
707 b ext_interrupt_to_host
708 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
710 /* External interrupt ? */
711 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
712 bne+ ext_interrupt_to_host
714 /* External interrupt, first check for host_ipi. If this is
715 * set, we know the host wants us out so let's do it now
718 lbz r0, HSTATE_HOST_IPI(r13)
720 bne ext_interrupt_to_host
722 /* Now read the interrupt from the ICP */
723 ld r5, HSTATE_XICS_PHYS(r13)
726 beq- ext_interrupt_to_host
728 rlwinm. r0, r3, 0, 0xffffff
730 beq 3f /* if nothing pending in the ICP */
732 /* We found something in the ICP...
734 * If it's not an IPI, stash it in the PACA and return to
735 * the host, we don't (yet) handle directing real external
736 * interrupts directly to the guest
739 bne ext_stash_for_host
741 /* It's an IPI, clear the MFRR and EOI it */
744 stbcix r0, r5, r6 /* clear the IPI */
745 stwcix r3, r5, r7 /* EOI it */
748 /* We need to re-check host IPI now in case it got set in the
749 * meantime. If it's clear, we bounce the interrupt to the
752 lbz r0, HSTATE_HOST_IPI(r13)
756 /* Allright, looks like an IPI for the guest, we need to set MER */
758 /* Check if any CPU is heading out to the host, if so head out too */
759 ld r5, HSTATE_KVM_VCORE(r13)
760 lwz r0, VCORE_ENTRY_EXIT(r5)
762 bge ext_interrupt_to_host
764 /* See if there is a pending interrupt for the guest */
766 ld r0, VCPU_PENDING_EXC(r9)
767 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
768 rldicl. r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
769 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
772 /* And if the guest EE is set, we can deliver immediately, else
773 * we return to the guest with MER set
775 andi. r0, r11, MSR_EE
779 li r10, BOOK3S_INTERRUPT_EXTERNAL
780 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
786 /* We raced with the host, we need to resend that IPI, bummer */
787 1: li r0, IPI_PRIORITY
788 stbcix r0, r5, r6 /* set the IPI */
790 b ext_interrupt_to_host
793 /* It's not an IPI and it's for the host, stash it in the PACA
794 * before exit, it will be picked up by the host ICP driver
796 stw r3, HSTATE_SAVED_XIRR(r13)
797 ext_interrupt_to_host:
799 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
800 /* Save more register state */
804 stw r7, VCPU_DSISR(r9)
806 /* don't overwrite fault_dar/fault_dsisr if HDSI */
807 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
809 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
810 std r6, VCPU_FAULT_DAR(r9)
811 stw r7, VCPU_FAULT_DSISR(r9)
813 /* See if it is a machine check */
814 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
815 beq machine_check_realmode
818 /* Save guest CTRL register, set runlatch to 1 */
819 6: mfspr r6,SPRN_CTRLF
826 /* Read the guest SLB and save it away */
827 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
833 andis. r0,r8,SLB_ESID_V@h
835 add r8,r8,r6 /* put index in */
837 std r8,VCPU_SLB_E(r7)
838 std r3,VCPU_SLB_V(r7)
839 addi r7,r7,VCPU_SLB_SIZE
843 stw r5,VCPU_SLB_MAX(r9)
846 * Save the guest PURR/SPURR
854 std r6,VCPU_SPURR(r9)
859 * Restore host PURR/SPURR and add guest times
860 * so that the time in the guest gets accounted.
862 ld r3,HSTATE_PURR(r13)
863 ld r4,HSTATE_SPURR(r13)
868 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
876 hdec_soon: /* r9 = vcpu, r12 = trap, r13 = paca */
879 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
881 * POWER7 guest -> host partition switch code.
882 * We don't have to lock against tlbies but we do
883 * have to coordinate the hardware threads.
885 /* Increment the threads-exiting-guest count in the 0xff00
886 bits of vcore->entry_exit_count */
888 ld r5,HSTATE_KVM_VCORE(r13)
889 addi r6,r5,VCORE_ENTRY_EXIT
897 * At this point we have an interrupt that we have to pass
898 * up to the kernel or qemu; we can't handle it in real mode.
899 * Thus we have to do a partition switch, so we have to
900 * collect the other threads, if we are the first thread
901 * to take an interrupt. To do this, we set the HDEC to 0,
902 * which causes an HDEC interrupt in all threads within 2ns
903 * because the HDEC register is shared between all 4 threads.
904 * However, we don't need to bother if this is an HDEC
905 * interrupt, since the other threads will already be on their
906 * way here in that case.
908 cmpwi r3,0x100 /* Are we the first here? */
910 cmpwi r3,1 /* Are any other threads in the guest? */
912 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
918 * Send an IPI to any napping threads, since an HDEC interrupt
919 * doesn't wake CPUs up from nap.
921 lwz r3,VCORE_NAPPING_THREADS(r5)
925 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
927 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
931 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
934 stbcix r0,r7,r8 /* trigger the IPI */
939 /* Secondary threads wait for primary to do partition switch */
940 43: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
941 ld r5,HSTATE_KVM_VCORE(r13)
946 13: lbz r3,VCORE_IN_GUEST(r5)
952 /* Primary thread waits for all the secondaries to exit guest */
953 15: lwz r3,VCORE_ENTRY_EXIT(r5)
960 /* Primary thread switches back to host partition */
961 ld r6,KVM_HOST_SDR1(r4)
962 lwz r7,KVM_HOST_LPID(r4)
963 li r8,LPID_RSVD /* switch to reserved LPID */
966 mtspr SPRN_SDR1,r6 /* switch to partition page table */
970 /* Subtract timebase offset from timebase */
971 ld r8,VCORE_TB_OFFSET(r5)
974 mftb r6 /* current host timebase */
976 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
977 mftb r7 /* check if lower 24 bits overflowed */
982 addis r8,r8,0x100 /* if so, increment upper 40 bits */
985 /* Signal secondary CPUs to continue */
987 stb r0,VCORE_IN_GUEST(r5)
988 lis r8,0x7fff /* MAX_INT@h */
991 16: ld r8,KVM_HOST_LPCR(r4)
997 * PPC970 guest -> host partition switch code.
998 * We have to lock against concurrent tlbies, and
999 * we have to flush the whole TLB.
1001 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
1003 /* Take the guest's tlbie_lock */
1004 #ifdef __BIG_ENDIAN__
1005 lwz r8,PACA_LOCK_TOKEN(r13)
1007 lwz r8,PACAPACAINDEX(r13)
1009 addi r3,r4,KVM_TLBIE_LOCK
1017 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
1019 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
1023 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
1026 stw r0,0(r3) /* drop guest tlbie_lock */
1028 /* invalidate the whole TLB */
1037 /* take native_tlbie_lock */
1038 ld r3,toc_tlbie_lock@toc(2)
1046 ld r6,KVM_HOST_SDR1(r4)
1047 mtspr SPRN_SDR1,r6 /* switch to host page table */
1049 /* Set up host HID4 value */
1054 stw r0,0(r3) /* drop native_tlbie_lock */
1056 lis r8,0x7fff /* MAX_INT@h */
1059 /* Disable HDEC interrupts */
1062 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1072 /* load host SLB entries */
1073 33: ld r8,PACA_SLBSHADOWPTR(r13)
1075 .rept SLB_NUM_BOLTED
1076 ld r5,SLBSHADOW_SAVEAREA(r8)
1077 ld r6,SLBSHADOW_SAVEAREA+8(r8)
1078 andis. r7,r5,SLB_ESID_V@h
1089 std r5,VCPU_DEC_EXPIRES(r9)
1091 /* Save and reset AMR and UAMOR before turning on the MMU */
1096 std r6,VCPU_UAMOR(r9)
1099 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1101 /* Switch DSCR back to host value */
1104 ld r7, HSTATE_DSCR(r13)
1105 std r8, VCPU_DSCR(r7)
1107 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1109 /* Save non-volatile GPRs */
1110 std r14, VCPU_GPR(R14)(r9)
1111 std r15, VCPU_GPR(R15)(r9)
1112 std r16, VCPU_GPR(R16)(r9)
1113 std r17, VCPU_GPR(R17)(r9)
1114 std r18, VCPU_GPR(R18)(r9)
1115 std r19, VCPU_GPR(R19)(r9)
1116 std r20, VCPU_GPR(R20)(r9)
1117 std r21, VCPU_GPR(R21)(r9)
1118 std r22, VCPU_GPR(R22)(r9)
1119 std r23, VCPU_GPR(R23)(r9)
1120 std r24, VCPU_GPR(R24)(r9)
1121 std r25, VCPU_GPR(R25)(r9)
1122 std r26, VCPU_GPR(R26)(r9)
1123 std r27, VCPU_GPR(R27)(r9)
1124 std r28, VCPU_GPR(R28)(r9)
1125 std r29, VCPU_GPR(R29)(r9)
1126 std r30, VCPU_GPR(R30)(r9)
1127 std r31, VCPU_GPR(R31)(r9)
1130 mfspr r3, SPRN_SPRG0
1131 mfspr r4, SPRN_SPRG1
1132 mfspr r5, SPRN_SPRG2
1133 mfspr r6, SPRN_SPRG3
1134 std r3, VCPU_SPRG0(r9)
1135 std r4, VCPU_SPRG1(r9)
1136 std r5, VCPU_SPRG2(r9)
1137 std r6, VCPU_SPRG3(r9)
1143 /* Increment yield count if they have a VPA */
1144 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1147 lwz r3, LPPACA_YIELDCOUNT(r8)
1149 stw r3, LPPACA_YIELDCOUNT(r8)
1151 stb r3, VCPU_VPA_DIRTY(r9)
1153 /* Save PMU registers if requested */
1154 /* r8 and cr0.eq are live here */
1156 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1157 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1158 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1159 mfspr r6, SPRN_MMCRA
1161 /* On P7, clear MMCRA in order to disable SDAR updates */
1163 mtspr SPRN_MMCRA, r7
1164 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1166 beq 21f /* if no VPA, save PMU stuff anyway */
1167 lbz r7, LPPACA_PMCINUSE(r8)
1168 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1170 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1172 21: mfspr r5, SPRN_MMCR1
1175 std r4, VCPU_MMCR(r9)
1176 std r5, VCPU_MMCR + 8(r9)
1177 std r6, VCPU_MMCR + 16(r9)
1178 std r7, VCPU_SIAR(r9)
1179 std r8, VCPU_SDAR(r9)
1187 mfspr r10, SPRN_PMC7
1188 mfspr r11, SPRN_PMC8
1189 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1190 stw r3, VCPU_PMC(r9)
1191 stw r4, VCPU_PMC + 4(r9)
1192 stw r5, VCPU_PMC + 8(r9)
1193 stw r6, VCPU_PMC + 12(r9)
1194 stw r7, VCPU_PMC + 16(r9)
1195 stw r8, VCPU_PMC + 20(r9)
1197 stw r10, VCPU_PMC + 24(r9)
1198 stw r11, VCPU_PMC + 28(r9)
1199 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1202 /* Secondary threads go off to take a nap on POWER7 */
1204 lwz r0,VCPU_PTID(r9)
1207 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1209 /* Restore host DABR and DABRX */
1210 ld r5,HSTATE_DABR(r13)
1216 ld r3,PACA_SPRG3(r13)
1220 * Reload DEC. HDEC interrupts were disabled when
1221 * we reloaded the host's LPCR value.
1223 ld r3, HSTATE_DECEXP(r13)
1228 /* Reload the host's PMU registers */
1229 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
1230 lbz r4, LPPACA_PMCINUSE(r3)
1232 beq 23f /* skip if not */
1233 lwz r3, HSTATE_PMC(r13)
1234 lwz r4, HSTATE_PMC + 4(r13)
1235 lwz r5, HSTATE_PMC + 8(r13)
1236 lwz r6, HSTATE_PMC + 12(r13)
1237 lwz r8, HSTATE_PMC + 16(r13)
1238 lwz r9, HSTATE_PMC + 20(r13)
1240 lwz r10, HSTATE_PMC + 24(r13)
1241 lwz r11, HSTATE_PMC + 28(r13)
1242 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1250 mtspr SPRN_PMC7, r10
1251 mtspr SPRN_PMC8, r11
1252 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1253 ld r3, HSTATE_MMCR(r13)
1254 ld r4, HSTATE_MMCR + 8(r13)
1255 ld r5, HSTATE_MMCR + 16(r13)
1256 mtspr SPRN_MMCR1, r4
1257 mtspr SPRN_MMCRA, r5
1258 mtspr SPRN_MMCR0, r3
1262 * For external and machine check interrupts, we need
1263 * to call the Linux handler to process the interrupt.
1264 * We do that by jumping to absolute address 0x500 for
1265 * external interrupts, or the machine_check_fwnmi label
1266 * for machine checks (since firmware might have patched
1267 * the vector area at 0x200). The [h]rfid at the end of the
1268 * handler will return to the book3s_hv_interrupts.S code.
1269 * For other interrupts we do the rfid to get back
1270 * to the book3s_hv_interrupts.S code here.
1272 ld r8, HSTATE_VMHANDLER(r13)
1273 ld r7, HSTATE_HOST_MSR(r13)
1275 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1276 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1279 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1281 /* RFI into the highmem handler, or branch to interrupt handler */
1285 mtmsrd r6, 1 /* Clear RI in MSR */
1288 beqa 0x500 /* external interrupt (PPC970) */
1289 beq cr1, 13f /* machine check */
1292 /* On POWER7, we have external interrupts set to use HSRR0/1 */
1293 11: mtspr SPRN_HSRR0, r8
1294 mtspr SPRN_HSRR1, r7
1297 13: b machine_check_fwnmi
1300 * Check whether an HDSI is an HPTE not found fault or something else.
1301 * If it is an HPTE not found fault that is due to the guest accessing
1302 * a page that they have mapped but which we have paged out, then
1303 * we continue on with the guest exit path. In all other cases,
1304 * reflect the HDSI to the guest as a DSI.
1308 mfspr r6, SPRN_HDSISR
1309 /* HPTE not found fault or protection fault? */
1310 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1311 beq 1f /* if not, send it to the guest */
1312 andi. r0, r11, MSR_DR /* data relocation enabled? */
1315 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1316 bne 1f /* if no SLB entry found */
1317 4: std r4, VCPU_FAULT_DAR(r9)
1318 stw r6, VCPU_FAULT_DSISR(r9)
1320 /* Search the hash table. */
1321 mr r3, r9 /* vcpu pointer */
1322 li r7, 1 /* data fault */
1323 bl .kvmppc_hpte_hv_fault
1324 ld r9, HSTATE_KVM_VCPU(r13)
1326 ld r11, VCPU_MSR(r9)
1327 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1328 cmpdi r3, 0 /* retry the instruction */
1330 cmpdi r3, -1 /* handle in kernel mode */
1332 cmpdi r3, -2 /* MMIO emulation; need instr word */
1335 /* Synthesize a DSI for the guest */
1336 ld r4, VCPU_FAULT_DAR(r9)
1338 1: mtspr SPRN_DAR, r4
1339 mtspr SPRN_DSISR, r6
1340 mtspr SPRN_SRR0, r10
1341 mtspr SPRN_SRR1, r11
1342 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1343 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1345 fast_interrupt_c_return:
1346 6: ld r7, VCPU_CTR(r9)
1347 lwz r8, VCPU_XER(r9)
1353 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1354 ld r5, KVM_VRMA_SLB_V(r5)
1357 /* If this is for emulated MMIO, load the instruction word */
1358 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1360 /* Set guest mode to 'jump over instruction' so if lwz faults
1361 * we'll just continue at the next IP. */
1362 li r0, KVM_GUEST_MODE_SKIP
1363 stb r0, HSTATE_IN_GUEST(r13)
1365 /* Do the access with MSR:DR enabled */
1367 ori r4, r3, MSR_DR /* Enable paging for data */
1372 /* Store the result */
1373 stw r8, VCPU_LAST_INST(r9)
1375 /* Unset guest mode. */
1376 li r0, KVM_GUEST_MODE_NONE
1377 stb r0, HSTATE_IN_GUEST(r13)
1381 * Similarly for an HISI, reflect it to the guest as an ISI unless
1382 * it is an HPTE not found fault for a page that we have paged out.
1385 andis. r0, r11, SRR1_ISI_NOPT@h
1387 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1390 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1391 bne 1f /* if no SLB entry found */
1393 /* Search the hash table. */
1394 mr r3, r9 /* vcpu pointer */
1397 li r7, 0 /* instruction fault */
1398 bl .kvmppc_hpte_hv_fault
1399 ld r9, HSTATE_KVM_VCPU(r13)
1401 ld r11, VCPU_MSR(r9)
1402 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1403 cmpdi r3, 0 /* retry the instruction */
1404 beq fast_interrupt_c_return
1405 cmpdi r3, -1 /* handle in kernel mode */
1408 /* Synthesize an ISI for the guest */
1410 1: mtspr SPRN_SRR0, r10
1411 mtspr SPRN_SRR1, r11
1412 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1413 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1415 b fast_interrupt_c_return
1417 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1418 ld r5, KVM_VRMA_SLB_V(r6)
1422 * Try to handle an hcall in real mode.
1423 * Returns to the guest if we handle it, or continues on up to
1424 * the kernel if we can't (i.e. if we don't have a handler for
1425 * it, or if the handler returns H_TOO_HARD).
1427 .globl hcall_try_real_mode
1428 hcall_try_real_mode:
1429 ld r3,VCPU_GPR(R3)(r9)
1433 cmpldi r3,hcall_real_table_end - hcall_real_table
1435 LOAD_REG_ADDR(r4, hcall_real_table)
1441 mr r3,r9 /* get vcpu pointer */
1442 ld r4,VCPU_GPR(R4)(r9)
1445 beq hcall_real_fallback
1446 ld r4,HSTATE_KVM_VCPU(r13)
1447 std r3,VCPU_GPR(R3)(r4)
1452 /* We've attempted a real mode hcall, but it's punted it back
1453 * to userspace. We need to restore some clobbered volatiles
1454 * before resuming the pass-it-to-qemu path */
1455 hcall_real_fallback:
1456 li r12,BOOK3S_INTERRUPT_SYSCALL
1457 ld r9, HSTATE_KVM_VCPU(r13)
1461 .globl hcall_real_table
1463 .long 0 /* 0 - unused */
1464 .long .kvmppc_h_remove - hcall_real_table
1465 .long .kvmppc_h_enter - hcall_real_table
1466 .long .kvmppc_h_read - hcall_real_table
1467 .long 0 /* 0x10 - H_CLEAR_MOD */
1468 .long 0 /* 0x14 - H_CLEAR_REF */
1469 .long .kvmppc_h_protect - hcall_real_table
1470 .long 0 /* 0x1c - H_GET_TCE */
1471 .long .kvmppc_h_put_tce - hcall_real_table
1472 .long 0 /* 0x24 - H_SET_SPRG0 */
1473 .long .kvmppc_h_set_dabr - hcall_real_table
1488 #ifdef CONFIG_KVM_XICS
1489 .long .kvmppc_rm_h_eoi - hcall_real_table
1490 .long .kvmppc_rm_h_cppr - hcall_real_table
1491 .long .kvmppc_rm_h_ipi - hcall_real_table
1492 .long 0 /* 0x70 - H_IPOLL */
1493 .long .kvmppc_rm_h_xirr - hcall_real_table
1495 .long 0 /* 0x64 - H_EOI */
1496 .long 0 /* 0x68 - H_CPPR */
1497 .long 0 /* 0x6c - H_IPI */
1498 .long 0 /* 0x70 - H_IPOLL */
1499 .long 0 /* 0x74 - H_XIRR */
1527 .long .kvmppc_h_cede - hcall_real_table
1544 .long .kvmppc_h_bulk_remove - hcall_real_table
1545 hcall_real_table_end:
1551 _GLOBAL(kvmppc_h_set_dabr)
1552 std r4,VCPU_DABR(r3)
1553 /* Work around P7 bug where DABR can get corrupted on mtspr */
1554 1: mtspr SPRN_DABR,r4
1562 _GLOBAL(kvmppc_h_cede)
1564 std r11,VCPU_MSR(r3)
1566 stb r0,VCPU_CEDED(r3)
1567 sync /* order setting ceded vs. testing prodded */
1568 lbz r5,VCPU_PRODDED(r3)
1570 bne kvm_cede_prodded
1571 li r0,0 /* set trap to 0 to say hcall is handled */
1572 stw r0,VCPU_TRAP(r3)
1574 std r0,VCPU_GPR(R3)(r3)
1576 b kvm_cede_exit /* just send it up to host on 970 */
1577 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1580 * Set our bit in the bitmask of napping threads unless all the
1581 * other threads are already napping, in which case we send this
1584 ld r5,HSTATE_KVM_VCORE(r13)
1585 lwz r6,VCPU_PTID(r3)
1586 lwz r8,VCORE_ENTRY_EXIT(r5)
1590 addi r6,r5,VCORE_NAPPING_THREADS
1599 stb r0,HSTATE_NAPPING(r13)
1600 /* order napping_threads update vs testing entry_exit_count */
1603 lwz r7,VCORE_ENTRY_EXIT(r5)
1605 bge 33f /* another thread already exiting */
1608 * Although not specifically required by the architecture, POWER7
1609 * preserves the following registers in nap mode, even if an SMT mode
1610 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
1611 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
1613 /* Save non-volatile GPRs */
1614 std r14, VCPU_GPR(R14)(r3)
1615 std r15, VCPU_GPR(R15)(r3)
1616 std r16, VCPU_GPR(R16)(r3)
1617 std r17, VCPU_GPR(R17)(r3)
1618 std r18, VCPU_GPR(R18)(r3)
1619 std r19, VCPU_GPR(R19)(r3)
1620 std r20, VCPU_GPR(R20)(r3)
1621 std r21, VCPU_GPR(R21)(r3)
1622 std r22, VCPU_GPR(R22)(r3)
1623 std r23, VCPU_GPR(R23)(r3)
1624 std r24, VCPU_GPR(R24)(r3)
1625 std r25, VCPU_GPR(R25)(r3)
1626 std r26, VCPU_GPR(R26)(r3)
1627 std r27, VCPU_GPR(R27)(r3)
1628 std r28, VCPU_GPR(R28)(r3)
1629 std r29, VCPU_GPR(R29)(r3)
1630 std r30, VCPU_GPR(R30)(r3)
1631 std r31, VCPU_GPR(R31)(r3)
1637 * Take a nap until a decrementer or external interrupt occurs,
1638 * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR
1641 stb r0,HSTATE_HWTHREAD_REQ(r13)
1643 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
1647 std r0, HSTATE_SCRATCH0(r13)
1649 ld r0, HSTATE_SCRATCH0(r13)
1656 /* get vcpu pointer */
1657 ld r4, HSTATE_KVM_VCPU(r13)
1659 /* Woken by external or decrementer interrupt */
1660 ld r1, HSTATE_HOST_R1(r13)
1662 /* load up FP state */
1666 ld r14, VCPU_GPR(R14)(r4)
1667 ld r15, VCPU_GPR(R15)(r4)
1668 ld r16, VCPU_GPR(R16)(r4)
1669 ld r17, VCPU_GPR(R17)(r4)
1670 ld r18, VCPU_GPR(R18)(r4)
1671 ld r19, VCPU_GPR(R19)(r4)
1672 ld r20, VCPU_GPR(R20)(r4)
1673 ld r21, VCPU_GPR(R21)(r4)
1674 ld r22, VCPU_GPR(R22)(r4)
1675 ld r23, VCPU_GPR(R23)(r4)
1676 ld r24, VCPU_GPR(R24)(r4)
1677 ld r25, VCPU_GPR(R25)(r4)
1678 ld r26, VCPU_GPR(R26)(r4)
1679 ld r27, VCPU_GPR(R27)(r4)
1680 ld r28, VCPU_GPR(R28)(r4)
1681 ld r29, VCPU_GPR(R29)(r4)
1682 ld r30, VCPU_GPR(R30)(r4)
1683 ld r31, VCPU_GPR(R31)(r4)
1685 /* clear our bit in vcore->napping_threads */
1686 33: ld r5,HSTATE_KVM_VCORE(r13)
1687 lwz r3,VCPU_PTID(r4)
1690 addi r6,r5,VCORE_NAPPING_THREADS
1696 stb r0,HSTATE_NAPPING(r13)
1698 /* Check the wake reason in SRR1 to see why we got here */
1700 rlwinm r3, r3, 44-31, 0x7 /* extract wake reason field */
1701 cmpwi r3, 4 /* was it an external interrupt? */
1702 li r12, BOOK3S_INTERRUPT_EXTERNAL
1705 ld r11, VCPU_MSR(r9)
1706 beq do_ext_interrupt /* if so */
1708 /* see if any other thread is already exiting */
1709 lwz r0,VCORE_ENTRY_EXIT(r5)
1711 blt kvmppc_cede_reentry /* if not go back to guest */
1713 /* some threads are exiting, so go to the guest exit path */
1714 b hcall_real_fallback
1716 /* cede when already previously prodded case */
1719 stb r0,VCPU_PRODDED(r3)
1720 sync /* order testing prodded vs. clearing ceded */
1721 stb r0,VCPU_CEDED(r3)
1725 /* we've ceded but we want to give control to the host */
1727 b hcall_real_fallback
1729 /* Try to handle a machine check in real mode */
1730 machine_check_realmode:
1731 mr r3, r9 /* get vcpu pointer */
1732 bl .kvmppc_realmode_machine_check
1734 cmpdi r3, 0 /* continue exiting from guest? */
1735 ld r9, HSTATE_KVM_VCPU(r13)
1736 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1738 /* If not, deliver a machine check. SRR0/1 are already set */
1739 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
1740 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1742 b fast_interrupt_c_return
1745 ld r5,HSTATE_KVM_VCORE(r13)
1747 13: lbz r3,VCORE_IN_GUEST(r5)
1751 ld r11,PACA_SLBSHADOWPTR(r13)
1753 .rept SLB_NUM_BOLTED
1754 ld r5,SLBSHADOW_SAVEAREA(r11)
1755 ld r6,SLBSHADOW_SAVEAREA+8(r11)
1756 andis. r7,r5,SLB_ESID_V@h
1763 /* Clear our vcpu pointer so we don't come back in early */
1765 std r0, HSTATE_KVM_VCPU(r13)
1767 /* Clear any pending IPI - assume we're a secondary thread */
1768 ld r5, HSTATE_XICS_PHYS(r13)
1770 lwzcix r3, r5, r7 /* ack any pending interrupt */
1771 rlwinm. r0, r3, 0, 0xffffff /* any pending? */
1776 stbcix r0, r5, r6 /* clear the IPI */
1777 stwcix r3, r5, r7 /* EOI it */
1780 /* increment the nap count and then go to nap mode */
1781 ld r4, HSTATE_KVM_VCORE(r13)
1782 addi r4, r4, VCORE_NAP_COUNT
1783 lwsync /* make previous updates visible */
1790 li r0, KVM_HWTHREAD_IN_NAP
1791 stb r0, HSTATE_HWTHREAD_STATE(r13)
1795 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
1798 std r0, HSTATE_SCRATCH0(r13)
1800 ld r0, HSTATE_SCRATCH0(r13)
1807 * Save away FP, VMX and VSX registers.
1810 _GLOBAL(kvmppc_save_fp)
1813 #ifdef CONFIG_ALTIVEC
1815 oris r8,r8,MSR_VEC@h
1816 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1820 oris r8,r8,MSR_VSX@h
1821 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1829 li r6,reg*16+VCPU_VSRS
1837 stfd reg,reg*8+VCPU_FPRS(r3)
1841 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1844 stfd fr0,VCPU_FPSCR(r3)
1846 #ifdef CONFIG_ALTIVEC
1850 li r6,reg*16+VCPU_VRS
1857 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1859 mfspr r6,SPRN_VRSAVE
1860 stw r6,VCPU_VRSAVE(r3)
1866 * Load up FP, VMX and VSX registers
1869 .globl kvmppc_load_fp
1873 #ifdef CONFIG_ALTIVEC
1875 oris r8,r8,MSR_VEC@h
1876 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1880 oris r8,r8,MSR_VSX@h
1881 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1885 lfd fr0,VCPU_FPSCR(r4)
1891 li r7,reg*16+VCPU_VSRS
1899 lfd reg,reg*8+VCPU_FPRS(r4)
1903 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1906 #ifdef CONFIG_ALTIVEC
1913 li r7,reg*16+VCPU_VRS
1917 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1919 lwz r7,VCPU_VRSAVE(r4)
1920 mtspr SPRN_VRSAVE,r7