2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
31 /*****************************************************************************
33 * Real Mode handlers that need to be in the linear mapping *
35 ****************************************************************************/
37 .globl kvmppc_skip_interrupt
38 kvmppc_skip_interrupt:
46 .globl kvmppc_skip_Hinterrupt
47 kvmppc_skip_Hinterrupt:
56 * Call kvmppc_hv_entry in real mode.
57 * Must be called with interrupts hard-disabled.
61 * LR = return address to continue at after eventually re-enabling MMU
63 _GLOBAL(kvmppc_hv_entry_trampoline)
65 LOAD_REG_ADDR(r5, kvmppc_hv_entry)
70 mtmsrd r0,1 /* clear RI in MSR */
75 /******************************************************************************
79 *****************************************************************************/
83 #define XICS_IPI 2 /* interrupt source # for IPIs */
86 * We come in here when wakened from nap mode on a secondary hw thread.
87 * Relocation is off and most register values are lost.
88 * r13 points to the PACA.
90 .globl kvm_start_guest
92 ld r1,PACAEMERGSP(r13)
93 subi r1,r1,STACK_FRAME_OVERHEAD
96 li r0,KVM_HWTHREAD_IN_KVM
97 stb r0,HSTATE_HWTHREAD_STATE(r13)
99 /* NV GPR values from power7_idle() will no longer be valid */
101 stb r0,PACA_NAPSTATELOST(r13)
103 /* get vcpu pointer, NULL if we have no vcpu to run */
104 ld r4,HSTATE_KVM_VCPU(r13)
107 /* Check the wake reason in SRR1 to see why we got here */
109 rlwinm r3,r3,44-31,0x7 /* extract wake reason field */
110 cmpwi r3,4 /* was it an external interrupt? */
114 * External interrupt - for now assume it is an IPI, since we
115 * should never get any other interrupts sent to offline threads.
116 * Only do this for secondary threads.
122 25: ld r5,HSTATE_XICS_PHYS(r13)
126 lwzcix r8,r5,r7 /* get and ack the interrupt */
128 clrldi. r9,r8,40 /* get interrupt source ID. */
129 beq 27f /* none there? */
132 stbcix r0,r5,r6 /* clear IPI */
133 26: stwcix r8,r5,r7 /* EOI the interrupt */
135 27: /* XXX should handle hypervisor maintenance interrupts etc. here */
137 /* reload vcpu pointer after clearing the IPI */
138 ld r4,HSTATE_KVM_VCPU(r13)
140 /* if we have no vcpu to run, go back to sleep */
143 /* were we napping due to cede? */
144 lbz r0,HSTATE_NAPPING(r13)
148 .global kvmppc_hv_entry
157 * all other volatile GPRS = free
160 std r0, HSTATE_VMHANDLER(r13)
162 /* Set partition DABR */
163 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
170 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
172 /* Load guest PMU registers */
173 /* R4 is live here (vcpu pointer) */
175 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
176 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
178 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
179 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
180 lwz r6, VCPU_PMC + 8(r4)
181 lwz r7, VCPU_PMC + 12(r4)
182 lwz r8, VCPU_PMC + 16(r4)
183 lwz r9, VCPU_PMC + 20(r4)
185 lwz r10, VCPU_PMC + 24(r4)
186 lwz r11, VCPU_PMC + 28(r4)
187 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
197 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
199 ld r5, VCPU_MMCR + 8(r4)
200 ld r6, VCPU_MMCR + 16(r4)
206 /* Load up FP, VMX and VSX registers */
209 ld r14, VCPU_GPR(R14)(r4)
210 ld r15, VCPU_GPR(R15)(r4)
211 ld r16, VCPU_GPR(R16)(r4)
212 ld r17, VCPU_GPR(R17)(r4)
213 ld r18, VCPU_GPR(R18)(r4)
214 ld r19, VCPU_GPR(R19)(r4)
215 ld r20, VCPU_GPR(R20)(r4)
216 ld r21, VCPU_GPR(R21)(r4)
217 ld r22, VCPU_GPR(R22)(r4)
218 ld r23, VCPU_GPR(R23)(r4)
219 ld r24, VCPU_GPR(R24)(r4)
220 ld r25, VCPU_GPR(R25)(r4)
221 ld r26, VCPU_GPR(R26)(r4)
222 ld r27, VCPU_GPR(R27)(r4)
223 ld r28, VCPU_GPR(R28)(r4)
224 ld r29, VCPU_GPR(R29)(r4)
225 ld r30, VCPU_GPR(R30)(r4)
226 ld r31, VCPU_GPR(R31)(r4)
229 /* Switch DSCR to guest value */
232 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
235 * Set the decrementer to the guest decrementer.
237 ld r8,VCPU_DEC_EXPIRES(r4)
243 ld r5, VCPU_SPRG0(r4)
244 ld r6, VCPU_SPRG1(r4)
245 ld r7, VCPU_SPRG2(r4)
246 ld r8, VCPU_SPRG3(r4)
252 /* Save R1 in the PACA */
253 std r1, HSTATE_HOST_R1(r13)
255 /* Increment yield count if they have a VPA */
259 lwz r5, LPPACA_YIELDCOUNT(r3)
261 stw r5, LPPACA_YIELDCOUNT(r3)
263 /* Load up DAR and DSISR */
265 lwz r6, VCPU_DSISR(r4)
270 /* Restore AMR and UAMOR, set AMOR to all 1s */
277 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
287 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
289 * POWER7 host -> guest partition switch code.
290 * We don't have to lock against concurrent tlbies,
291 * but we do have to coordinate across hardware threads.
293 /* Increment entry count iff exit count is zero. */
294 ld r5,HSTATE_KVM_VCORE(r13)
295 addi r9,r5,VCORE_ENTRY_EXIT
297 cmpwi r3,0x100 /* any threads starting to exit? */
298 bge secondary_too_late /* if so we're too late to the party */
303 /* Primary thread switches to guest partition. */
304 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
310 li r0,LPID_RSVD /* switch to reserved LPID */
313 mtspr SPRN_SDR1,r6 /* switch to partition page table */
317 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
320 /* Secondary threads wait for primary to have done partition switch */
321 20: lbz r0,VCORE_IN_GUEST(r5)
325 /* Set LPCR and RMOR. */
326 10: ld r8,KVM_LPCR(r9)
332 /* Check if HDEC expires soon */
335 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
340 * Invalidate the TLB if we could possibly have stale TLB
341 * entries for this partition on this core due to the use
343 * XXX maybe only need this on primary thread?
345 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
346 lwz r5,VCPU_VCPUID(r4)
347 lhz r6,PACAPACAINDEX(r13)
348 rldimi r6,r5,0,62 /* XXX map as if threads 1:1 p:v */
349 lhz r8,VCPU_LAST_CPU(r4)
350 sldi r7,r6,1 /* see if this is the same vcpu */
351 add r7,r7,r9 /* as last ran on this pcpu */
352 lhz r0,KVM_LAST_VCPU(r7)
353 cmpw r6,r8 /* on the same cpu core as last time? */
355 cmpw r0,r5 /* same vcpu as this core last ran? */
357 3: sth r6,VCPU_LAST_CPU(r4) /* if not, invalidate partition TLB */
358 sth r5,KVM_LAST_VCPU(r7)
361 li r7,0x800 /* IS field = 0b10 */
369 /* Save purr/spurr */
372 std r5,HSTATE_PURR(r13)
373 std r6,HSTATE_SPURR(r13)
381 * PPC970 host -> guest partition switch code.
382 * We have to lock against concurrent tlbies,
383 * using native_tlbie_lock to lock against host tlbies
384 * and kvm->arch.tlbie_lock to lock against guest tlbies.
385 * We also have to invalidate the TLB since its
386 * entries aren't tagged with the LPID.
388 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
390 /* first take native_tlbie_lock */
393 .tc native_tlbie_lock[TC],native_tlbie_lock
395 ld r3,toc_tlbie_lock@toc(2)
396 lwz r8,PACA_LOCK_TOKEN(r13)
404 ld r7,KVM_LPCR(r9) /* use kvm->arch.lpcr to store HID4 */
406 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
410 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
413 stw r0,0(r3) /* drop native_tlbie_lock */
415 /* invalidate the whole TLB */
424 /* Take the guest's tlbie_lock */
425 addi r3,r9,KVM_TLBIE_LOCK
433 mtspr SPRN_SDR1,r6 /* switch to partition page table */
435 /* Set up HID4 with the guest's LPID etc. */
440 /* drop the guest's tlbie_lock */
444 /* Check if HDEC expires soon */
447 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
451 /* Enable HDEC interrupts */
454 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
464 /* Load up guest SLB entries */
465 31: lwz r5,VCPU_SLB_MAX(r4)
470 1: ld r8,VCPU_SLB_E(r6)
473 addi r6,r6,VCPU_SLB_SIZE
477 /* Restore state of CTRL run bit; assume 1 on entry */
491 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
495 ld r11, VCPU_MSR(r4) /* r11 = vcpu->arch.msr & ~MSR_HV */
497 rldicl r11, r11, 63 - MSR_HV_LG, 1
498 rotldi r11, r11, 1 + MSR_HV_LG
501 /* Check if we can deliver an external or decrementer interrupt now */
502 ld r0,VCPU_PENDING_EXC(r4)
503 li r8,(1 << BOOK3S_IRQPRIO_EXTERNAL)
504 oris r8,r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
514 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
516 li r0,BOOK3S_INTERRUPT_EXTERNAL
520 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
526 li r0,BOOK3S_INTERRUPT_DECREMENTER
529 /* Move SRR0 and SRR1 into the respective regs */
530 5: mtspr SPRN_SRR0, r6
533 stb r0,VCPU_CEDED(r4) /* cancel cede */
539 /* Activate guest mode, so faults get handled by KVM */
540 li r9, KVM_GUEST_MODE_GUEST
541 stb r9, HSTATE_IN_GUEST(r13)
550 ld r0, VCPU_GPR(R0)(r4)
551 ld r1, VCPU_GPR(R1)(r4)
552 ld r2, VCPU_GPR(R2)(r4)
553 ld r3, VCPU_GPR(R3)(r4)
554 ld r5, VCPU_GPR(R5)(r4)
555 ld r6, VCPU_GPR(R6)(r4)
556 ld r7, VCPU_GPR(R7)(r4)
557 ld r8, VCPU_GPR(R8)(r4)
558 ld r9, VCPU_GPR(R9)(r4)
559 ld r10, VCPU_GPR(R10)(r4)
560 ld r11, VCPU_GPR(R11)(r4)
561 ld r12, VCPU_GPR(R12)(r4)
562 ld r13, VCPU_GPR(R13)(r4)
564 ld r4, VCPU_GPR(R4)(r4)
569 /******************************************************************************
573 *****************************************************************************/
576 * We come here from the first-level interrupt handlers.
578 .globl kvmppc_interrupt
582 * R12 = interrupt vector
584 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
585 * guest R13 saved in SPRN_SCRATCH0
587 /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */
588 std r9, HSTATE_HOST_R2(r13)
589 ld r9, HSTATE_KVM_VCPU(r13)
593 std r0, VCPU_GPR(R0)(r9)
594 std r1, VCPU_GPR(R1)(r9)
595 std r2, VCPU_GPR(R2)(r9)
596 std r3, VCPU_GPR(R3)(r9)
597 std r4, VCPU_GPR(R4)(r9)
598 std r5, VCPU_GPR(R5)(r9)
599 std r6, VCPU_GPR(R6)(r9)
600 std r7, VCPU_GPR(R7)(r9)
601 std r8, VCPU_GPR(R8)(r9)
602 ld r0, HSTATE_HOST_R2(r13)
603 std r0, VCPU_GPR(R9)(r9)
604 std r10, VCPU_GPR(R10)(r9)
605 std r11, VCPU_GPR(R11)(r9)
606 ld r3, HSTATE_SCRATCH0(r13)
607 lwz r4, HSTATE_SCRATCH1(r13)
608 std r3, VCPU_GPR(R12)(r9)
611 /* Restore R1/R2 so we can handle faults */
612 ld r1, HSTATE_HOST_R1(r13)
617 std r10, VCPU_SRR0(r9)
618 std r11, VCPU_SRR1(r9)
619 andi. r0, r12, 2 /* need to read HSRR0/1? */
621 mfspr r10, SPRN_HSRR0
622 mfspr r11, SPRN_HSRR1
624 1: std r10, VCPU_PC(r9)
625 std r11, VCPU_MSR(r9)
629 std r3, VCPU_GPR(R13)(r9)
632 /* Unset guest mode */
633 li r0, KVM_GUEST_MODE_NONE
634 stb r0, HSTATE_IN_GUEST(r13)
636 stw r12,VCPU_TRAP(r9)
638 /* Save HEIR (HV emulation assist reg) in last_inst
639 if this is an HEI (HV emulation interrupt, e40) */
640 li r3,KVM_INST_FETCH_FAILED
642 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
645 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
646 11: stw r3,VCPU_LAST_INST(r9)
648 /* these are volatile across C function calls */
655 /* If this is a page table miss then see if it's theirs or ours */
656 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
658 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
660 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
662 /* See if this is a leftover HDEC interrupt */
663 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
669 /* See if this is an hcall we can handle in real mode */
670 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
671 beq hcall_try_real_mode
673 /* Check for mediated interrupts (could be done earlier really ...) */
675 cmpwi r12,BOOK3S_INTERRUPT_EXTERNAL
681 bne bounce_ext_interrupt
683 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
686 hcall_real_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
692 std r5,VCPU_DEC_EXPIRES(r9)
694 /* Save more register state */
698 stw r7, VCPU_DSISR(r9)
700 /* don't overwrite fault_dar/fault_dsisr if HDSI */
701 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
703 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
704 std r6, VCPU_FAULT_DAR(r9)
705 stw r7, VCPU_FAULT_DSISR(r9)
707 /* Save guest CTRL register, set runlatch to 1 */
708 6: mfspr r6,SPRN_CTRLF
715 /* Read the guest SLB and save it away */
716 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
722 andis. r0,r8,SLB_ESID_V@h
724 add r8,r8,r6 /* put index in */
726 std r8,VCPU_SLB_E(r7)
727 std r3,VCPU_SLB_V(r7)
728 addi r7,r7,VCPU_SLB_SIZE
732 stw r5,VCPU_SLB_MAX(r9)
735 * Save the guest PURR/SPURR
743 std r6,VCPU_SPURR(r9)
748 * Restore host PURR/SPURR and add guest times
749 * so that the time in the guest gets accounted.
751 ld r3,HSTATE_PURR(r13)
752 ld r4,HSTATE_SPURR(r13)
757 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
765 hdec_soon: /* r9 = vcpu, r12 = trap, r13 = paca */
768 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
770 * POWER7 guest -> host partition switch code.
771 * We don't have to lock against tlbies but we do
772 * have to coordinate the hardware threads.
774 /* Increment the threads-exiting-guest count in the 0xff00
775 bits of vcore->entry_exit_count */
777 ld r5,HSTATE_KVM_VCORE(r13)
778 addi r6,r5,VCORE_ENTRY_EXIT
786 * At this point we have an interrupt that we have to pass
787 * up to the kernel or qemu; we can't handle it in real mode.
788 * Thus we have to do a partition switch, so we have to
789 * collect the other threads, if we are the first thread
790 * to take an interrupt. To do this, we set the HDEC to 0,
791 * which causes an HDEC interrupt in all threads within 2ns
792 * because the HDEC register is shared between all 4 threads.
793 * However, we don't need to bother if this is an HDEC
794 * interrupt, since the other threads will already be on their
795 * way here in that case.
797 cmpwi r3,0x100 /* Are we the first here? */
799 cmpwi r3,1 /* Are any other threads in the guest? */
801 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
807 * Send an IPI to any napping threads, since an HDEC interrupt
808 * doesn't wake CPUs up from nap.
810 lwz r3,VCORE_NAPPING_THREADS(r5)
814 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
816 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
820 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
823 stbcix r0,r7,r8 /* trigger the IPI */
828 /* Secondary threads wait for primary to do partition switch */
829 43: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
830 ld r5,HSTATE_KVM_VCORE(r13)
835 13: lbz r3,VCORE_IN_GUEST(r5)
841 /* Primary thread waits for all the secondaries to exit guest */
842 15: lwz r3,VCORE_ENTRY_EXIT(r5)
849 /* Primary thread switches back to host partition */
850 ld r6,KVM_HOST_SDR1(r4)
851 lwz r7,KVM_HOST_LPID(r4)
852 li r8,LPID_RSVD /* switch to reserved LPID */
855 mtspr SPRN_SDR1,r6 /* switch to partition page table */
859 stb r0,VCORE_IN_GUEST(r5)
860 lis r8,0x7fff /* MAX_INT@h */
863 16: ld r8,KVM_HOST_LPCR(r4)
869 * PPC970 guest -> host partition switch code.
870 * We have to lock against concurrent tlbies, and
871 * we have to flush the whole TLB.
873 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
875 /* Take the guest's tlbie_lock */
876 lwz r8,PACA_LOCK_TOKEN(r13)
877 addi r3,r4,KVM_TLBIE_LOCK
885 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
887 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
891 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
894 stw r0,0(r3) /* drop guest tlbie_lock */
896 /* invalidate the whole TLB */
905 /* take native_tlbie_lock */
906 ld r3,toc_tlbie_lock@toc(2)
914 ld r6,KVM_HOST_SDR1(r4)
915 mtspr SPRN_SDR1,r6 /* switch to host page table */
917 /* Set up host HID4 value */
922 stw r0,0(r3) /* drop native_tlbie_lock */
924 lis r8,0x7fff /* MAX_INT@h */
927 /* Disable HDEC interrupts */
930 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
940 /* load host SLB entries */
941 33: ld r8,PACA_SLBSHADOWPTR(r13)
944 ld r5,SLBSHADOW_SAVEAREA(r8)
945 ld r6,SLBSHADOW_SAVEAREA+8(r8)
946 andis. r7,r5,SLB_ESID_V@h
952 /* Save and reset AMR and UAMOR before turning on the MMU */
957 std r6,VCPU_UAMOR(r9)
960 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
962 /* Switch DSCR back to host value */
965 ld r7, HSTATE_DSCR(r13)
966 std r8, VCPU_DSCR(r7)
968 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
970 /* Save non-volatile GPRs */
971 std r14, VCPU_GPR(R14)(r9)
972 std r15, VCPU_GPR(R15)(r9)
973 std r16, VCPU_GPR(R16)(r9)
974 std r17, VCPU_GPR(R17)(r9)
975 std r18, VCPU_GPR(R18)(r9)
976 std r19, VCPU_GPR(R19)(r9)
977 std r20, VCPU_GPR(R20)(r9)
978 std r21, VCPU_GPR(R21)(r9)
979 std r22, VCPU_GPR(R22)(r9)
980 std r23, VCPU_GPR(R23)(r9)
981 std r24, VCPU_GPR(R24)(r9)
982 std r25, VCPU_GPR(R25)(r9)
983 std r26, VCPU_GPR(R26)(r9)
984 std r27, VCPU_GPR(R27)(r9)
985 std r28, VCPU_GPR(R28)(r9)
986 std r29, VCPU_GPR(R29)(r9)
987 std r30, VCPU_GPR(R30)(r9)
988 std r31, VCPU_GPR(R31)(r9)
995 std r3, VCPU_SPRG0(r9)
996 std r4, VCPU_SPRG1(r9)
997 std r5, VCPU_SPRG2(r9)
998 std r6, VCPU_SPRG3(r9)
1004 /* Increment yield count if they have a VPA */
1005 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1008 lwz r3, LPPACA_YIELDCOUNT(r8)
1010 stw r3, LPPACA_YIELDCOUNT(r8)
1012 /* Save PMU registers if requested */
1013 /* r8 and cr0.eq are live here */
1015 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1016 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1017 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1018 mfspr r6, SPRN_MMCRA
1020 /* On P7, clear MMCRA in order to disable SDAR updates */
1022 mtspr SPRN_MMCRA, r7
1023 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1025 beq 21f /* if no VPA, save PMU stuff anyway */
1026 lbz r7, LPPACA_PMCINUSE(r8)
1027 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1029 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1031 21: mfspr r5, SPRN_MMCR1
1032 std r4, VCPU_MMCR(r9)
1033 std r5, VCPU_MMCR + 8(r9)
1034 std r6, VCPU_MMCR + 16(r9)
1042 mfspr r10, SPRN_PMC7
1043 mfspr r11, SPRN_PMC8
1044 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1045 stw r3, VCPU_PMC(r9)
1046 stw r4, VCPU_PMC + 4(r9)
1047 stw r5, VCPU_PMC + 8(r9)
1048 stw r6, VCPU_PMC + 12(r9)
1049 stw r7, VCPU_PMC + 16(r9)
1050 stw r8, VCPU_PMC + 20(r9)
1052 stw r10, VCPU_PMC + 24(r9)
1053 stw r11, VCPU_PMC + 28(r9)
1054 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1057 /* Secondary threads go off to take a nap on POWER7 */
1059 lwz r0,VCPU_PTID(r9)
1062 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1064 /* Restore host DABR and DABRX */
1065 ld r5,HSTATE_DABR(r13)
1071 ld r3,PACA_SPRG3(r13)
1075 * Reload DEC. HDEC interrupts were disabled when
1076 * we reloaded the host's LPCR value.
1078 ld r3, HSTATE_DECEXP(r13)
1083 /* Reload the host's PMU registers */
1084 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
1085 lbz r4, LPPACA_PMCINUSE(r3)
1087 beq 23f /* skip if not */
1088 lwz r3, HSTATE_PMC(r13)
1089 lwz r4, HSTATE_PMC + 4(r13)
1090 lwz r5, HSTATE_PMC + 8(r13)
1091 lwz r6, HSTATE_PMC + 12(r13)
1092 lwz r8, HSTATE_PMC + 16(r13)
1093 lwz r9, HSTATE_PMC + 20(r13)
1095 lwz r10, HSTATE_PMC + 24(r13)
1096 lwz r11, HSTATE_PMC + 28(r13)
1097 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1105 mtspr SPRN_PMC7, r10
1106 mtspr SPRN_PMC8, r11
1107 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1108 ld r3, HSTATE_MMCR(r13)
1109 ld r4, HSTATE_MMCR + 8(r13)
1110 ld r5, HSTATE_MMCR + 16(r13)
1111 mtspr SPRN_MMCR1, r4
1112 mtspr SPRN_MMCRA, r5
1113 mtspr SPRN_MMCR0, r3
1117 * For external and machine check interrupts, we need
1118 * to call the Linux handler to process the interrupt.
1119 * We do that by jumping to the interrupt vector address
1120 * which we have in r12. The [h]rfid at the end of the
1121 * handler will return to the book3s_hv_interrupts.S code.
1122 * For other interrupts we do the rfid to get back
1123 * to the book3s_interrupts.S code here.
1125 ld r8, HSTATE_VMHANDLER(r13)
1126 ld r7, HSTATE_HOST_MSR(r13)
1128 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1130 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1132 /* RFI into the highmem handler, or branch to interrupt handler */
1137 mtmsrd r6, 1 /* Clear RI in MSR */
1146 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1147 mtspr SPRN_HSRR0, r8
1148 mtspr SPRN_HSRR1, r7
1152 * Check whether an HDSI is an HPTE not found fault or something else.
1153 * If it is an HPTE not found fault that is due to the guest accessing
1154 * a page that they have mapped but which we have paged out, then
1155 * we continue on with the guest exit path. In all other cases,
1156 * reflect the HDSI to the guest as a DSI.
1160 mfspr r6, SPRN_HDSISR
1161 /* HPTE not found fault or protection fault? */
1162 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1163 beq 1f /* if not, send it to the guest */
1164 andi. r0, r11, MSR_DR /* data relocation enabled? */
1167 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1168 bne 1f /* if no SLB entry found */
1169 4: std r4, VCPU_FAULT_DAR(r9)
1170 stw r6, VCPU_FAULT_DSISR(r9)
1172 /* Search the hash table. */
1173 mr r3, r9 /* vcpu pointer */
1174 li r7, 1 /* data fault */
1175 bl .kvmppc_hpte_hv_fault
1176 ld r9, HSTATE_KVM_VCPU(r13)
1178 ld r11, VCPU_MSR(r9)
1179 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1180 cmpdi r3, 0 /* retry the instruction */
1182 cmpdi r3, -1 /* handle in kernel mode */
1184 cmpdi r3, -2 /* MMIO emulation; need instr word */
1187 /* Synthesize a DSI for the guest */
1188 ld r4, VCPU_FAULT_DAR(r9)
1190 1: mtspr SPRN_DAR, r4
1191 mtspr SPRN_DSISR, r6
1192 mtspr SPRN_SRR0, r10
1193 mtspr SPRN_SRR1, r11
1194 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1195 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1197 6: ld r7, VCPU_CTR(r9)
1198 lwz r8, VCPU_XER(r9)
1204 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1205 ld r5, KVM_VRMA_SLB_V(r5)
1208 /* If this is for emulated MMIO, load the instruction word */
1209 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1211 /* Set guest mode to 'jump over instruction' so if lwz faults
1212 * we'll just continue at the next IP. */
1213 li r0, KVM_GUEST_MODE_SKIP
1214 stb r0, HSTATE_IN_GUEST(r13)
1216 /* Do the access with MSR:DR enabled */
1218 ori r4, r3, MSR_DR /* Enable paging for data */
1223 /* Store the result */
1224 stw r8, VCPU_LAST_INST(r9)
1226 /* Unset guest mode. */
1227 li r0, KVM_GUEST_MODE_NONE
1228 stb r0, HSTATE_IN_GUEST(r13)
1232 * Similarly for an HISI, reflect it to the guest as an ISI unless
1233 * it is an HPTE not found fault for a page that we have paged out.
1236 andis. r0, r11, SRR1_ISI_NOPT@h
1238 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1241 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1242 bne 1f /* if no SLB entry found */
1244 /* Search the hash table. */
1245 mr r3, r9 /* vcpu pointer */
1248 li r7, 0 /* instruction fault */
1249 bl .kvmppc_hpte_hv_fault
1250 ld r9, HSTATE_KVM_VCPU(r13)
1252 ld r11, VCPU_MSR(r9)
1253 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1254 cmpdi r3, 0 /* retry the instruction */
1256 cmpdi r3, -1 /* handle in kernel mode */
1259 /* Synthesize an ISI for the guest */
1261 1: mtspr SPRN_SRR0, r10
1262 mtspr SPRN_SRR1, r11
1263 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1264 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1266 6: ld r7, VCPU_CTR(r9)
1267 lwz r8, VCPU_XER(r9)
1273 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1274 ld r5, KVM_VRMA_SLB_V(r6)
1278 * Try to handle an hcall in real mode.
1279 * Returns to the guest if we handle it, or continues on up to
1280 * the kernel if we can't (i.e. if we don't have a handler for
1281 * it, or if the handler returns H_TOO_HARD).
1283 .globl hcall_try_real_mode
1284 hcall_try_real_mode:
1285 ld r3,VCPU_GPR(R3)(r9)
1289 cmpldi r3,hcall_real_table_end - hcall_real_table
1291 LOAD_REG_ADDR(r4, hcall_real_table)
1297 mr r3,r9 /* get vcpu pointer */
1298 ld r4,VCPU_GPR(R4)(r9)
1301 beq hcall_real_fallback
1302 ld r4,HSTATE_KVM_VCPU(r13)
1303 std r3,VCPU_GPR(R3)(r4)
1308 /* We've attempted a real mode hcall, but it's punted it back
1309 * to userspace. We need to restore some clobbered volatiles
1310 * before resuming the pass-it-to-qemu path */
1311 hcall_real_fallback:
1312 li r12,BOOK3S_INTERRUPT_SYSCALL
1313 ld r9, HSTATE_KVM_VCPU(r13)
1317 .globl hcall_real_table
1319 .long 0 /* 0 - unused */
1320 .long .kvmppc_h_remove - hcall_real_table
1321 .long .kvmppc_h_enter - hcall_real_table
1322 .long .kvmppc_h_read - hcall_real_table
1323 .long 0 /* 0x10 - H_CLEAR_MOD */
1324 .long 0 /* 0x14 - H_CLEAR_REF */
1325 .long .kvmppc_h_protect - hcall_real_table
1326 .long 0 /* 0x1c - H_GET_TCE */
1327 .long .kvmppc_h_put_tce - hcall_real_table
1328 .long 0 /* 0x24 - H_SET_SPRG0 */
1329 .long .kvmppc_h_set_dabr - hcall_real_table
1375 .long .kvmppc_h_cede - hcall_real_table
1392 .long .kvmppc_h_bulk_remove - hcall_real_table
1393 hcall_real_table_end:
1399 bounce_ext_interrupt:
1403 li r10,BOOK3S_INTERRUPT_EXTERNAL
1404 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1408 _GLOBAL(kvmppc_h_set_dabr)
1409 std r4,VCPU_DABR(r3)
1410 /* Work around P7 bug where DABR can get corrupted on mtspr */
1411 1: mtspr SPRN_DABR,r4
1419 _GLOBAL(kvmppc_h_cede)
1421 std r11,VCPU_MSR(r3)
1423 stb r0,VCPU_CEDED(r3)
1424 sync /* order setting ceded vs. testing prodded */
1425 lbz r5,VCPU_PRODDED(r3)
1427 bne kvm_cede_prodded
1428 li r0,0 /* set trap to 0 to say hcall is handled */
1429 stw r0,VCPU_TRAP(r3)
1431 std r0,VCPU_GPR(R3)(r3)
1433 b kvm_cede_exit /* just send it up to host on 970 */
1434 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1437 * Set our bit in the bitmask of napping threads unless all the
1438 * other threads are already napping, in which case we send this
1441 ld r5,HSTATE_KVM_VCORE(r13)
1442 lwz r6,VCPU_PTID(r3)
1443 lwz r8,VCORE_ENTRY_EXIT(r5)
1447 addi r6,r5,VCORE_NAPPING_THREADS
1456 stb r0,HSTATE_NAPPING(r13)
1457 /* order napping_threads update vs testing entry_exit_count */
1460 lwz r7,VCORE_ENTRY_EXIT(r5)
1462 bge 33f /* another thread already exiting */
1465 * Although not specifically required by the architecture, POWER7
1466 * preserves the following registers in nap mode, even if an SMT mode
1467 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
1468 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
1470 /* Save non-volatile GPRs */
1471 std r14, VCPU_GPR(R14)(r3)
1472 std r15, VCPU_GPR(R15)(r3)
1473 std r16, VCPU_GPR(R16)(r3)
1474 std r17, VCPU_GPR(R17)(r3)
1475 std r18, VCPU_GPR(R18)(r3)
1476 std r19, VCPU_GPR(R19)(r3)
1477 std r20, VCPU_GPR(R20)(r3)
1478 std r21, VCPU_GPR(R21)(r3)
1479 std r22, VCPU_GPR(R22)(r3)
1480 std r23, VCPU_GPR(R23)(r3)
1481 std r24, VCPU_GPR(R24)(r3)
1482 std r25, VCPU_GPR(R25)(r3)
1483 std r26, VCPU_GPR(R26)(r3)
1484 std r27, VCPU_GPR(R27)(r3)
1485 std r28, VCPU_GPR(R28)(r3)
1486 std r29, VCPU_GPR(R29)(r3)
1487 std r30, VCPU_GPR(R30)(r3)
1488 std r31, VCPU_GPR(R31)(r3)
1494 * Take a nap until a decrementer or external interrupt occurs,
1495 * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR
1498 stb r0,HSTATE_HWTHREAD_REQ(r13)
1500 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
1504 std r0, HSTATE_SCRATCH0(r13)
1506 ld r0, HSTATE_SCRATCH0(r13)
1513 /* Woken by external or decrementer interrupt */
1514 ld r1, HSTATE_HOST_R1(r13)
1516 /* load up FP state */
1520 ld r14, VCPU_GPR(R14)(r4)
1521 ld r15, VCPU_GPR(R15)(r4)
1522 ld r16, VCPU_GPR(R16)(r4)
1523 ld r17, VCPU_GPR(R17)(r4)
1524 ld r18, VCPU_GPR(R18)(r4)
1525 ld r19, VCPU_GPR(R19)(r4)
1526 ld r20, VCPU_GPR(R20)(r4)
1527 ld r21, VCPU_GPR(R21)(r4)
1528 ld r22, VCPU_GPR(R22)(r4)
1529 ld r23, VCPU_GPR(R23)(r4)
1530 ld r24, VCPU_GPR(R24)(r4)
1531 ld r25, VCPU_GPR(R25)(r4)
1532 ld r26, VCPU_GPR(R26)(r4)
1533 ld r27, VCPU_GPR(R27)(r4)
1534 ld r28, VCPU_GPR(R28)(r4)
1535 ld r29, VCPU_GPR(R29)(r4)
1536 ld r30, VCPU_GPR(R30)(r4)
1537 ld r31, VCPU_GPR(R31)(r4)
1539 /* clear our bit in vcore->napping_threads */
1540 33: ld r5,HSTATE_KVM_VCORE(r13)
1541 lwz r3,VCPU_PTID(r4)
1544 addi r6,r5,VCORE_NAPPING_THREADS
1550 stb r0,HSTATE_NAPPING(r13)
1552 /* see if any other thread is already exiting */
1553 lwz r0,VCORE_ENTRY_EXIT(r5)
1555 blt kvmppc_cede_reentry /* if not go back to guest */
1557 /* some threads are exiting, so go to the guest exit path */
1558 b hcall_real_fallback
1560 /* cede when already previously prodded case */
1563 stb r0,VCPU_PRODDED(r3)
1564 sync /* order testing prodded vs. clearing ceded */
1565 stb r0,VCPU_CEDED(r3)
1569 /* we've ceded but we want to give control to the host */
1575 ld r5,HSTATE_KVM_VCORE(r13)
1577 13: lbz r3,VCORE_IN_GUEST(r5)
1581 ld r11,PACA_SLBSHADOWPTR(r13)
1583 .rept SLB_NUM_BOLTED
1584 ld r5,SLBSHADOW_SAVEAREA(r11)
1585 ld r6,SLBSHADOW_SAVEAREA+8(r11)
1586 andis. r7,r5,SLB_ESID_V@h
1593 /* Clear our vcpu pointer so we don't come back in early */
1595 std r0, HSTATE_KVM_VCPU(r13)
1597 /* Clear any pending IPI - assume we're a secondary thread */
1598 ld r5, HSTATE_XICS_PHYS(r13)
1600 lwzcix r3, r5, r7 /* ack any pending interrupt */
1601 rlwinm. r0, r3, 0, 0xffffff /* any pending? */
1606 stbcix r0, r5, r6 /* clear the IPI */
1607 stwcix r3, r5, r7 /* EOI it */
1610 /* increment the nap count and then go to nap mode */
1611 ld r4, HSTATE_KVM_VCORE(r13)
1612 addi r4, r4, VCORE_NAP_COUNT
1613 lwsync /* make previous updates visible */
1620 li r0, KVM_HWTHREAD_IN_NAP
1621 stb r0, HSTATE_HWTHREAD_STATE(r13)
1625 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
1628 std r0, HSTATE_SCRATCH0(r13)
1630 ld r0, HSTATE_SCRATCH0(r13)
1637 * Save away FP, VMX and VSX registers.
1640 _GLOBAL(kvmppc_save_fp)
1643 #ifdef CONFIG_ALTIVEC
1645 oris r8,r8,MSR_VEC@h
1646 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1650 oris r8,r8,MSR_VSX@h
1651 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1659 li r6,reg*16+VCPU_VSRS
1667 stfd reg,reg*8+VCPU_FPRS(r3)
1671 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1674 stfd fr0,VCPU_FPSCR(r3)
1676 #ifdef CONFIG_ALTIVEC
1680 li r6,reg*16+VCPU_VRS
1687 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1689 mfspr r6,SPRN_VRSAVE
1690 stw r6,VCPU_VRSAVE(r3)
1696 * Load up FP, VMX and VSX registers
1699 .globl kvmppc_load_fp
1703 #ifdef CONFIG_ALTIVEC
1705 oris r8,r8,MSR_VEC@h
1706 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1710 oris r8,r8,MSR_VSX@h
1711 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1715 lfd fr0,VCPU_FPSCR(r4)
1721 li r7,reg*16+VCPU_VSRS
1729 lfd reg,reg*8+VCPU_FPRS(r4)
1733 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1736 #ifdef CONFIG_ALTIVEC
1743 li r7,reg*16+VCPU_VRS
1747 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1749 lwz r7,VCPU_VRSAVE(r4)
1750 mtspr SPRN_VRSAVE,r7