2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/kvm_ppc.h>
21 #include <asm/disassemble.h>
22 #include <asm/kvm_book3s.h>
24 #include <asm/switch_to.h>
26 #define OP_19_XOP_RFID 18
27 #define OP_19_XOP_RFI 50
29 #define OP_31_XOP_MFMSR 83
30 #define OP_31_XOP_MTMSR 146
31 #define OP_31_XOP_MTMSRD 178
32 #define OP_31_XOP_MTSR 210
33 #define OP_31_XOP_MTSRIN 242
34 #define OP_31_XOP_TLBIEL 274
35 #define OP_31_XOP_TLBIE 306
36 #define OP_31_XOP_SLBMTE 402
37 #define OP_31_XOP_SLBIE 434
38 #define OP_31_XOP_SLBIA 498
39 #define OP_31_XOP_MFSR 595
40 #define OP_31_XOP_MFSRIN 659
41 #define OP_31_XOP_DCBA 758
42 #define OP_31_XOP_SLBMFEV 851
43 #define OP_31_XOP_EIOIO 854
44 #define OP_31_XOP_SLBMFEE 915
46 /* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */
47 #define OP_31_XOP_DCBZ 1010
63 /* Book3S_32 defines mfsrin(v) - but that messes up our abstract
64 * function pointers, so let's just disable the define. */
73 static bool spr_allowed(struct kvm_vcpu *vcpu, enum priv_level level)
75 /* PAPR VMs only access supervisor SPRs */
76 if (vcpu->arch.papr_enabled && (level > PRIV_SUPER))
79 /* Limit user space to its own small SPR set */
80 if ((vcpu->arch.shared->msr & MSR_PR) && level > PRIV_PROBLEM)
86 int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
87 unsigned int inst, int *advance)
89 int emulated = EMULATE_DONE;
91 switch (get_op(inst)) {
93 switch (get_xop(inst)) {
96 kvmppc_set_pc(vcpu, vcpu->arch.shared->srr0);
97 kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
102 emulated = EMULATE_FAIL;
107 switch (get_xop(inst)) {
108 case OP_31_XOP_MFMSR:
109 kvmppc_set_gpr(vcpu, get_rt(inst),
110 vcpu->arch.shared->msr);
112 case OP_31_XOP_MTMSRD:
114 ulong rs = kvmppc_get_gpr(vcpu, get_rs(inst));
115 if (inst & 0x10000) {
116 vcpu->arch.shared->msr &= ~(MSR_RI | MSR_EE);
117 vcpu->arch.shared->msr |= rs & (MSR_RI | MSR_EE);
119 kvmppc_set_msr(vcpu, rs);
122 case OP_31_XOP_MTMSR:
123 kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, get_rs(inst)));
129 srnum = kvmppc_get_field(inst, 12 + 32, 15 + 32);
130 if (vcpu->arch.mmu.mfsrin) {
132 sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
133 kvmppc_set_gpr(vcpu, get_rt(inst), sr);
137 case OP_31_XOP_MFSRIN:
141 srnum = (kvmppc_get_gpr(vcpu, get_rb(inst)) >> 28) & 0xf;
142 if (vcpu->arch.mmu.mfsrin) {
144 sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
145 kvmppc_set_gpr(vcpu, get_rt(inst), sr);
150 vcpu->arch.mmu.mtsrin(vcpu,
152 kvmppc_get_gpr(vcpu, get_rs(inst)));
154 case OP_31_XOP_MTSRIN:
155 vcpu->arch.mmu.mtsrin(vcpu,
156 (kvmppc_get_gpr(vcpu, get_rb(inst)) >> 28) & 0xf,
157 kvmppc_get_gpr(vcpu, get_rs(inst)));
159 case OP_31_XOP_TLBIE:
160 case OP_31_XOP_TLBIEL:
162 bool large = (inst & 0x00200000) ? true : false;
163 ulong addr = kvmppc_get_gpr(vcpu, get_rb(inst));
164 vcpu->arch.mmu.tlbie(vcpu, addr, large);
167 case OP_31_XOP_EIOIO:
169 case OP_31_XOP_SLBMTE:
170 if (!vcpu->arch.mmu.slbmte)
173 vcpu->arch.mmu.slbmte(vcpu,
174 kvmppc_get_gpr(vcpu, get_rs(inst)),
175 kvmppc_get_gpr(vcpu, get_rb(inst)));
177 case OP_31_XOP_SLBIE:
178 if (!vcpu->arch.mmu.slbie)
181 vcpu->arch.mmu.slbie(vcpu,
182 kvmppc_get_gpr(vcpu, get_rb(inst)));
184 case OP_31_XOP_SLBIA:
185 if (!vcpu->arch.mmu.slbia)
188 vcpu->arch.mmu.slbia(vcpu);
190 case OP_31_XOP_SLBMFEE:
191 if (!vcpu->arch.mmu.slbmfee) {
192 emulated = EMULATE_FAIL;
196 rb = kvmppc_get_gpr(vcpu, get_rb(inst));
197 t = vcpu->arch.mmu.slbmfee(vcpu, rb);
198 kvmppc_set_gpr(vcpu, get_rt(inst), t);
201 case OP_31_XOP_SLBMFEV:
202 if (!vcpu->arch.mmu.slbmfev) {
203 emulated = EMULATE_FAIL;
207 rb = kvmppc_get_gpr(vcpu, get_rb(inst));
208 t = vcpu->arch.mmu.slbmfev(vcpu, rb);
209 kvmppc_set_gpr(vcpu, get_rt(inst), t);
213 /* Gets treated as NOP */
217 ulong rb = kvmppc_get_gpr(vcpu, get_rb(inst));
220 u32 zeros[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
225 ra = kvmppc_get_gpr(vcpu, get_ra(inst));
227 addr = (ra + rb) & ~31ULL;
228 if (!(vcpu->arch.shared->msr & MSR_SF))
232 r = kvmppc_st(vcpu, &addr, 32, zeros, true);
233 if ((r == -ENOENT) || (r == -EPERM)) {
234 struct kvmppc_book3s_shadow_vcpu *svcpu;
236 svcpu = svcpu_get(vcpu);
238 vcpu->arch.shared->dar = vaddr;
239 svcpu->fault_dar = vaddr;
241 dsisr = DSISR_ISSTORE;
243 dsisr |= DSISR_NOHPTE;
244 else if (r == -EPERM)
245 dsisr |= DSISR_PROTFAULT;
247 vcpu->arch.shared->dsisr = dsisr;
248 svcpu->fault_dsisr = dsisr;
251 kvmppc_book3s_queue_irqprio(vcpu,
252 BOOK3S_INTERRUPT_DATA_STORAGE);
258 emulated = EMULATE_FAIL;
262 emulated = EMULATE_FAIL;
265 if (emulated == EMULATE_FAIL)
266 emulated = kvmppc_emulate_paired_single(run, vcpu);
271 void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat, bool upper,
276 u32 bl = (val >> 2) & 0x7ff;
277 bat->bepi_mask = (~bl << 17);
278 bat->bepi = val & 0xfffe0000;
279 bat->vs = (val & 2) ? 1 : 0;
280 bat->vp = (val & 1) ? 1 : 0;
281 bat->raw = (bat->raw & 0xffffffff00000000ULL) | val;
284 bat->brpn = val & 0xfffe0000;
285 bat->wimg = (val >> 3) & 0xf;
287 bat->raw = (bat->raw & 0x00000000ffffffffULL) | ((u64)val << 32);
291 static struct kvmppc_bat *kvmppc_find_bat(struct kvm_vcpu *vcpu, int sprn)
293 struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
294 struct kvmppc_bat *bat;
297 case SPRN_IBAT0U ... SPRN_IBAT3L:
298 bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT0U) / 2];
300 case SPRN_IBAT4U ... SPRN_IBAT7L:
301 bat = &vcpu_book3s->ibat[4 + ((sprn - SPRN_IBAT4U) / 2)];
303 case SPRN_DBAT0U ... SPRN_DBAT3L:
304 bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT0U) / 2];
306 case SPRN_DBAT4U ... SPRN_DBAT7L:
307 bat = &vcpu_book3s->dbat[4 + ((sprn - SPRN_DBAT4U) / 2)];
316 int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs)
318 int emulated = EMULATE_DONE;
319 ulong spr_val = kvmppc_get_gpr(vcpu, rs);
323 if (!spr_allowed(vcpu, PRIV_HYPER))
325 to_book3s(vcpu)->sdr1 = spr_val;
328 vcpu->arch.shared->dsisr = spr_val;
331 vcpu->arch.shared->dar = spr_val;
334 to_book3s(vcpu)->hior = spr_val;
336 case SPRN_IBAT0U ... SPRN_IBAT3L:
337 case SPRN_IBAT4U ... SPRN_IBAT7L:
338 case SPRN_DBAT0U ... SPRN_DBAT3L:
339 case SPRN_DBAT4U ... SPRN_DBAT7L:
341 struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn);
343 kvmppc_set_bat(vcpu, bat, !(sprn % 2), (u32)spr_val);
344 /* BAT writes happen so rarely that we're ok to flush
346 kvmppc_mmu_pte_flush(vcpu, 0, 0);
347 kvmppc_mmu_flush_segments(vcpu);
351 to_book3s(vcpu)->hid[0] = spr_val;
354 to_book3s(vcpu)->hid[1] = spr_val;
357 to_book3s(vcpu)->hid[2] = spr_val;
359 case SPRN_HID2_GEKKO:
360 to_book3s(vcpu)->hid[2] = spr_val;
361 /* HID2.PSE controls paired single on gekko */
362 switch (vcpu->arch.pvr) {
363 case 0x00080200: /* lonestar 2.0 */
364 case 0x00088202: /* lonestar 2.2 */
365 case 0x70000100: /* gekko 1.0 */
366 case 0x00080100: /* gekko 2.0 */
367 case 0x00083203: /* gekko 2.3a */
368 case 0x00083213: /* gekko 2.3b */
369 case 0x00083204: /* gekko 2.4 */
370 case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */
371 case 0x00087200: /* broadway */
372 if (vcpu->arch.hflags & BOOK3S_HFLAG_NATIVE_PS) {
373 /* Native paired singles */
374 } else if (spr_val & (1 << 29)) { /* HID2.PSE */
375 vcpu->arch.hflags |= BOOK3S_HFLAG_PAIRED_SINGLE;
376 kvmppc_giveup_ext(vcpu, MSR_FP);
378 vcpu->arch.hflags &= ~BOOK3S_HFLAG_PAIRED_SINGLE;
384 case SPRN_HID4_GEKKO:
385 to_book3s(vcpu)->hid[4] = spr_val;
388 to_book3s(vcpu)->hid[5] = spr_val;
389 /* guest HID5 set can change is_dcbz32 */
390 if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
392 vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
402 to_book3s(vcpu)->gqr[sprn - SPRN_GQR0] = spr_val;
411 case SPRN_MMCR0_GEKKO:
412 case SPRN_MMCR1_GEKKO:
413 case SPRN_PMC1_GEKKO:
414 case SPRN_PMC2_GEKKO:
415 case SPRN_PMC3_GEKKO:
416 case SPRN_PMC4_GEKKO:
417 case SPRN_WPAR_GEKKO:
421 printk(KERN_INFO "KVM: invalid SPR write: %d\n", sprn);
423 emulated = EMULATE_FAIL;
431 int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt)
433 int emulated = EMULATE_DONE;
436 case SPRN_IBAT0U ... SPRN_IBAT3L:
437 case SPRN_IBAT4U ... SPRN_IBAT7L:
438 case SPRN_DBAT0U ... SPRN_DBAT3L:
439 case SPRN_DBAT4U ... SPRN_DBAT7L:
441 struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn);
444 kvmppc_set_gpr(vcpu, rt, bat->raw >> 32);
446 kvmppc_set_gpr(vcpu, rt, bat->raw);
451 if (!spr_allowed(vcpu, PRIV_HYPER))
453 kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->sdr1);
456 kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->dsisr);
459 kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->dar);
462 kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hior);
465 kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[0]);
468 kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[1]);
471 case SPRN_HID2_GEKKO:
472 kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[2]);
475 case SPRN_HID4_GEKKO:
476 kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[4]);
479 kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[5]);
483 kvmppc_set_gpr(vcpu, rt, 0);
493 kvmppc_set_gpr(vcpu, rt,
494 to_book3s(vcpu)->gqr[sprn - SPRN_GQR0]);
502 case SPRN_MMCR0_GEKKO:
503 case SPRN_MMCR1_GEKKO:
504 case SPRN_PMC1_GEKKO:
505 case SPRN_PMC2_GEKKO:
506 case SPRN_PMC3_GEKKO:
507 case SPRN_PMC4_GEKKO:
508 case SPRN_WPAR_GEKKO:
509 kvmppc_set_gpr(vcpu, rt, 0);
513 printk(KERN_INFO "KVM: invalid SPR read: %d\n", sprn);
515 emulated = EMULATE_FAIL;
523 u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst)
528 * This is what the spec says about DSISR bits (not mentioned = 0):
530 * 12:13 [DS] Set to bits 30:31
531 * 15:16 [X] Set to bits 29:30
532 * 17 [X] Set to bit 25
533 * [D/DS] Set to bit 5
534 * 18:21 [X] Set to bits 21:24
535 * [D/DS] Set to bits 1:4
536 * 22:26 Set to bits 6:10 (RT/RS/FRT/FRS)
537 * 27:31 Set to bits 11:15 (RA)
540 switch (get_op(inst)) {
546 dsisr |= (inst >> 12) & 0x4000; /* bit 17 */
547 dsisr |= (inst >> 17) & 0x3c00; /* bits 18:21 */
551 dsisr |= (inst << 14) & 0x18000; /* bits 15:16 */
552 dsisr |= (inst << 8) & 0x04000; /* bit 17 */
553 dsisr |= (inst << 3) & 0x03c00; /* bits 18:21 */
556 printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst);
560 dsisr |= (inst >> 16) & 0x03ff; /* bits 22:31 */
565 ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst)
570 switch (get_op(inst)) {
577 dar = kvmppc_get_gpr(vcpu, ra);
578 dar += (s32)((s16)inst);
583 dar = kvmppc_get_gpr(vcpu, ra);
584 dar += kvmppc_get_gpr(vcpu, get_rb(inst));
587 printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst);