Merge tag 'drm-intel-fixes-2016-01-02' of git://anongit.freedesktop.org/drm-intel
[firefly-linux-kernel-4.4.55.git] / arch / powerpc / kernel / process.c
1 /*
2  *  Derived from "arch/i386/kernel/process.c"
3  *    Copyright (C) 1995  Linus Torvalds
4  *
5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6  *  Paul Mackerras (paulus@cs.anu.edu.au)
7  *
8  *  PowerPC version
9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
10  *
11  *  This program is free software; you can redistribute it and/or
12  *  modify it under the terms of the GNU General Public License
13  *  as published by the Free Software Foundation; either version
14  *  2 of the License, or (at your option) any later version.
15  */
16
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/mm.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/elf.h>
28 #include <linux/prctl.h>
29 #include <linux/init_task.h>
30 #include <linux/export.h>
31 #include <linux/kallsyms.h>
32 #include <linux/mqueue.h>
33 #include <linux/hardirq.h>
34 #include <linux/utsname.h>
35 #include <linux/ftrace.h>
36 #include <linux/kernel_stat.h>
37 #include <linux/personality.h>
38 #include <linux/random.h>
39 #include <linux/hw_breakpoint.h>
40 #include <linux/uaccess.h>
41
42 #include <asm/pgtable.h>
43 #include <asm/io.h>
44 #include <asm/processor.h>
45 #include <asm/mmu.h>
46 #include <asm/prom.h>
47 #include <asm/machdep.h>
48 #include <asm/time.h>
49 #include <asm/runlatch.h>
50 #include <asm/syscalls.h>
51 #include <asm/switch_to.h>
52 #include <asm/tm.h>
53 #include <asm/debug.h>
54 #ifdef CONFIG_PPC64
55 #include <asm/firmware.h>
56 #endif
57 #include <asm/code-patching.h>
58 #include <linux/kprobes.h>
59 #include <linux/kdebug.h>
60
61 /* Transactional Memory debug */
62 #ifdef TM_DEBUG_SW
63 #define TM_DEBUG(x...) printk(KERN_INFO x)
64 #else
65 #define TM_DEBUG(x...) do { } while(0)
66 #endif
67
68 extern unsigned long _get_SP(void);
69
70 #ifndef CONFIG_SMP
71 struct task_struct *last_task_used_math = NULL;
72 struct task_struct *last_task_used_altivec = NULL;
73 struct task_struct *last_task_used_vsx = NULL;
74 struct task_struct *last_task_used_spe = NULL;
75 #endif
76
77 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
78 void giveup_fpu_maybe_transactional(struct task_struct *tsk)
79 {
80         /*
81          * If we are saving the current thread's registers, and the
82          * thread is in a transactional state, set the TIF_RESTORE_TM
83          * bit so that we know to restore the registers before
84          * returning to userspace.
85          */
86         if (tsk == current && tsk->thread.regs &&
87             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
88             !test_thread_flag(TIF_RESTORE_TM)) {
89                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
90                 set_thread_flag(TIF_RESTORE_TM);
91         }
92
93         giveup_fpu(tsk);
94 }
95
96 void giveup_altivec_maybe_transactional(struct task_struct *tsk)
97 {
98         /*
99          * If we are saving the current thread's registers, and the
100          * thread is in a transactional state, set the TIF_RESTORE_TM
101          * bit so that we know to restore the registers before
102          * returning to userspace.
103          */
104         if (tsk == current && tsk->thread.regs &&
105             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
106             !test_thread_flag(TIF_RESTORE_TM)) {
107                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
108                 set_thread_flag(TIF_RESTORE_TM);
109         }
110
111         giveup_altivec(tsk);
112 }
113
114 #else
115 #define giveup_fpu_maybe_transactional(tsk)     giveup_fpu(tsk)
116 #define giveup_altivec_maybe_transactional(tsk) giveup_altivec(tsk)
117 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
118
119 #ifdef CONFIG_PPC_FPU
120 /*
121  * Make sure the floating-point register state in the
122  * the thread_struct is up to date for task tsk.
123  */
124 void flush_fp_to_thread(struct task_struct *tsk)
125 {
126         if (tsk->thread.regs) {
127                 /*
128                  * We need to disable preemption here because if we didn't,
129                  * another process could get scheduled after the regs->msr
130                  * test but before we have finished saving the FP registers
131                  * to the thread_struct.  That process could take over the
132                  * FPU, and then when we get scheduled again we would store
133                  * bogus values for the remaining FP registers.
134                  */
135                 preempt_disable();
136                 if (tsk->thread.regs->msr & MSR_FP) {
137 #ifdef CONFIG_SMP
138                         /*
139                          * This should only ever be called for current or
140                          * for a stopped child process.  Since we save away
141                          * the FP register state on context switch on SMP,
142                          * there is something wrong if a stopped child appears
143                          * to still have its FP state in the CPU registers.
144                          */
145                         BUG_ON(tsk != current);
146 #endif
147                         giveup_fpu_maybe_transactional(tsk);
148                 }
149                 preempt_enable();
150         }
151 }
152 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
153 #endif /* CONFIG_PPC_FPU */
154
155 void enable_kernel_fp(void)
156 {
157         WARN_ON(preemptible());
158
159 #ifdef CONFIG_SMP
160         if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
161                 giveup_fpu_maybe_transactional(current);
162         else
163                 giveup_fpu(NULL);       /* just enables FP for kernel */
164 #else
165         giveup_fpu_maybe_transactional(last_task_used_math);
166 #endif /* CONFIG_SMP */
167 }
168 EXPORT_SYMBOL(enable_kernel_fp);
169
170 #ifdef CONFIG_ALTIVEC
171 void enable_kernel_altivec(void)
172 {
173         WARN_ON(preemptible());
174
175 #ifdef CONFIG_SMP
176         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
177                 giveup_altivec_maybe_transactional(current);
178         else
179                 giveup_altivec_notask();
180 #else
181         giveup_altivec_maybe_transactional(last_task_used_altivec);
182 #endif /* CONFIG_SMP */
183 }
184 EXPORT_SYMBOL(enable_kernel_altivec);
185
186 /*
187  * Make sure the VMX/Altivec register state in the
188  * the thread_struct is up to date for task tsk.
189  */
190 void flush_altivec_to_thread(struct task_struct *tsk)
191 {
192         if (tsk->thread.regs) {
193                 preempt_disable();
194                 if (tsk->thread.regs->msr & MSR_VEC) {
195 #ifdef CONFIG_SMP
196                         BUG_ON(tsk != current);
197 #endif
198                         giveup_altivec_maybe_transactional(tsk);
199                 }
200                 preempt_enable();
201         }
202 }
203 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
204 #endif /* CONFIG_ALTIVEC */
205
206 #ifdef CONFIG_VSX
207 void enable_kernel_vsx(void)
208 {
209         WARN_ON(preemptible());
210
211 #ifdef CONFIG_SMP
212         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX))
213                 giveup_vsx(current);
214         else
215                 giveup_vsx(NULL);       /* just enable vsx for kernel - force */
216 #else
217         giveup_vsx(last_task_used_vsx);
218 #endif /* CONFIG_SMP */
219 }
220 EXPORT_SYMBOL(enable_kernel_vsx);
221
222 void giveup_vsx(struct task_struct *tsk)
223 {
224         giveup_fpu_maybe_transactional(tsk);
225         giveup_altivec_maybe_transactional(tsk);
226         __giveup_vsx(tsk);
227 }
228 EXPORT_SYMBOL(giveup_vsx);
229
230 void flush_vsx_to_thread(struct task_struct *tsk)
231 {
232         if (tsk->thread.regs) {
233                 preempt_disable();
234                 if (tsk->thread.regs->msr & MSR_VSX) {
235 #ifdef CONFIG_SMP
236                         BUG_ON(tsk != current);
237 #endif
238                         giveup_vsx(tsk);
239                 }
240                 preempt_enable();
241         }
242 }
243 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
244 #endif /* CONFIG_VSX */
245
246 #ifdef CONFIG_SPE
247
248 void enable_kernel_spe(void)
249 {
250         WARN_ON(preemptible());
251
252 #ifdef CONFIG_SMP
253         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
254                 giveup_spe(current);
255         else
256                 giveup_spe(NULL);       /* just enable SPE for kernel - force */
257 #else
258         giveup_spe(last_task_used_spe);
259 #endif /* __SMP __ */
260 }
261 EXPORT_SYMBOL(enable_kernel_spe);
262
263 void flush_spe_to_thread(struct task_struct *tsk)
264 {
265         if (tsk->thread.regs) {
266                 preempt_disable();
267                 if (tsk->thread.regs->msr & MSR_SPE) {
268 #ifdef CONFIG_SMP
269                         BUG_ON(tsk != current);
270 #endif
271                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
272                         giveup_spe(tsk);
273                 }
274                 preempt_enable();
275         }
276 }
277 #endif /* CONFIG_SPE */
278
279 #ifndef CONFIG_SMP
280 /*
281  * If we are doing lazy switching of CPU state (FP, altivec or SPE),
282  * and the current task has some state, discard it.
283  */
284 void discard_lazy_cpu_state(void)
285 {
286         preempt_disable();
287         if (last_task_used_math == current)
288                 last_task_used_math = NULL;
289 #ifdef CONFIG_ALTIVEC
290         if (last_task_used_altivec == current)
291                 last_task_used_altivec = NULL;
292 #endif /* CONFIG_ALTIVEC */
293 #ifdef CONFIG_VSX
294         if (last_task_used_vsx == current)
295                 last_task_used_vsx = NULL;
296 #endif /* CONFIG_VSX */
297 #ifdef CONFIG_SPE
298         if (last_task_used_spe == current)
299                 last_task_used_spe = NULL;
300 #endif
301         preempt_enable();
302 }
303 #endif /* CONFIG_SMP */
304
305 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
306 void do_send_trap(struct pt_regs *regs, unsigned long address,
307                   unsigned long error_code, int signal_code, int breakpt)
308 {
309         siginfo_t info;
310
311         current->thread.trap_nr = signal_code;
312         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
313                         11, SIGSEGV) == NOTIFY_STOP)
314                 return;
315
316         /* Deliver the signal to userspace */
317         info.si_signo = SIGTRAP;
318         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
319         info.si_code = signal_code;
320         info.si_addr = (void __user *)address;
321         force_sig_info(SIGTRAP, &info, current);
322 }
323 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
324 void do_break (struct pt_regs *regs, unsigned long address,
325                     unsigned long error_code)
326 {
327         siginfo_t info;
328
329         current->thread.trap_nr = TRAP_HWBKPT;
330         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
331                         11, SIGSEGV) == NOTIFY_STOP)
332                 return;
333
334         if (debugger_break_match(regs))
335                 return;
336
337         /* Clear the breakpoint */
338         hw_breakpoint_disable();
339
340         /* Deliver the signal to userspace */
341         info.si_signo = SIGTRAP;
342         info.si_errno = 0;
343         info.si_code = TRAP_HWBKPT;
344         info.si_addr = (void __user *)address;
345         force_sig_info(SIGTRAP, &info, current);
346 }
347 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
348
349 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
350
351 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
352 /*
353  * Set the debug registers back to their default "safe" values.
354  */
355 static void set_debug_reg_defaults(struct thread_struct *thread)
356 {
357         thread->debug.iac1 = thread->debug.iac2 = 0;
358 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
359         thread->debug.iac3 = thread->debug.iac4 = 0;
360 #endif
361         thread->debug.dac1 = thread->debug.dac2 = 0;
362 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
363         thread->debug.dvc1 = thread->debug.dvc2 = 0;
364 #endif
365         thread->debug.dbcr0 = 0;
366 #ifdef CONFIG_BOOKE
367         /*
368          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
369          */
370         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
371                         DBCR1_IAC3US | DBCR1_IAC4US;
372         /*
373          * Force Data Address Compare User/Supervisor bits to be User-only
374          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
375          */
376         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
377 #else
378         thread->debug.dbcr1 = 0;
379 #endif
380 }
381
382 static void prime_debug_regs(struct debug_reg *debug)
383 {
384         /*
385          * We could have inherited MSR_DE from userspace, since
386          * it doesn't get cleared on exception entry.  Make sure
387          * MSR_DE is clear before we enable any debug events.
388          */
389         mtmsr(mfmsr() & ~MSR_DE);
390
391         mtspr(SPRN_IAC1, debug->iac1);
392         mtspr(SPRN_IAC2, debug->iac2);
393 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
394         mtspr(SPRN_IAC3, debug->iac3);
395         mtspr(SPRN_IAC4, debug->iac4);
396 #endif
397         mtspr(SPRN_DAC1, debug->dac1);
398         mtspr(SPRN_DAC2, debug->dac2);
399 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
400         mtspr(SPRN_DVC1, debug->dvc1);
401         mtspr(SPRN_DVC2, debug->dvc2);
402 #endif
403         mtspr(SPRN_DBCR0, debug->dbcr0);
404         mtspr(SPRN_DBCR1, debug->dbcr1);
405 #ifdef CONFIG_BOOKE
406         mtspr(SPRN_DBCR2, debug->dbcr2);
407 #endif
408 }
409 /*
410  * Unless neither the old or new thread are making use of the
411  * debug registers, set the debug registers from the values
412  * stored in the new thread.
413  */
414 void switch_booke_debug_regs(struct debug_reg *new_debug)
415 {
416         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
417                 || (new_debug->dbcr0 & DBCR0_IDM))
418                         prime_debug_regs(new_debug);
419 }
420 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
421 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
422 #ifndef CONFIG_HAVE_HW_BREAKPOINT
423 static void set_debug_reg_defaults(struct thread_struct *thread)
424 {
425         thread->hw_brk.address = 0;
426         thread->hw_brk.type = 0;
427         set_breakpoint(&thread->hw_brk);
428 }
429 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
430 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
431
432 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
433 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
434 {
435         mtspr(SPRN_DAC1, dabr);
436 #ifdef CONFIG_PPC_47x
437         isync();
438 #endif
439         return 0;
440 }
441 #elif defined(CONFIG_PPC_BOOK3S)
442 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
443 {
444         mtspr(SPRN_DABR, dabr);
445         if (cpu_has_feature(CPU_FTR_DABRX))
446                 mtspr(SPRN_DABRX, dabrx);
447         return 0;
448 }
449 #else
450 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
451 {
452         return -EINVAL;
453 }
454 #endif
455
456 static inline int set_dabr(struct arch_hw_breakpoint *brk)
457 {
458         unsigned long dabr, dabrx;
459
460         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
461         dabrx = ((brk->type >> 3) & 0x7);
462
463         if (ppc_md.set_dabr)
464                 return ppc_md.set_dabr(dabr, dabrx);
465
466         return __set_dabr(dabr, dabrx);
467 }
468
469 static inline int set_dawr(struct arch_hw_breakpoint *brk)
470 {
471         unsigned long dawr, dawrx, mrd;
472
473         dawr = brk->address;
474
475         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
476                                    << (63 - 58); //* read/write bits */
477         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
478                                    << (63 - 59); //* translate */
479         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
480                                    >> 3; //* PRIM bits */
481         /* dawr length is stored in field MDR bits 48:53.  Matches range in
482            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
483            0b111111=64DW.
484            brk->len is in bytes.
485            This aligns up to double word size, shifts and does the bias.
486         */
487         mrd = ((brk->len + 7) >> 3) - 1;
488         dawrx |= (mrd & 0x3f) << (63 - 53);
489
490         if (ppc_md.set_dawr)
491                 return ppc_md.set_dawr(dawr, dawrx);
492         mtspr(SPRN_DAWR, dawr);
493         mtspr(SPRN_DAWRX, dawrx);
494         return 0;
495 }
496
497 void __set_breakpoint(struct arch_hw_breakpoint *brk)
498 {
499         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
500
501         if (cpu_has_feature(CPU_FTR_DAWR))
502                 set_dawr(brk);
503         else
504                 set_dabr(brk);
505 }
506
507 void set_breakpoint(struct arch_hw_breakpoint *brk)
508 {
509         preempt_disable();
510         __set_breakpoint(brk);
511         preempt_enable();
512 }
513
514 #ifdef CONFIG_PPC64
515 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
516 #endif
517
518 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
519                               struct arch_hw_breakpoint *b)
520 {
521         if (a->address != b->address)
522                 return false;
523         if (a->type != b->type)
524                 return false;
525         if (a->len != b->len)
526                 return false;
527         return true;
528 }
529
530 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
531 static void tm_reclaim_thread(struct thread_struct *thr,
532                               struct thread_info *ti, uint8_t cause)
533 {
534         unsigned long msr_diff = 0;
535
536         /*
537          * If FP/VSX registers have been already saved to the
538          * thread_struct, move them to the transact_fp array.
539          * We clear the TIF_RESTORE_TM bit since after the reclaim
540          * the thread will no longer be transactional.
541          */
542         if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
543                 msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr;
544                 if (msr_diff & MSR_FP)
545                         memcpy(&thr->transact_fp, &thr->fp_state,
546                                sizeof(struct thread_fp_state));
547                 if (msr_diff & MSR_VEC)
548                         memcpy(&thr->transact_vr, &thr->vr_state,
549                                sizeof(struct thread_vr_state));
550                 clear_ti_thread_flag(ti, TIF_RESTORE_TM);
551                 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
552         }
553
554         /*
555          * Use the current MSR TM suspended bit to track if we have
556          * checkpointed state outstanding.
557          * On signal delivery, we'd normally reclaim the checkpointed
558          * state to obtain stack pointer (see:get_tm_stackpointer()).
559          * This will then directly return to userspace without going
560          * through __switch_to(). However, if the stack frame is bad,
561          * we need to exit this thread which calls __switch_to() which
562          * will again attempt to reclaim the already saved tm state.
563          * Hence we need to check that we've not already reclaimed
564          * this state.
565          * We do this using the current MSR, rather tracking it in
566          * some specific thread_struct bit, as it has the additional
567          * benifit of checking for a potential TM bad thing exception.
568          */
569         if (!MSR_TM_SUSPENDED(mfmsr()))
570                 return;
571
572         tm_reclaim(thr, thr->regs->msr, cause);
573
574         /* Having done the reclaim, we now have the checkpointed
575          * FP/VSX values in the registers.  These might be valid
576          * even if we have previously called enable_kernel_fp() or
577          * flush_fp_to_thread(), so update thr->regs->msr to
578          * indicate their current validity.
579          */
580         thr->regs->msr |= msr_diff;
581 }
582
583 void tm_reclaim_current(uint8_t cause)
584 {
585         tm_enable();
586         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
587 }
588
589 static inline void tm_reclaim_task(struct task_struct *tsk)
590 {
591         /* We have to work out if we're switching from/to a task that's in the
592          * middle of a transaction.
593          *
594          * In switching we need to maintain a 2nd register state as
595          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
596          * checkpointed (tbegin) state in ckpt_regs and saves the transactional
597          * (current) FPRs into oldtask->thread.transact_fpr[].
598          *
599          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
600          */
601         struct thread_struct *thr = &tsk->thread;
602
603         if (!thr->regs)
604                 return;
605
606         if (!MSR_TM_ACTIVE(thr->regs->msr))
607                 goto out_and_saveregs;
608
609         /* Stash the original thread MSR, as giveup_fpu et al will
610          * modify it.  We hold onto it to see whether the task used
611          * FP & vector regs.  If the TIF_RESTORE_TM flag is set,
612          * ckpt_regs.msr is already set.
613          */
614         if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
615                 thr->ckpt_regs.msr = thr->regs->msr;
616
617         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
618                  "ccr=%lx, msr=%lx, trap=%lx)\n",
619                  tsk->pid, thr->regs->nip,
620                  thr->regs->ccr, thr->regs->msr,
621                  thr->regs->trap);
622
623         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
624
625         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
626                  tsk->pid);
627
628 out_and_saveregs:
629         /* Always save the regs here, even if a transaction's not active.
630          * This context-switches a thread's TM info SPRs.  We do it here to
631          * be consistent with the restore path (in recheckpoint) which
632          * cannot happen later in _switch().
633          */
634         tm_save_sprs(thr);
635 }
636
637 extern void __tm_recheckpoint(struct thread_struct *thread,
638                               unsigned long orig_msr);
639
640 void tm_recheckpoint(struct thread_struct *thread,
641                      unsigned long orig_msr)
642 {
643         unsigned long flags;
644
645         /* We really can't be interrupted here as the TEXASR registers can't
646          * change and later in the trecheckpoint code, we have a userspace R1.
647          * So let's hard disable over this region.
648          */
649         local_irq_save(flags);
650         hard_irq_disable();
651
652         /* The TM SPRs are restored here, so that TEXASR.FS can be set
653          * before the trecheckpoint and no explosion occurs.
654          */
655         tm_restore_sprs(thread);
656
657         __tm_recheckpoint(thread, orig_msr);
658
659         local_irq_restore(flags);
660 }
661
662 static inline void tm_recheckpoint_new_task(struct task_struct *new)
663 {
664         unsigned long msr;
665
666         if (!cpu_has_feature(CPU_FTR_TM))
667                 return;
668
669         /* Recheckpoint the registers of the thread we're about to switch to.
670          *
671          * If the task was using FP, we non-lazily reload both the original and
672          * the speculative FP register states.  This is because the kernel
673          * doesn't see if/when a TM rollback occurs, so if we take an FP
674          * unavoidable later, we are unable to determine which set of FP regs
675          * need to be restored.
676          */
677         if (!new->thread.regs)
678                 return;
679
680         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
681                 tm_restore_sprs(&new->thread);
682                 return;
683         }
684         msr = new->thread.ckpt_regs.msr;
685         /* Recheckpoint to restore original checkpointed register state. */
686         TM_DEBUG("*** tm_recheckpoint of pid %d "
687                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
688                  new->pid, new->thread.regs->msr, msr);
689
690         /* This loads the checkpointed FP/VEC state, if used */
691         tm_recheckpoint(&new->thread, msr);
692
693         /* This loads the speculative FP/VEC state, if used */
694         if (msr & MSR_FP) {
695                 do_load_up_transact_fpu(&new->thread);
696                 new->thread.regs->msr |=
697                         (MSR_FP | new->thread.fpexc_mode);
698         }
699 #ifdef CONFIG_ALTIVEC
700         if (msr & MSR_VEC) {
701                 do_load_up_transact_altivec(&new->thread);
702                 new->thread.regs->msr |= MSR_VEC;
703         }
704 #endif
705         /* We may as well turn on VSX too since all the state is restored now */
706         if (msr & MSR_VSX)
707                 new->thread.regs->msr |= MSR_VSX;
708
709         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
710                  "(kernel msr 0x%lx)\n",
711                  new->pid, mfmsr());
712 }
713
714 static inline void __switch_to_tm(struct task_struct *prev)
715 {
716         if (cpu_has_feature(CPU_FTR_TM)) {
717                 tm_enable();
718                 tm_reclaim_task(prev);
719         }
720 }
721
722 /*
723  * This is called if we are on the way out to userspace and the
724  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
725  * FP and/or vector state and does so if necessary.
726  * If userspace is inside a transaction (whether active or
727  * suspended) and FP/VMX/VSX instructions have ever been enabled
728  * inside that transaction, then we have to keep them enabled
729  * and keep the FP/VMX/VSX state loaded while ever the transaction
730  * continues.  The reason is that if we didn't, and subsequently
731  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
732  * we don't know whether it's the same transaction, and thus we
733  * don't know which of the checkpointed state and the transactional
734  * state to use.
735  */
736 void restore_tm_state(struct pt_regs *regs)
737 {
738         unsigned long msr_diff;
739
740         clear_thread_flag(TIF_RESTORE_TM);
741         if (!MSR_TM_ACTIVE(regs->msr))
742                 return;
743
744         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
745         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
746         if (msr_diff & MSR_FP) {
747                 fp_enable();
748                 load_fp_state(&current->thread.fp_state);
749                 regs->msr |= current->thread.fpexc_mode;
750         }
751         if (msr_diff & MSR_VEC) {
752                 vec_enable();
753                 load_vr_state(&current->thread.vr_state);
754         }
755         regs->msr |= msr_diff;
756 }
757
758 #else
759 #define tm_recheckpoint_new_task(new)
760 #define __switch_to_tm(prev)
761 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
762
763 struct task_struct *__switch_to(struct task_struct *prev,
764         struct task_struct *new)
765 {
766         struct thread_struct *new_thread, *old_thread;
767         struct task_struct *last;
768 #ifdef CONFIG_PPC_BOOK3S_64
769         struct ppc64_tlb_batch *batch;
770 #endif
771
772         WARN_ON(!irqs_disabled());
773
774         /* Back up the TAR and DSCR across context switches.
775          * Note that the TAR is not available for use in the kernel.  (To
776          * provide this, the TAR should be backed up/restored on exception
777          * entry/exit instead, and be in pt_regs.  FIXME, this should be in
778          * pt_regs anyway (for debug).)
779          * Save the TAR and DSCR here before we do treclaim/trecheckpoint as
780          * these will change them.
781          */
782         save_early_sprs(&prev->thread);
783
784         __switch_to_tm(prev);
785
786 #ifdef CONFIG_SMP
787         /* avoid complexity of lazy save/restore of fpu
788          * by just saving it every time we switch out if
789          * this task used the fpu during the last quantum.
790          *
791          * If it tries to use the fpu again, it'll trap and
792          * reload its fp regs.  So we don't have to do a restore
793          * every switch, just a save.
794          *  -- Cort
795          */
796         if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
797                 giveup_fpu(prev);
798 #ifdef CONFIG_ALTIVEC
799         /*
800          * If the previous thread used altivec in the last quantum
801          * (thus changing altivec regs) then save them.
802          * We used to check the VRSAVE register but not all apps
803          * set it, so we don't rely on it now (and in fact we need
804          * to save & restore VSCR even if VRSAVE == 0).  -- paulus
805          *
806          * On SMP we always save/restore altivec regs just to avoid the
807          * complexity of changing processors.
808          *  -- Cort
809          */
810         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
811                 giveup_altivec(prev);
812 #endif /* CONFIG_ALTIVEC */
813 #ifdef CONFIG_VSX
814         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
815                 /* VMX and FPU registers are already save here */
816                 __giveup_vsx(prev);
817 #endif /* CONFIG_VSX */
818 #ifdef CONFIG_SPE
819         /*
820          * If the previous thread used spe in the last quantum
821          * (thus changing spe regs) then save them.
822          *
823          * On SMP we always save/restore spe regs just to avoid the
824          * complexity of changing processors.
825          */
826         if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
827                 giveup_spe(prev);
828 #endif /* CONFIG_SPE */
829
830 #else  /* CONFIG_SMP */
831 #ifdef CONFIG_ALTIVEC
832         /* Avoid the trap.  On smp this this never happens since
833          * we don't set last_task_used_altivec -- Cort
834          */
835         if (new->thread.regs && last_task_used_altivec == new)
836                 new->thread.regs->msr |= MSR_VEC;
837 #endif /* CONFIG_ALTIVEC */
838 #ifdef CONFIG_VSX
839         if (new->thread.regs && last_task_used_vsx == new)
840                 new->thread.regs->msr |= MSR_VSX;
841 #endif /* CONFIG_VSX */
842 #ifdef CONFIG_SPE
843         /* Avoid the trap.  On smp this this never happens since
844          * we don't set last_task_used_spe
845          */
846         if (new->thread.regs && last_task_used_spe == new)
847                 new->thread.regs->msr |= MSR_SPE;
848 #endif /* CONFIG_SPE */
849
850 #endif /* CONFIG_SMP */
851
852 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
853         switch_booke_debug_regs(&new->thread.debug);
854 #else
855 /*
856  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
857  * schedule DABR
858  */
859 #ifndef CONFIG_HAVE_HW_BREAKPOINT
860         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
861                 __set_breakpoint(&new->thread.hw_brk);
862 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
863 #endif
864
865
866         new_thread = &new->thread;
867         old_thread = &current->thread;
868
869 #ifdef CONFIG_PPC64
870         /*
871          * Collect processor utilization data per process
872          */
873         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
874                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
875                 long unsigned start_tb, current_tb;
876                 start_tb = old_thread->start_tb;
877                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
878                 old_thread->accum_tb += (current_tb - start_tb);
879                 new_thread->start_tb = current_tb;
880         }
881 #endif /* CONFIG_PPC64 */
882
883 #ifdef CONFIG_PPC_BOOK3S_64
884         batch = this_cpu_ptr(&ppc64_tlb_batch);
885         if (batch->active) {
886                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
887                 if (batch->index)
888                         __flush_tlb_pending(batch);
889                 batch->active = 0;
890         }
891 #endif /* CONFIG_PPC_BOOK3S_64 */
892
893         /*
894          * We can't take a PMU exception inside _switch() since there is a
895          * window where the kernel stack SLB and the kernel stack are out
896          * of sync. Hard disable here.
897          */
898         hard_irq_disable();
899
900         tm_recheckpoint_new_task(new);
901
902         last = _switch(old_thread, new_thread);
903
904 #ifdef CONFIG_PPC_BOOK3S_64
905         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
906                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
907                 batch = this_cpu_ptr(&ppc64_tlb_batch);
908                 batch->active = 1;
909         }
910 #endif /* CONFIG_PPC_BOOK3S_64 */
911
912         return last;
913 }
914
915 static int instructions_to_print = 16;
916
917 static void show_instructions(struct pt_regs *regs)
918 {
919         int i;
920         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
921                         sizeof(int));
922
923         printk("Instruction dump:");
924
925         for (i = 0; i < instructions_to_print; i++) {
926                 int instr;
927
928                 if (!(i % 8))
929                         printk("\n");
930
931 #if !defined(CONFIG_BOOKE)
932                 /* If executing with the IMMU off, adjust pc rather
933                  * than print XXXXXXXX.
934                  */
935                 if (!(regs->msr & MSR_IR))
936                         pc = (unsigned long)phys_to_virt(pc);
937 #endif
938
939                 if (!__kernel_text_address(pc) ||
940                      probe_kernel_address((unsigned int __user *)pc, instr)) {
941                         printk(KERN_CONT "XXXXXXXX ");
942                 } else {
943                         if (regs->nip == pc)
944                                 printk(KERN_CONT "<%08x> ", instr);
945                         else
946                                 printk(KERN_CONT "%08x ", instr);
947                 }
948
949                 pc += sizeof(int);
950         }
951
952         printk("\n");
953 }
954
955 static struct regbit {
956         unsigned long bit;
957         const char *name;
958 } msr_bits[] = {
959 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
960         {MSR_SF,        "SF"},
961         {MSR_HV,        "HV"},
962 #endif
963         {MSR_VEC,       "VEC"},
964         {MSR_VSX,       "VSX"},
965 #ifdef CONFIG_BOOKE
966         {MSR_CE,        "CE"},
967 #endif
968         {MSR_EE,        "EE"},
969         {MSR_PR,        "PR"},
970         {MSR_FP,        "FP"},
971         {MSR_ME,        "ME"},
972 #ifdef CONFIG_BOOKE
973         {MSR_DE,        "DE"},
974 #else
975         {MSR_SE,        "SE"},
976         {MSR_BE,        "BE"},
977 #endif
978         {MSR_IR,        "IR"},
979         {MSR_DR,        "DR"},
980         {MSR_PMM,       "PMM"},
981 #ifndef CONFIG_BOOKE
982         {MSR_RI,        "RI"},
983         {MSR_LE,        "LE"},
984 #endif
985         {0,             NULL}
986 };
987
988 static void printbits(unsigned long val, struct regbit *bits)
989 {
990         const char *sep = "";
991
992         printk("<");
993         for (; bits->bit; ++bits)
994                 if (val & bits->bit) {
995                         printk("%s%s", sep, bits->name);
996                         sep = ",";
997                 }
998         printk(">");
999 }
1000
1001 #ifdef CONFIG_PPC64
1002 #define REG             "%016lx"
1003 #define REGS_PER_LINE   4
1004 #define LAST_VOLATILE   13
1005 #else
1006 #define REG             "%08lx"
1007 #define REGS_PER_LINE   8
1008 #define LAST_VOLATILE   12
1009 #endif
1010
1011 void show_regs(struct pt_regs * regs)
1012 {
1013         int i, trap;
1014
1015         show_regs_print_info(KERN_DEFAULT);
1016
1017         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1018                regs->nip, regs->link, regs->ctr);
1019         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1020                regs, regs->trap, print_tainted(), init_utsname()->release);
1021         printk("MSR: "REG" ", regs->msr);
1022         printbits(regs->msr, msr_bits);
1023         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1024         trap = TRAP(regs);
1025         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1026                 printk("CFAR: "REG" ", regs->orig_gpr3);
1027         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1028 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1029                 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1030 #else
1031                 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1032 #endif
1033 #ifdef CONFIG_PPC64
1034         printk("SOFTE: %ld ", regs->softe);
1035 #endif
1036 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1037         if (MSR_TM_ACTIVE(regs->msr))
1038                 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1039 #endif
1040
1041         for (i = 0;  i < 32;  i++) {
1042                 if ((i % REGS_PER_LINE) == 0)
1043                         printk("\nGPR%02d: ", i);
1044                 printk(REG " ", regs->gpr[i]);
1045                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1046                         break;
1047         }
1048         printk("\n");
1049 #ifdef CONFIG_KALLSYMS
1050         /*
1051          * Lookup NIP late so we have the best change of getting the
1052          * above info out without failing
1053          */
1054         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1055         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1056 #endif
1057         show_stack(current, (unsigned long *) regs->gpr[1]);
1058         if (!user_mode(regs))
1059                 show_instructions(regs);
1060 }
1061
1062 void exit_thread(void)
1063 {
1064         discard_lazy_cpu_state();
1065 }
1066
1067 void flush_thread(void)
1068 {
1069         discard_lazy_cpu_state();
1070
1071 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1072         flush_ptrace_hw_breakpoint(current);
1073 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1074         set_debug_reg_defaults(&current->thread);
1075 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1076 }
1077
1078 void
1079 release_thread(struct task_struct *t)
1080 {
1081 }
1082
1083 /*
1084  * this gets called so that we can store coprocessor state into memory and
1085  * copy the current task into the new thread.
1086  */
1087 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1088 {
1089         flush_fp_to_thread(src);
1090         flush_altivec_to_thread(src);
1091         flush_vsx_to_thread(src);
1092         flush_spe_to_thread(src);
1093         /*
1094          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1095          * flush but it removes the checkpointed state from the current CPU and
1096          * transitions the CPU out of TM mode.  Hence we need to call
1097          * tm_recheckpoint_new_task() (on the same task) to restore the
1098          * checkpointed state back and the TM mode.
1099          */
1100         __switch_to_tm(src);
1101         tm_recheckpoint_new_task(src);
1102
1103         *dst = *src;
1104
1105         clear_task_ebb(dst);
1106
1107         return 0;
1108 }
1109
1110 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1111 {
1112 #ifdef CONFIG_PPC_STD_MMU_64
1113         unsigned long sp_vsid;
1114         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1115
1116         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1117                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1118                         << SLB_VSID_SHIFT_1T;
1119         else
1120                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1121                         << SLB_VSID_SHIFT;
1122         sp_vsid |= SLB_VSID_KERNEL | llp;
1123         p->thread.ksp_vsid = sp_vsid;
1124 #endif
1125 }
1126
1127 /*
1128  * Copy a thread..
1129  */
1130
1131 /*
1132  * Copy architecture-specific thread state
1133  */
1134 int copy_thread(unsigned long clone_flags, unsigned long usp,
1135                 unsigned long kthread_arg, struct task_struct *p)
1136 {
1137         struct pt_regs *childregs, *kregs;
1138         extern void ret_from_fork(void);
1139         extern void ret_from_kernel_thread(void);
1140         void (*f)(void);
1141         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1142
1143         /* Copy registers */
1144         sp -= sizeof(struct pt_regs);
1145         childregs = (struct pt_regs *) sp;
1146         if (unlikely(p->flags & PF_KTHREAD)) {
1147                 /* kernel thread */
1148                 struct thread_info *ti = (void *)task_stack_page(p);
1149                 memset(childregs, 0, sizeof(struct pt_regs));
1150                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1151                 /* function */
1152                 if (usp)
1153                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1154 #ifdef CONFIG_PPC64
1155                 clear_tsk_thread_flag(p, TIF_32BIT);
1156                 childregs->softe = 1;
1157 #endif
1158                 childregs->gpr[15] = kthread_arg;
1159                 p->thread.regs = NULL;  /* no user register state */
1160                 ti->flags |= _TIF_RESTOREALL;
1161                 f = ret_from_kernel_thread;
1162         } else {
1163                 /* user thread */
1164                 struct pt_regs *regs = current_pt_regs();
1165                 CHECK_FULL_REGS(regs);
1166                 *childregs = *regs;
1167                 if (usp)
1168                         childregs->gpr[1] = usp;
1169                 p->thread.regs = childregs;
1170                 childregs->gpr[3] = 0;  /* Result from fork() */
1171                 if (clone_flags & CLONE_SETTLS) {
1172 #ifdef CONFIG_PPC64
1173                         if (!is_32bit_task())
1174                                 childregs->gpr[13] = childregs->gpr[6];
1175                         else
1176 #endif
1177                                 childregs->gpr[2] = childregs->gpr[6];
1178                 }
1179
1180                 f = ret_from_fork;
1181         }
1182         sp -= STACK_FRAME_OVERHEAD;
1183
1184         /*
1185          * The way this works is that at some point in the future
1186          * some task will call _switch to switch to the new task.
1187          * That will pop off the stack frame created below and start
1188          * the new task running at ret_from_fork.  The new task will
1189          * do some house keeping and then return from the fork or clone
1190          * system call, using the stack frame created above.
1191          */
1192         ((unsigned long *)sp)[0] = 0;
1193         sp -= sizeof(struct pt_regs);
1194         kregs = (struct pt_regs *) sp;
1195         sp -= STACK_FRAME_OVERHEAD;
1196         p->thread.ksp = sp;
1197 #ifdef CONFIG_PPC32
1198         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1199                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1200 #endif
1201 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1202         p->thread.ptrace_bps[0] = NULL;
1203 #endif
1204
1205         p->thread.fp_save_area = NULL;
1206 #ifdef CONFIG_ALTIVEC
1207         p->thread.vr_save_area = NULL;
1208 #endif
1209
1210         setup_ksp_vsid(p, sp);
1211
1212 #ifdef CONFIG_PPC64 
1213         if (cpu_has_feature(CPU_FTR_DSCR)) {
1214                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1215                 p->thread.dscr = current->thread.dscr;
1216         }
1217         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1218                 p->thread.ppr = INIT_PPR;
1219 #endif
1220         kregs->nip = ppc_function_entry(f);
1221         return 0;
1222 }
1223
1224 /*
1225  * Set up a thread for executing a new program
1226  */
1227 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1228 {
1229 #ifdef CONFIG_PPC64
1230         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1231 #endif
1232
1233         /*
1234          * If we exec out of a kernel thread then thread.regs will not be
1235          * set.  Do it now.
1236          */
1237         if (!current->thread.regs) {
1238                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1239                 current->thread.regs = regs - 1;
1240         }
1241
1242         memset(regs->gpr, 0, sizeof(regs->gpr));
1243         regs->ctr = 0;
1244         regs->link = 0;
1245         regs->xer = 0;
1246         regs->ccr = 0;
1247         regs->gpr[1] = sp;
1248
1249         /*
1250          * We have just cleared all the nonvolatile GPRs, so make
1251          * FULL_REGS(regs) return true.  This is necessary to allow
1252          * ptrace to examine the thread immediately after exec.
1253          */
1254         regs->trap &= ~1UL;
1255
1256 #ifdef CONFIG_PPC32
1257         regs->mq = 0;
1258         regs->nip = start;
1259         regs->msr = MSR_USER;
1260 #else
1261         if (!is_32bit_task()) {
1262                 unsigned long entry;
1263
1264                 if (is_elf2_task()) {
1265                         /* Look ma, no function descriptors! */
1266                         entry = start;
1267
1268                         /*
1269                          * Ulrich says:
1270                          *   The latest iteration of the ABI requires that when
1271                          *   calling a function (at its global entry point),
1272                          *   the caller must ensure r12 holds the entry point
1273                          *   address (so that the function can quickly
1274                          *   establish addressability).
1275                          */
1276                         regs->gpr[12] = start;
1277                         /* Make sure that's restored on entry to userspace. */
1278                         set_thread_flag(TIF_RESTOREALL);
1279                 } else {
1280                         unsigned long toc;
1281
1282                         /* start is a relocated pointer to the function
1283                          * descriptor for the elf _start routine.  The first
1284                          * entry in the function descriptor is the entry
1285                          * address of _start and the second entry is the TOC
1286                          * value we need to use.
1287                          */
1288                         __get_user(entry, (unsigned long __user *)start);
1289                         __get_user(toc, (unsigned long __user *)start+1);
1290
1291                         /* Check whether the e_entry function descriptor entries
1292                          * need to be relocated before we can use them.
1293                          */
1294                         if (load_addr != 0) {
1295                                 entry += load_addr;
1296                                 toc   += load_addr;
1297                         }
1298                         regs->gpr[2] = toc;
1299                 }
1300                 regs->nip = entry;
1301                 regs->msr = MSR_USER64;
1302         } else {
1303                 regs->nip = start;
1304                 regs->gpr[2] = 0;
1305                 regs->msr = MSR_USER32;
1306         }
1307 #endif
1308         discard_lazy_cpu_state();
1309 #ifdef CONFIG_VSX
1310         current->thread.used_vsr = 0;
1311 #endif
1312         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1313         current->thread.fp_save_area = NULL;
1314 #ifdef CONFIG_ALTIVEC
1315         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1316         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1317         current->thread.vr_save_area = NULL;
1318         current->thread.vrsave = 0;
1319         current->thread.used_vr = 0;
1320 #endif /* CONFIG_ALTIVEC */
1321 #ifdef CONFIG_SPE
1322         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1323         current->thread.acc = 0;
1324         current->thread.spefscr = 0;
1325         current->thread.used_spe = 0;
1326 #endif /* CONFIG_SPE */
1327 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1328         if (cpu_has_feature(CPU_FTR_TM))
1329                 regs->msr |= MSR_TM;
1330         current->thread.tm_tfhar = 0;
1331         current->thread.tm_texasr = 0;
1332         current->thread.tm_tfiar = 0;
1333 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1334 }
1335 EXPORT_SYMBOL(start_thread);
1336
1337 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1338                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1339
1340 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1341 {
1342         struct pt_regs *regs = tsk->thread.regs;
1343
1344         /* This is a bit hairy.  If we are an SPE enabled  processor
1345          * (have embedded fp) we store the IEEE exception enable flags in
1346          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1347          * mode (asyn, precise, disabled) for 'Classic' FP. */
1348         if (val & PR_FP_EXC_SW_ENABLE) {
1349 #ifdef CONFIG_SPE
1350                 if (cpu_has_feature(CPU_FTR_SPE)) {
1351                         /*
1352                          * When the sticky exception bits are set
1353                          * directly by userspace, it must call prctl
1354                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1355                          * in the existing prctl settings) or
1356                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1357                          * the bits being set).  <fenv.h> functions
1358                          * saving and restoring the whole
1359                          * floating-point environment need to do so
1360                          * anyway to restore the prctl settings from
1361                          * the saved environment.
1362                          */
1363                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1364                         tsk->thread.fpexc_mode = val &
1365                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1366                         return 0;
1367                 } else {
1368                         return -EINVAL;
1369                 }
1370 #else
1371                 return -EINVAL;
1372 #endif
1373         }
1374
1375         /* on a CONFIG_SPE this does not hurt us.  The bits that
1376          * __pack_fe01 use do not overlap with bits used for
1377          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1378          * on CONFIG_SPE implementations are reserved so writing to
1379          * them does not change anything */
1380         if (val > PR_FP_EXC_PRECISE)
1381                 return -EINVAL;
1382         tsk->thread.fpexc_mode = __pack_fe01(val);
1383         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1384                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1385                         | tsk->thread.fpexc_mode;
1386         return 0;
1387 }
1388
1389 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1390 {
1391         unsigned int val;
1392
1393         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1394 #ifdef CONFIG_SPE
1395                 if (cpu_has_feature(CPU_FTR_SPE)) {
1396                         /*
1397                          * When the sticky exception bits are set
1398                          * directly by userspace, it must call prctl
1399                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1400                          * in the existing prctl settings) or
1401                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1402                          * the bits being set).  <fenv.h> functions
1403                          * saving and restoring the whole
1404                          * floating-point environment need to do so
1405                          * anyway to restore the prctl settings from
1406                          * the saved environment.
1407                          */
1408                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1409                         val = tsk->thread.fpexc_mode;
1410                 } else
1411                         return -EINVAL;
1412 #else
1413                 return -EINVAL;
1414 #endif
1415         else
1416                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1417         return put_user(val, (unsigned int __user *) adr);
1418 }
1419
1420 int set_endian(struct task_struct *tsk, unsigned int val)
1421 {
1422         struct pt_regs *regs = tsk->thread.regs;
1423
1424         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1425             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1426                 return -EINVAL;
1427
1428         if (regs == NULL)
1429                 return -EINVAL;
1430
1431         if (val == PR_ENDIAN_BIG)
1432                 regs->msr &= ~MSR_LE;
1433         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1434                 regs->msr |= MSR_LE;
1435         else
1436                 return -EINVAL;
1437
1438         return 0;
1439 }
1440
1441 int get_endian(struct task_struct *tsk, unsigned long adr)
1442 {
1443         struct pt_regs *regs = tsk->thread.regs;
1444         unsigned int val;
1445
1446         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1447             !cpu_has_feature(CPU_FTR_REAL_LE))
1448                 return -EINVAL;
1449
1450         if (regs == NULL)
1451                 return -EINVAL;
1452
1453         if (regs->msr & MSR_LE) {
1454                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1455                         val = PR_ENDIAN_LITTLE;
1456                 else
1457                         val = PR_ENDIAN_PPC_LITTLE;
1458         } else
1459                 val = PR_ENDIAN_BIG;
1460
1461         return put_user(val, (unsigned int __user *)adr);
1462 }
1463
1464 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1465 {
1466         tsk->thread.align_ctl = val;
1467         return 0;
1468 }
1469
1470 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1471 {
1472         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1473 }
1474
1475 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1476                                   unsigned long nbytes)
1477 {
1478         unsigned long stack_page;
1479         unsigned long cpu = task_cpu(p);
1480
1481         /*
1482          * Avoid crashing if the stack has overflowed and corrupted
1483          * task_cpu(p), which is in the thread_info struct.
1484          */
1485         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1486                 stack_page = (unsigned long) hardirq_ctx[cpu];
1487                 if (sp >= stack_page + sizeof(struct thread_struct)
1488                     && sp <= stack_page + THREAD_SIZE - nbytes)
1489                         return 1;
1490
1491                 stack_page = (unsigned long) softirq_ctx[cpu];
1492                 if (sp >= stack_page + sizeof(struct thread_struct)
1493                     && sp <= stack_page + THREAD_SIZE - nbytes)
1494                         return 1;
1495         }
1496         return 0;
1497 }
1498
1499 int validate_sp(unsigned long sp, struct task_struct *p,
1500                        unsigned long nbytes)
1501 {
1502         unsigned long stack_page = (unsigned long)task_stack_page(p);
1503
1504         if (sp >= stack_page + sizeof(struct thread_struct)
1505             && sp <= stack_page + THREAD_SIZE - nbytes)
1506                 return 1;
1507
1508         return valid_irq_stack(sp, p, nbytes);
1509 }
1510
1511 EXPORT_SYMBOL(validate_sp);
1512
1513 unsigned long get_wchan(struct task_struct *p)
1514 {
1515         unsigned long ip, sp;
1516         int count = 0;
1517
1518         if (!p || p == current || p->state == TASK_RUNNING)
1519                 return 0;
1520
1521         sp = p->thread.ksp;
1522         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1523                 return 0;
1524
1525         do {
1526                 sp = *(unsigned long *)sp;
1527                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1528                         return 0;
1529                 if (count > 0) {
1530                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1531                         if (!in_sched_functions(ip))
1532                                 return ip;
1533                 }
1534         } while (count++ < 16);
1535         return 0;
1536 }
1537
1538 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1539
1540 void show_stack(struct task_struct *tsk, unsigned long *stack)
1541 {
1542         unsigned long sp, ip, lr, newsp;
1543         int count = 0;
1544         int firstframe = 1;
1545 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1546         int curr_frame = current->curr_ret_stack;
1547         extern void return_to_handler(void);
1548         unsigned long rth = (unsigned long)return_to_handler;
1549 #endif
1550
1551         sp = (unsigned long) stack;
1552         if (tsk == NULL)
1553                 tsk = current;
1554         if (sp == 0) {
1555                 if (tsk == current)
1556                         sp = current_stack_pointer();
1557                 else
1558                         sp = tsk->thread.ksp;
1559         }
1560
1561         lr = 0;
1562         printk("Call Trace:\n");
1563         do {
1564                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1565                         return;
1566
1567                 stack = (unsigned long *) sp;
1568                 newsp = stack[0];
1569                 ip = stack[STACK_FRAME_LR_SAVE];
1570                 if (!firstframe || ip != lr) {
1571                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1572 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1573                         if ((ip == rth) && curr_frame >= 0) {
1574                                 printk(" (%pS)",
1575                                        (void *)current->ret_stack[curr_frame].ret);
1576                                 curr_frame--;
1577                         }
1578 #endif
1579                         if (firstframe)
1580                                 printk(" (unreliable)");
1581                         printk("\n");
1582                 }
1583                 firstframe = 0;
1584
1585                 /*
1586                  * See if this is an exception frame.
1587                  * We look for the "regshere" marker in the current frame.
1588                  */
1589                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1590                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1591                         struct pt_regs *regs = (struct pt_regs *)
1592                                 (sp + STACK_FRAME_OVERHEAD);
1593                         lr = regs->link;
1594                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1595                                regs->trap, (void *)regs->nip, (void *)lr);
1596                         firstframe = 1;
1597                 }
1598
1599                 sp = newsp;
1600         } while (count++ < kstack_depth_to_print);
1601 }
1602
1603 #ifdef CONFIG_PPC64
1604 /* Called with hard IRQs off */
1605 void notrace __ppc64_runlatch_on(void)
1606 {
1607         struct thread_info *ti = current_thread_info();
1608         unsigned long ctrl;
1609
1610         ctrl = mfspr(SPRN_CTRLF);
1611         ctrl |= CTRL_RUNLATCH;
1612         mtspr(SPRN_CTRLT, ctrl);
1613
1614         ti->local_flags |= _TLF_RUNLATCH;
1615 }
1616
1617 /* Called with hard IRQs off */
1618 void notrace __ppc64_runlatch_off(void)
1619 {
1620         struct thread_info *ti = current_thread_info();
1621         unsigned long ctrl;
1622
1623         ti->local_flags &= ~_TLF_RUNLATCH;
1624
1625         ctrl = mfspr(SPRN_CTRLF);
1626         ctrl &= ~CTRL_RUNLATCH;
1627         mtspr(SPRN_CTRLT, ctrl);
1628 }
1629 #endif /* CONFIG_PPC64 */
1630
1631 unsigned long arch_align_stack(unsigned long sp)
1632 {
1633         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1634                 sp -= get_random_int() & ~PAGE_MASK;
1635         return sp & ~0xf;
1636 }
1637
1638 static inline unsigned long brk_rnd(void)
1639 {
1640         unsigned long rnd = 0;
1641
1642         /* 8MB for 32bit, 1GB for 64bit */
1643         if (is_32bit_task())
1644                 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
1645         else
1646                 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
1647
1648         return rnd << PAGE_SHIFT;
1649 }
1650
1651 unsigned long arch_randomize_brk(struct mm_struct *mm)
1652 {
1653         unsigned long base = mm->brk;
1654         unsigned long ret;
1655
1656 #ifdef CONFIG_PPC_STD_MMU_64
1657         /*
1658          * If we are using 1TB segments and we are allowed to randomise
1659          * the heap, we can put it above 1TB so it is backed by a 1TB
1660          * segment. Otherwise the heap will be in the bottom 1TB
1661          * which always uses 256MB segments and this may result in a
1662          * performance penalty.
1663          */
1664         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1665                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1666 #endif
1667
1668         ret = PAGE_ALIGN(base + brk_rnd());
1669
1670         if (ret < mm->brk)
1671                 return mm->brk;
1672
1673         return ret;
1674 }
1675