2 * Boot code and exception vectors for Book3E processors
4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/threads.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cputable.h>
18 #include <asm/setup.h>
19 #include <asm/thread_info.h>
20 #include <asm/reg_a2.h>
21 #include <asm/exception-64e.h>
23 #include <asm/irqflags.h>
24 #include <asm/ptrace.h>
25 #include <asm/ppc-opcode.h>
27 #include <asm/hw_irq.h>
28 #include <asm/kvm_asm.h>
29 #include <asm/kvm_booke_hv_asm.h>
31 /* XXX This will ultimately add space for a special exception save
32 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
33 * when taking special interrupts. For now we don't support that,
34 * special interrupts from within a non-standard level will probably
37 #define SPECIAL_EXC_FRAME_SIZE INT_FRAME_SIZE
39 /* Exception prolog code for all exceptions */
40 #define EXCEPTION_PROLOG(n, intnum, type, addition) \
41 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
42 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
43 std r10,PACA_EX##type+EX_R10(r13); \
44 std r11,PACA_EX##type+EX_R11(r13); \
45 PROLOG_STORE_RESTORE_SCRATCH_##type; \
46 mfcr r10; /* save CR */ \
47 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
48 DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \
49 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
50 addition; /* additional code for that exc. */ \
51 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
52 type##_SET_KSTACK; /* get special stack if necessary */\
53 andi. r10,r11,MSR_PR; /* save stack pointer */ \
54 beq 1f; /* branch around if supervisor */ \
55 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
56 1: cmpdi cr1,r1,0; /* check if SP makes sense */ \
57 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
58 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
60 /* Exception type-specific macros */
61 #define GEN_SET_KSTACK \
62 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
63 #define SPRN_GEN_SRR0 SPRN_SRR0
64 #define SPRN_GEN_SRR1 SPRN_SRR1
66 #define GDBELL_SET_KSTACK GEN_SET_KSTACK
67 #define SPRN_GDBELL_SRR0 SPRN_GSRR0
68 #define SPRN_GDBELL_SRR1 SPRN_GSRR1
70 #define CRIT_SET_KSTACK \
71 ld r1,PACA_CRIT_STACK(r13); \
72 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
73 #define SPRN_CRIT_SRR0 SPRN_CSRR0
74 #define SPRN_CRIT_SRR1 SPRN_CSRR1
76 #define DBG_SET_KSTACK \
77 ld r1,PACA_DBG_STACK(r13); \
78 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
79 #define SPRN_DBG_SRR0 SPRN_DSRR0
80 #define SPRN_DBG_SRR1 SPRN_DSRR1
82 #define MC_SET_KSTACK \
83 ld r1,PACA_MC_STACK(r13); \
84 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
85 #define SPRN_MC_SRR0 SPRN_MCSRR0
86 #define SPRN_MC_SRR1 SPRN_MCSRR1
88 #define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \
89 EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n))
91 #define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \
92 EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n))
94 #define DBG_EXCEPTION_PROLOG(n, intnum, addition) \
95 EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n))
97 #define MC_EXCEPTION_PROLOG(n, intnum, addition) \
98 EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n))
100 #define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \
101 EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n))
104 * Store user-visible scratch in PACA exception slots and restore proper value
106 #define PROLOG_STORE_RESTORE_SCRATCH_GEN
107 #define PROLOG_STORE_RESTORE_SCRATCH_GDBELL
108 #define PROLOG_STORE_RESTORE_SCRATCH_DBG
109 #define PROLOG_STORE_RESTORE_SCRATCH_MC
111 #define PROLOG_STORE_RESTORE_SCRATCH_CRIT \
112 mfspr r10,SPRN_SPRG_CRIT_SCRATCH; /* get r13 */ \
113 std r10,PACA_EXCRIT+EX_R13(r13); \
114 ld r11,PACA_SPRG3(r13); \
115 mtspr SPRN_SPRG_CRIT_SCRATCH,r11;
117 /* Variants of the "addition" argument for the prolog
119 #define PROLOG_ADDITION_NONE_GEN(n)
120 #define PROLOG_ADDITION_NONE_GDBELL(n)
121 #define PROLOG_ADDITION_NONE_CRIT(n)
122 #define PROLOG_ADDITION_NONE_DBG(n)
123 #define PROLOG_ADDITION_NONE_MC(n)
125 #define PROLOG_ADDITION_MASKABLE_GEN(n) \
126 lbz r10,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
127 cmpwi cr0,r10,0; /* yes -> go out of line */ \
128 beq masked_interrupt_book3e_##n
130 #define PROLOG_ADDITION_2REGS_GEN(n) \
131 std r14,PACA_EXGEN+EX_R14(r13); \
132 std r15,PACA_EXGEN+EX_R15(r13)
134 #define PROLOG_ADDITION_1REG_GEN(n) \
135 std r14,PACA_EXGEN+EX_R14(r13);
137 #define PROLOG_ADDITION_2REGS_CRIT(n) \
138 std r14,PACA_EXCRIT+EX_R14(r13); \
139 std r15,PACA_EXCRIT+EX_R15(r13)
141 #define PROLOG_ADDITION_2REGS_DBG(n) \
142 std r14,PACA_EXDBG+EX_R14(r13); \
143 std r15,PACA_EXDBG+EX_R15(r13)
145 #define PROLOG_ADDITION_2REGS_MC(n) \
146 std r14,PACA_EXMC+EX_R14(r13); \
147 std r15,PACA_EXMC+EX_R15(r13)
150 /* Core exception code for all exceptions except TLB misses.
151 * XXX: Needs to make SPRN_SPRG_GEN depend on exception type
153 #define EXCEPTION_COMMON(n, excf, ints) \
155 std r0,GPR0(r1); /* save r0 in stackframe */ \
156 std r2,GPR2(r1); /* save r2 in stackframe */ \
157 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
158 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
159 std r9,GPR9(r1); /* save r9 in stackframe */ \
160 std r10,_NIP(r1); /* save SRR0 to stackframe */ \
161 std r11,_MSR(r1); /* save SRR1 to stackframe */ \
162 beq 2f; /* if from kernel mode */ \
163 ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \
164 2: ld r3,excf+EX_R10(r13); /* get back r10 */ \
165 ld r4,excf+EX_R11(r13); /* get back r11 */ \
166 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */ \
167 std r12,GPR12(r1); /* save r12 in stackframe */ \
168 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
169 mflr r6; /* save LR in stackframe */ \
170 mfctr r7; /* save CTR in stackframe */ \
171 mfspr r8,SPRN_XER; /* save XER in stackframe */ \
172 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
173 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \
174 lbz r11,PACASOFTIRQEN(r13); /* get current IRQ softe */ \
175 ld r12,exception_marker@toc(r2); \
177 std r3,GPR10(r1); /* save r10 to stackframe */ \
178 std r4,GPR11(r1); /* save r11 to stackframe */ \
179 std r5,GPR13(r1); /* save it to stackframe */ \
183 li r3,(n)+1; /* indicate partial regs in trap */ \
184 std r9,0(r1); /* store stack frame back link */ \
185 std r10,_CCR(r1); /* store orig CR in stackframe */ \
186 std r9,GPR1(r1); /* store stack frame back link */ \
187 std r11,SOFTE(r1); /* and save it to stackframe */ \
188 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
189 std r3,_TRAP(r1); /* set trap number */ \
190 std r0,RESULT(r1); /* clear regs->result */ \
193 /* Variants for the "ints" argument. This one does nothing when we want
194 * to keep interrupts in their original state
198 /* This second version is meant for exceptions that don't immediately
199 * hard-enable. We set a bit in paca->irq_happened to ensure that
200 * a subsequent call to arch_local_irq_restore() will properly
201 * hard-enable and avoid the fast-path
203 #define INTS_DISABLE SOFT_DISABLE_INTS(r3,r4)
205 /* This is called by exceptions that used INTS_KEEP (that did not touch
206 * irq indicators in the PACA). This will restore MSR:EE to it's previous
209 * XXX In the long run, we may want to open-code it in order to separate the
210 * load from the wrtee, thus limiting the latency caused by the dependency
211 * but at this point, I'll favor code clarity until we have a near to final
214 #define INTS_RESTORE_HARD \
218 /* XXX FIXME: Restore r14/r15 when necessary */
219 #define BAD_STACK_TRAMPOLINE(n) \
220 exc_##n##_bad_stack: \
221 li r1,(n); /* get exception number */ \
222 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
223 b bad_stack_book3e; /* bad stack error */
225 /* WARNING: If you change the layout of this stub, make sure you chcek
226 * the debug exception handler which handles single stepping
227 * into exceptions from userspace, and the MM code in
228 * arch/powerpc/mm/tlb_nohash.c which patches the branch here
229 * and would need to be updated if that branch is moved
231 #define EXCEPTION_STUB(loc, label) \
232 . = interrupt_base_book3e + loc; \
233 nop; /* To make debug interrupts happy */ \
234 b exc_##label##_book3e;
244 /* Used by asynchronous interrupt that may happen in the idle loop.
246 * This check if the thread was in the idle loop, and if yes, returns
247 * to the caller rather than the PC. This is to avoid a race if
248 * interrupts happen before the wait instruction.
250 #define CHECK_NAPPING() \
251 CURRENT_THREAD_INFO(r11, r1); \
252 ld r10,TI_LOCAL_FLAGS(r11); \
253 andi. r9,r10,_TLF_NAPPING; \
256 rlwinm r7,r10,0,~_TLF_NAPPING; \
258 std r7,TI_LOCAL_FLAGS(r11); \
262 #define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \
263 START_EXCEPTION(label); \
264 NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
265 EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE) \
268 addi r3,r1,STACK_FRAME_OVERHEAD; \
270 b .ret_from_except_lite;
272 /* This value is used to mark exception frames on the stack. */
275 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
279 * And here we have the exception vectors !
284 .globl interrupt_base_book3e
285 interrupt_base_book3e: /* fake trap */
286 EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */
287 EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */
288 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
289 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
290 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
291 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
292 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
293 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
294 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
295 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
296 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
297 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
298 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
299 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
300 EXCEPTION_STUB(0x1c0, data_tlb_miss)
301 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
302 EXCEPTION_STUB(0x260, perfmon)
303 EXCEPTION_STUB(0x280, doorbell)
304 EXCEPTION_STUB(0x2a0, doorbell_crit)
305 EXCEPTION_STUB(0x2c0, guest_doorbell)
306 EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
307 EXCEPTION_STUB(0x300, hypercall)
308 EXCEPTION_STUB(0x320, ehpriv)
310 .globl interrupt_end_book3e
311 interrupt_end_book3e:
313 /* Critical Input Interrupt */
314 START_EXCEPTION(critical_input);
315 CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
316 PROLOG_ADDITION_NONE)
317 // EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE)
318 // bl special_reg_save_crit
320 // addi r3,r1,STACK_FRAME_OVERHEAD
321 // bl .critical_exception
322 // b ret_from_crit_except
325 /* Machine Check Interrupt */
326 START_EXCEPTION(machine_check);
327 MC_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_MACHINE_CHECK,
328 PROLOG_ADDITION_NONE)
329 // EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE)
330 // bl special_reg_save_mc
331 // addi r3,r1,STACK_FRAME_OVERHEAD
333 // bl .machine_check_exception
334 // b ret_from_mc_except
337 /* Data Storage Interrupt */
338 START_EXCEPTION(data_storage)
339 NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
340 PROLOG_ADDITION_2REGS)
343 EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_DISABLE)
344 b storage_fault_common
346 /* Instruction Storage Interrupt */
347 START_EXCEPTION(instruction_storage);
348 NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
349 PROLOG_ADDITION_2REGS)
352 EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_DISABLE)
353 b storage_fault_common
355 /* External Input Interrupt */
356 MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
357 external_input, .do_IRQ, ACK_NONE)
360 START_EXCEPTION(alignment);
361 NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
362 PROLOG_ADDITION_2REGS)
365 EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
366 b alignment_more /* no room, go out of line */
368 /* Program Interrupt */
369 START_EXCEPTION(program);
370 NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
371 PROLOG_ADDITION_1REG)
373 EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE)
375 addi r3,r1,STACK_FRAME_OVERHEAD
376 ld r14,PACA_EXGEN+EX_R14(r13)
378 bl .program_check_exception
381 /* Floating Point Unavailable Interrupt */
382 START_EXCEPTION(fp_unavailable);
383 NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
384 PROLOG_ADDITION_NONE)
385 /* we can probably do a shorter exception entry for that one... */
386 EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
391 b fast_exception_return
394 addi r3,r1,STACK_FRAME_OVERHEAD
395 bl .kernel_fp_unavailable_exception
398 /* Decrementer Interrupt */
399 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
400 decrementer, .timer_interrupt, ACK_DEC)
402 /* Fixed Interval Timer Interrupt */
403 MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
404 fixed_interval, .unknown_exception, ACK_FIT)
406 /* Watchdog Timer Interrupt */
407 START_EXCEPTION(watchdog);
408 CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
409 PROLOG_ADDITION_NONE)
410 // EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE)
411 // bl special_reg_save_crit
413 // addi r3,r1,STACK_FRAME_OVERHEAD
414 // bl .unknown_exception
415 // b ret_from_crit_except
418 /* System Call Interrupt */
419 START_EXCEPTION(system_call)
420 mr r9,r13 /* keep a copy of userland r13 */
421 mfspr r11,SPRN_SRR0 /* get return address */
422 mfspr r12,SPRN_SRR1 /* get previous MSR */
423 mfspr r13,SPRN_SPRG_PACA /* get our PACA */
426 /* Auxiliary Processor Unavailable Interrupt */
427 START_EXCEPTION(ap_unavailable);
428 NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
429 PROLOG_ADDITION_NONE)
430 EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_DISABLE)
432 addi r3,r1,STACK_FRAME_OVERHEAD
433 bl .unknown_exception
436 /* Debug exception as a critical interrupt*/
437 START_EXCEPTION(debug_crit);
438 CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
439 PROLOG_ADDITION_2REGS)
442 * If there is a single step or branch-taken exception in an
443 * exception entry sequence, it was probably meant to apply to
444 * the code where the exception occurred (since exception entry
445 * doesn't turn off DE automatically). We simulate the effect
446 * of turning off DE on entry to an exception handler by turning
447 * off DE in the CSRR1 value and clearing the debug status.
450 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
451 andis. r15,r14,DBSR_IC@h
454 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
455 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
461 /* here it looks like we got an inappropriate debug exception. */
462 lis r14,DBSR_IC@h /* clear the IC event */
463 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
466 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */
467 ld r1,PACA_EXCRIT+EX_R1(r13)
468 ld r14,PACA_EXCRIT+EX_R14(r13)
469 ld r15,PACA_EXCRIT+EX_R15(r13)
471 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */
472 ld r11,PACA_EXCRIT+EX_R11(r13)
473 ld r13,PACA_EXCRIT+EX_R13(r13)
476 /* Normal debug exception */
477 /* XXX We only handle coming from userspace for now since we can't
478 * quite save properly an interrupted kernel state yet
480 1: andi. r14,r11,MSR_PR; /* check for userspace again */
481 beq kernel_dbg_exc; /* if from kernel mode */
483 /* Now we mash up things to make it look like we are coming on a
486 ld r15,PACA_EXCRIT+EX_R13(r13)
487 mtspr SPRN_SPRG_GEN_SCRATCH,r15
489 EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE)
491 addi r3,r1,STACK_FRAME_OVERHEAD
493 ld r14,PACA_EXCRIT+EX_R14(r13)
494 ld r15,PACA_EXCRIT+EX_R15(r13)
502 /* Debug exception as a debug interrupt*/
503 START_EXCEPTION(debug_debug);
504 DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
505 PROLOG_ADDITION_2REGS)
508 * If there is a single step or branch-taken exception in an
509 * exception entry sequence, it was probably meant to apply to
510 * the code where the exception occurred (since exception entry
511 * doesn't turn off DE automatically). We simulate the effect
512 * of turning off DE on entry to an exception handler by turning
513 * off DE in the DSRR1 value and clearing the debug status.
516 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
517 andis. r15,r14,DBSR_IC@h
520 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
521 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
527 /* here it looks like we got an inappropriate debug exception. */
528 lis r14,DBSR_IC@h /* clear the IC event */
529 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
532 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
533 ld r1,PACA_EXDBG+EX_R1(r13)
534 ld r14,PACA_EXDBG+EX_R14(r13)
535 ld r15,PACA_EXDBG+EX_R15(r13)
537 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
538 ld r11,PACA_EXDBG+EX_R11(r13)
539 mfspr r13,SPRN_SPRG_DBG_SCRATCH
542 /* Normal debug exception */
543 /* XXX We only handle coming from userspace for now since we can't
544 * quite save properly an interrupted kernel state yet
546 1: andi. r14,r11,MSR_PR; /* check for userspace again */
547 beq kernel_dbg_exc; /* if from kernel mode */
549 /* Now we mash up things to make it look like we are coming on a
552 mfspr r15,SPRN_SPRG_DBG_SCRATCH
553 mtspr SPRN_SPRG_GEN_SCRATCH,r15
555 EXCEPTION_COMMON(0xd08, PACA_EXDBG, INTS_DISABLE)
557 addi r3,r1,STACK_FRAME_OVERHEAD
559 ld r14,PACA_EXDBG+EX_R14(r13)
560 ld r15,PACA_EXDBG+EX_R15(r13)
565 START_EXCEPTION(perfmon);
566 NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
567 PROLOG_ADDITION_NONE)
568 EXCEPTION_COMMON(0x260, PACA_EXGEN, INTS_DISABLE)
569 addi r3,r1,STACK_FRAME_OVERHEAD
570 bl .performance_monitor_exception
571 b .ret_from_except_lite
573 /* Doorbell interrupt */
574 MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
575 doorbell, .doorbell_exception, ACK_NONE)
577 /* Doorbell critical Interrupt */
578 START_EXCEPTION(doorbell_crit);
579 CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
580 PROLOG_ADDITION_NONE)
581 // EXCEPTION_COMMON(0x2a0, PACA_EXCRIT, INTS_DISABLE)
582 // bl special_reg_save_crit
584 // addi r3,r1,STACK_FRAME_OVERHEAD
585 // bl .doorbell_critical_exception
586 // b ret_from_crit_except
590 * Guest doorbell interrupt
591 * This general exception use GSRRx save/restore registers
593 START_EXCEPTION(guest_doorbell);
594 GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL,
595 PROLOG_ADDITION_NONE)
596 EXCEPTION_COMMON(0x2c0, PACA_EXGEN, INTS_KEEP)
597 addi r3,r1,STACK_FRAME_OVERHEAD
600 bl .unknown_exception
603 /* Guest Doorbell critical Interrupt */
604 START_EXCEPTION(guest_doorbell_crit);
605 CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
606 PROLOG_ADDITION_NONE)
607 // EXCEPTION_COMMON(0x2e0, PACA_EXCRIT, INTS_DISABLE)
608 // bl special_reg_save_crit
610 // addi r3,r1,STACK_FRAME_OVERHEAD
611 // bl .guest_doorbell_critical_exception
612 // b ret_from_crit_except
615 /* Hypervisor call */
616 START_EXCEPTION(hypercall);
617 NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
618 PROLOG_ADDITION_NONE)
619 EXCEPTION_COMMON(0x310, PACA_EXGEN, INTS_KEEP)
620 addi r3,r1,STACK_FRAME_OVERHEAD
623 bl .unknown_exception
626 /* Embedded Hypervisor priviledged */
627 START_EXCEPTION(ehpriv);
628 NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
629 PROLOG_ADDITION_NONE)
630 EXCEPTION_COMMON(0x320, PACA_EXGEN, INTS_KEEP)
631 addi r3,r1,STACK_FRAME_OVERHEAD
634 bl .unknown_exception
638 * An interrupt came in while soft-disabled; We mark paca->irq_happened
639 * accordingly and if the interrupt is level sensitive, we hard disable
642 .macro masked_interrupt_book3e paca_irq full_mask
643 lbz r10,PACAIRQHAPPENED(r13)
644 ori r10,r10,\paca_irq
645 stb r10,PACAIRQHAPPENED(r13)
648 rldicl r10,r11,48,1 /* clear MSR_EE */
653 lwz r11,PACA_EXGEN+EX_CR(r13)
655 ld r10,PACA_EXGEN+EX_R10(r13)
656 ld r11,PACA_EXGEN+EX_R11(r13)
657 mfspr r13,SPRN_SPRG_GEN_SCRATCH
662 masked_interrupt_book3e_0x500:
663 // XXX When adding support for EPR, use PACA_IRQ_EE_EDGE
664 masked_interrupt_book3e PACA_IRQ_EE 1
666 masked_interrupt_book3e_0x900:
668 masked_interrupt_book3e PACA_IRQ_DEC 0
670 masked_interrupt_book3e_0x980:
672 masked_interrupt_book3e PACA_IRQ_DEC 0
674 masked_interrupt_book3e_0x280:
675 masked_interrupt_book3e_0x2c0:
676 masked_interrupt_book3e PACA_IRQ_DBELL 0
679 * Called from arch_local_irq_enable when an interrupt needs
680 * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280
681 * to indicate the kind of interrupt. MSR:EE is already off.
682 * We generate a stackframe like if a real interrupt had happened.
684 * Note: While MSR:EE is off, we need to make sure that _MSR
685 * in the generated frame has EE set to 1 or the exception
686 * handler will not properly re-enable them.
688 _GLOBAL(__replay_interrupt)
689 /* We are going to jump to the exception common code which
690 * will retrieve various register values from the PACA which
691 * we don't give a damn about.
696 mtspr SPRN_SPRG_GEN_SCRATCH,r13;
697 std r1,PACA_EXGEN+EX_R1(r13);
698 stw r4,PACA_EXGEN+EX_CR(r13);
700 subi r1,r1,INT_FRAME_SIZE;
711 * This is called from 0x300 and 0x400 handlers after the prologs with
712 * r14 and r15 containing the fault address and error code, with the
713 * original values stashed away in the PACA
715 storage_fault_common:
718 addi r3,r1,STACK_FRAME_OVERHEAD
721 ld r14,PACA_EXGEN+EX_R14(r13)
722 ld r15,PACA_EXGEN+EX_R15(r13)
726 b .ret_from_except_lite
729 addi r3,r1,STACK_FRAME_OVERHEAD
735 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
741 addi r3,r1,STACK_FRAME_OVERHEAD
742 ld r14,PACA_EXGEN+EX_R14(r13)
743 ld r15,PACA_EXGEN+EX_R15(r13)
746 bl .alignment_exception
750 * We branch here from entry_64.S for the last stage of the exception
751 * return code path. MSR:EE is expected to be off at that point
753 _GLOBAL(exception_return_book3e)
756 /* This is the return from load_up_fpu fast path which could do with
757 * less GPR restores in fact, but for now we have a single return path
759 .globl fast_exception_return
760 fast_exception_return:
768 ACCOUNT_CPU_USER_EXIT(r10, r11)
771 1: stdcx. r0,0,r1 /* to clear the reservation */
785 mtspr SPRN_SPRG_GEN_SCRATCH,r0
787 std r10,PACA_EXGEN+EX_R10(r13);
788 std r11,PACA_EXGEN+EX_R11(r13);
795 ld r10,PACA_EXGEN+EX_R10(r13)
796 ld r11,PACA_EXGEN+EX_R11(r13)
797 mfspr r13,SPRN_SPRG_GEN_SCRATCH
801 * Trampolines used when spotting a bad kernel stack pointer in
802 * the exception entry code.
804 * TODO: move some bits like SRR0 read to trampoline, pass PACA
805 * index around, etc... to handle crit & mcheck
807 BAD_STACK_TRAMPOLINE(0x000)
808 BAD_STACK_TRAMPOLINE(0x100)
809 BAD_STACK_TRAMPOLINE(0x200)
810 BAD_STACK_TRAMPOLINE(0x260)
811 BAD_STACK_TRAMPOLINE(0x280)
812 BAD_STACK_TRAMPOLINE(0x2a0)
813 BAD_STACK_TRAMPOLINE(0x2c0)
814 BAD_STACK_TRAMPOLINE(0x2e0)
815 BAD_STACK_TRAMPOLINE(0x300)
816 BAD_STACK_TRAMPOLINE(0x310)
817 BAD_STACK_TRAMPOLINE(0x320)
818 BAD_STACK_TRAMPOLINE(0x400)
819 BAD_STACK_TRAMPOLINE(0x500)
820 BAD_STACK_TRAMPOLINE(0x600)
821 BAD_STACK_TRAMPOLINE(0x700)
822 BAD_STACK_TRAMPOLINE(0x800)
823 BAD_STACK_TRAMPOLINE(0x900)
824 BAD_STACK_TRAMPOLINE(0x980)
825 BAD_STACK_TRAMPOLINE(0x9f0)
826 BAD_STACK_TRAMPOLINE(0xa00)
827 BAD_STACK_TRAMPOLINE(0xb00)
828 BAD_STACK_TRAMPOLINE(0xc00)
829 BAD_STACK_TRAMPOLINE(0xd00)
830 BAD_STACK_TRAMPOLINE(0xd08)
831 BAD_STACK_TRAMPOLINE(0xe00)
832 BAD_STACK_TRAMPOLINE(0xf00)
833 BAD_STACK_TRAMPOLINE(0xf20)
835 .globl bad_stack_book3e
837 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
838 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */
839 ld r1,PACAEMERGSP(r13)
840 subi r1,r1,64+INT_FRAME_SIZE
843 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
844 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
851 std r0,GPR0(r1); /* save r0 in stackframe */ \
852 std r2,GPR2(r1); /* save r2 in stackframe */ \
853 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
854 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
855 std r9,GPR9(r1); /* save r9 in stackframe */ \
856 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
857 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
858 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
859 std r3,GPR10(r1); /* save r10 to stackframe */ \
860 std r4,GPR11(r1); /* save r11 to stackframe */ \
861 std r12,GPR12(r1); /* save r12 in stackframe */ \
862 std r5,GPR13(r1); /* save it to stackframe */ \
871 lhz r12,PACA_TRAP_SAVE(r13)
873 addi r11,r1,INT_FRAME_SIZE
878 1: addi r3,r1,STACK_FRAME_OVERHEAD
883 * Setup the initial TLB for a core. This current implementation
884 * assume that whatever we are running off will not conflict with
885 * the new mapping at PAGE_OFFSET.
887 _GLOBAL(initial_tlb_book3e)
889 /* Look for the first TLB with IPROT set */
890 mfspr r4,SPRN_TLB0CFG
891 andi. r3,r4,TLBnCFG_IPROT
892 lis r3,MAS0_TLBSEL(0)@h
895 mfspr r4,SPRN_TLB1CFG
896 andi. r3,r4,TLBnCFG_IPROT
897 lis r3,MAS0_TLBSEL(1)@h
900 mfspr r4,SPRN_TLB2CFG
901 andi. r3,r4,TLBnCFG_IPROT
902 lis r3,MAS0_TLBSEL(2)@h
905 lis r3,MAS0_TLBSEL(3)@h
906 mfspr r4,SPRN_TLB3CFG
910 andi. r5,r4,TLBnCFG_HES
913 mflr r8 /* save LR */
914 /* 1. Find the index of the entry we're executing in
916 * r3 = MAS0_TLBSEL (for the iprot array)
919 bl invstr /* Find our address */
920 invstr: mflr r6 /* Make it accessible */
922 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
927 tlbsx 0,r6 /* search MSR[IS], SPID=PID */
930 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
932 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
933 oris r7,r7,MAS1_IPROT@h
937 /* 2. Invalidate all entries except the entry we're executing in
939 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
941 * r5 = ESEL of entry we are running in
943 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
944 li r6,0 /* Set Entry counter to 0 */
945 1: mr r7,r3 /* Set MAS0(TLBSEL) */
946 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
950 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
952 beq skpinv /* Dont update the current execution TLB */
956 skpinv: addi r6,r6,1 /* Increment */
957 cmpw r6,r4 /* Are we done? */
958 bne 1b /* If not, repeat */
960 /* Invalidate all TLBs */
965 /* 3. Setup a temp mapping and jump to it
967 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
968 * r5 = ESEL of entry we are running in
970 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
972 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
976 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
980 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
988 bl 1f /* Find our address */
995 /* 4. Clear out PIDs & Search info
997 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
998 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1005 /* 5. Invalidate mapping we started in
1007 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1008 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1014 rlwinm r6,r6,0,2,0 /* clear IPROT */
1018 /* Invalidate TLB1 */
1019 PPC_TLBILX_ALL(0,R0)
1023 /* The mapping only needs to be cache-coherent on SMP */
1025 #define M_IF_SMP MAS2_M
1030 /* 6. Setup KERNELBASE mapping in TLB[0]
1032 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1033 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1036 rlwinm r3,r3,0,16,3 /* clear ESEL */
1038 lis r6,(MAS1_VALID|MAS1_IPROT)@h
1039 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
1042 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP)
1046 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
1053 /* 7. Jump to KERNELBASE mapping
1055 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1057 /* Now we branch the new virtual address mapped by this entry */
1058 LOAD_REG_IMMEDIATE(r6,2f)
1060 ori r7,r7,MSR_KERNEL@l
1063 rfi /* start execution out of TLB1[0] entry */
1066 /* 8. Clear out the temp mapping
1068 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1073 rlwinm r5,r5,0,2,0 /* clear IPROT */
1077 /* Invalidate TLB1 */
1078 PPC_TLBILX_ALL(0,R0)
1082 /* We translate LR and return */
1088 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
1089 * kernel linear mapping. We also set MAS8 once for all here though
1090 * that will have to be made dependent on whether we are running under
1091 * a hypervisor I suppose.
1095 * This code is called as an ordinary function on the boot CPU. But to
1096 * avoid duplication, this code is also used in SCOM bringup of
1097 * secondary CPUs. We read the code between the initial_tlb_code_start
1098 * and initial_tlb_code_end labels one instruction at a time and RAM it
1099 * into the new core via SCOM. That doesn't process branches, so there
1100 * must be none between those two labels. It also means if this code
1101 * ever takes any parameters, the SCOM code must also be updated to
1104 .globl a2_tlbinit_code_start
1105 a2_tlbinit_code_start:
1107 ori r11,r3,MAS0_WQ_ALLWAYS
1108 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
1110 lis r3,(MAS1_VALID | MAS1_IPROT)@h
1111 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
1113 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
1115 li r3,MAS3_SR | MAS3_SW | MAS3_SX
1116 mtspr SPRN_MAS7_MAS3,r3
1120 /* Write the TLB entry */
1123 .globl a2_tlbinit_after_linear_map
1124 a2_tlbinit_after_linear_map:
1126 /* Now we branch the new virtual address mapped by this entry */
1127 LOAD_REG_IMMEDIATE(r3,1f)
1131 1: /* We are now running at PAGE_OFFSET, clean the TLB of everything
1132 * else (including IPROTed things left by firmware)
1134 * r3 = current address (more or less)
1141 rlwinm r9,r4,0,TLBnCFG_N_ENTRY
1142 rlwinm r10,r4,8,0xff
1143 addi r10,r10,-1 /* Get inner loop mask */
1148 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1151 rldicr r6,r6,0,51 /* Extract EPN */
1154 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
1156 rlwinm r8,r7,16,0xfff /* Extract ESEL */
1161 rlwimi r7,r4,16,MAS0_ESEL_MASK
1172 addis r6,r6,(1<<30)@h
1177 .globl a2_tlbinit_after_iprot_flush
1178 a2_tlbinit_after_iprot_flush:
1180 #ifdef CONFIG_PPC_EARLY_DEBUG_WSP
1181 /* Now establish early debug mappings if applicable */
1182 /* Restore the MAS0 we used for linear mapping load */
1185 lis r3,(MAS1_VALID | MAS1_IPROT)@h
1186 ori r3,r3,(BOOK3E_PAGESZ_4K << MAS1_TSIZE_SHIFT)
1188 LOAD_REG_IMMEDIATE(r3, WSP_UART_VIRT | MAS2_I | MAS2_G)
1190 LOAD_REG_IMMEDIATE(r3, WSP_UART_PHYS | MAS3_SR | MAS3_SW)
1191 mtspr SPRN_MAS7_MAS3,r3
1192 /* re-use the MAS8 value from the linear mapping */
1194 #endif /* CONFIG_PPC_EARLY_DEBUG_WSP */
1200 .globl a2_tlbinit_code_end
1201 a2_tlbinit_code_end:
1203 /* We translate LR and return */
1210 * Main entry (boot CPU, thread 0)
1212 * We enter here from head_64.S, possibly after the prom_init trampoline
1213 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1214 * mode. Anything else is as it was left by the bootloader
1216 * Initial requirements of this port:
1218 * - Kernel loaded at 0 physical
1219 * - A good lump of memory mapped 0:0 by UTLB entry 0
1220 * - MSR:IS & MSR:DS set to 0
1222 * Note that some of the above requirements will be relaxed in the future
1223 * as the kernel becomes smarter at dealing with different initial conditions
1224 * but for now you have to be careful
1226 _GLOBAL(start_initialization_book3e)
1229 /* First, we need to setup some initial TLBs to map the kernel
1230 * text, data and bss at PAGE_OFFSET. We don't have a real mode
1231 * and always use AS 0, so we just set it up to match our link
1232 * address and never use 0 based addresses.
1234 bl .initial_tlb_book3e
1236 /* Init global core bits */
1237 bl .init_core_book3e
1239 /* Init per-thread bits */
1240 bl .init_thread_book3e
1242 /* Return to common init code */
1249 * Secondary core/processor entry
1251 * This is entered for thread 0 of a secondary core, all other threads
1252 * are expected to be stopped. It's similar to start_initialization_book3e
1253 * except that it's generally entered from the holding loop in head_64.S
1254 * after CPUs have been gathered by Open Firmware.
1256 * We assume we are in 32 bits mode running with whatever TLB entry was
1257 * set for us by the firmware or POR engine.
1259 _GLOBAL(book3e_secondary_core_init_tlb_set)
1261 b .generic_secondary_smp_init
1263 _GLOBAL(book3e_secondary_core_init)
1266 /* Do we need to setup initial TLB entry ? */
1270 /* Setup TLB for this core */
1271 bl .initial_tlb_book3e
1273 /* We can return from the above running at a different
1274 * address, so recalculate r2 (TOC)
1278 /* Init global core bits */
1279 2: bl .init_core_book3e
1281 /* Init per-thread bits */
1282 3: bl .init_thread_book3e
1284 /* Return to common init code at proper virtual address.
1286 * Due to various previous assumptions, we know we entered this
1287 * function at either the final PAGE_OFFSET mapping or using a
1288 * 1:1 mapping at 0, so we don't bother doing a complicated check
1289 * here, we just ensure the return address has the right top bits.
1291 * Note that if we ever want to be smarter about where we can be
1292 * started from, we have to be careful that by the time we reach
1293 * the code below we may already be running at a different location
1294 * than the one we were called from since initial_tlb_book3e can
1295 * have moved us already.
1299 lis r3,PAGE_OFFSET@highest
1305 _GLOBAL(book3e_secondary_thread_init)
1309 _STATIC(init_core_book3e)
1310 /* Establish the interrupt vector base */
1311 LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e)
1316 _STATIC(init_thread_book3e)
1317 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1320 /* Make sure interrupts are off */
1323 /* disable all timers and clear out status */
1331 _GLOBAL(__setup_base_ivors)
1332 SET_IVOR(0, 0x020) /* Critical Input */
1333 SET_IVOR(1, 0x000) /* Machine Check */
1334 SET_IVOR(2, 0x060) /* Data Storage */
1335 SET_IVOR(3, 0x080) /* Instruction Storage */
1336 SET_IVOR(4, 0x0a0) /* External Input */
1337 SET_IVOR(5, 0x0c0) /* Alignment */
1338 SET_IVOR(6, 0x0e0) /* Program */
1339 SET_IVOR(7, 0x100) /* FP Unavailable */
1340 SET_IVOR(8, 0x120) /* System Call */
1341 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
1342 SET_IVOR(10, 0x160) /* Decrementer */
1343 SET_IVOR(11, 0x180) /* Fixed Interval Timer */
1344 SET_IVOR(12, 0x1a0) /* Watchdog Timer */
1345 SET_IVOR(13, 0x1c0) /* Data TLB Error */
1346 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1347 SET_IVOR(15, 0x040) /* Debug */
1353 _GLOBAL(setup_perfmon_ivor)
1354 SET_IVOR(35, 0x260) /* Performance Monitor */
1357 _GLOBAL(setup_doorbell_ivors)
1358 SET_IVOR(36, 0x280) /* Processor Doorbell */
1359 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1362 _GLOBAL(setup_ehv_ivors)
1363 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1364 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
1365 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1366 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */