3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <asm/unistd.h>
23 #include <asm/processor.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cputable.h>
30 #include <asm/firmware.h>
32 #include <asm/ptrace.h>
33 #include <asm/irqflags.h>
34 #include <asm/ftrace.h>
35 #include <asm/hw_irq.h>
36 #include <asm/context_tracking.h>
43 .tc .sys_call_table[TC],.sys_call_table
45 /* This value is used to mark exception frames on the stack. */
47 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
54 .globl system_call_common
58 addi r1,r1,-INT_FRAME_SIZE
66 beq 2f /* if from kernel mode */
67 ACCOUNT_CPU_USER_ENTRY(r10, r11)
86 * This clears CR0.SO (bit 28), which is the error indication on
87 * return from this system call.
89 rldimi r2,r11,28,(63-28)
96 addi r9,r1,STACK_FRAME_OVERHEAD
97 ld r11,exception_marker@toc(r2)
98 std r11,-16(r9) /* "regshere" marker */
99 #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
102 /* if from user, see if there are any DTL entries to process */
103 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
104 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
105 ld r10,LPPACA_DTLIDX(r10) /* get log write index */
108 bl .accumulate_stolen_time
112 addi r9,r1,STACK_FRAME_OVERHEAD
114 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
115 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
118 * A syscall should always be called with interrupts enabled
119 * so we just unconditionally hard-enable here. When some kind
120 * of irq tracing is used, we additionally check that condition
123 #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
124 lbz r10,PACASOFTIRQEN(r13)
127 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
130 #ifdef CONFIG_PPC_BOOK3E
136 #endif /* CONFIG_PPC_BOOK3E */
138 /* We do need to set SOFTE in the stack frame or the return
139 * from interrupt will be painful
149 addi r9,r1,STACK_FRAME_OVERHEAD
151 CURRENT_THREAD_INFO(r11, r1)
153 andi. r11,r10,_TIF_SYSCALL_T_OR_A
155 .Lsyscall_dotrace_cont:
156 cmpldi 0,r0,NR_syscalls
159 system_call: /* label this so stack traces look sane */
161 * Need to vector to 32 Bit or default sys_call_table here,
162 * based on caller's run-mode / personality.
164 ld r11,.SYS_CALL_TABLE@toc(2)
165 andi. r10,r10,_TIF_32BIT
167 addi r11,r11,8 /* use 32-bit syscall entries */
176 ldx r10,r11,r0 /* Fetch system call handler [ptr] */
178 bctrl /* Call handler */
183 bl .do_show_syscall_exit
186 CURRENT_THREAD_INFO(r12, r1)
189 #ifdef CONFIG_PPC_BOOK3S
190 /* No MSR:RI on BookE */
195 * Disable interrupts so current_thread_info()->flags can't change,
196 * and so that we don't get interrupted after loading SRR0/1.
198 #ifdef CONFIG_PPC_BOOK3E
203 * For performance reasons we clear RI the same time that we
204 * clear EE. We only need to clear RI just before we restore r13
205 * below, but batching it with EE saves us one expensive mtmsrd call.
206 * We have to be careful to restore RI if we branch anywhere from
207 * here (eg syscall_exit_work).
212 #endif /* CONFIG_PPC_BOOK3E */
216 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
217 bne- syscall_exit_work
221 .Lsyscall_error_cont:
224 stdcx. r0,0,r1 /* to clear the reservation */
225 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
230 ACCOUNT_CPU_USER_EXIT(r11, r12)
231 HMT_MEDIUM_LOW_HAS_PPR
232 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
240 b . /* prevent speculative execution */
243 oris r5,r5,0x1000 /* Set SO bit in CR */
246 b .Lsyscall_error_cont
248 /* Traced system call support */
251 addi r3,r1,STACK_FRAME_OVERHEAD
252 bl .do_syscall_trace_enter
254 * Restore argument registers possibly just changed.
255 * We use the return value of do_syscall_trace_enter
256 * for the call number to look up in the table (r0).
265 addi r9,r1,STACK_FRAME_OVERHEAD
266 CURRENT_THREAD_INFO(r10, r1)
268 b .Lsyscall_dotrace_cont
275 #ifdef CONFIG_PPC_BOOK3S
276 mtmsrd r10,1 /* Restore RI */
278 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
279 If TIF_NOERROR is set, just save r3 as it is. */
281 andi. r0,r9,_TIF_RESTOREALL
285 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */
287 andi. r0,r9,_TIF_NOERROR
291 oris r5,r5,0x1000 /* Set SO bit in CR */
294 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
297 /* Clear per-syscall TIF flags if any are set. */
299 li r11,_TIF_PERSYSCALL_MASK
300 addi r12,r12,TI_FLAGS
305 subi r12,r12,TI_FLAGS
307 4: /* Anything else left to do? */
308 SET_DEFAULT_THREAD_PPR(r3, r10) /* Set thread.ppr = 3 */
309 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
310 beq .ret_from_except_lite
312 /* Re-enable interrupts */
313 #ifdef CONFIG_PPC_BOOK3E
319 #endif /* CONFIG_PPC_BOOK3E */
322 addi r3,r1,STACK_FRAME_OVERHEAD
323 bl .do_syscall_trace_leave
326 /* Save non-volatile GPRs, if not already saved. */
338 * The sigsuspend and rt_sigsuspend system calls can call do_signal
339 * and thus put the process into the stopped state where we might
340 * want to examine its user state with ptrace. Therefore we need
341 * to save all the nonvolatile registers (r14 - r31) before calling
342 * the C code. Similarly, fork, vfork and clone need the full
343 * register state on the stack so that it can be copied to the child.
361 _GLOBAL(ppc32_swapcontext)
363 bl .compat_sys_swapcontext
366 _GLOBAL(ppc64_swapcontext)
371 _GLOBAL(ret_from_fork)
377 _GLOBAL(ret_from_kernel_thread)
389 .tc dscr_default[TC],dscr_default
394 * This routine switches between two different tasks. The process
395 * state of one is saved on its kernel stack. Then the state
396 * of the other is restored from its kernel stack. The memory
397 * management hardware is updated to the second process's state.
398 * Finally, we can return to the second process, via ret_from_except.
399 * On entry, r3 points to the THREAD for the current task, r4
400 * points to the THREAD for the new task.
402 * Note: there are two ways to get to the "going out" portion
403 * of this code; either by coming in via the entry (_switch)
404 * or via "fork" which must set up an environment equivalent
405 * to the "_switch" path. If you change this you'll have to change
406 * the fork code also.
408 * The code which creates the new task context is in 'copy_thread'
409 * in arch/powerpc/kernel/process.c
415 stdu r1,-SWITCH_FRAME_SIZE(r1)
416 /* r3-r13 are caller saved -- Cort */
419 mflr r20 /* Return to switch caller */
424 oris r0,r0,MSR_VSX@h /* Disable VSX */
425 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
426 #endif /* CONFIG_VSX */
427 #ifdef CONFIG_ALTIVEC
429 oris r0,r0,MSR_VEC@h /* Disable altivec */
430 mfspr r24,SPRN_VRSAVE /* save vrsave register value */
431 std r24,THREAD_VRSAVE(r3)
432 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
433 #endif /* CONFIG_ALTIVEC */
437 std r25,THREAD_DSCR(r3)
438 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
448 std r1,KSP(r3) /* Set old stack pointer */
450 #ifdef CONFIG_PPC_BOOK3S_64
452 /* Event based branch registers */
454 std r0, THREAD_BESCR(r3)
456 std r0, THREAD_EBBHR(r3)
458 std r0, THREAD_EBBRR(r3)
459 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
463 /* We need a sync somewhere here to make sure that if the
464 * previous task gets rescheduled on another CPU, it sees all
465 * stores it has performed on this one.
468 #endif /* CONFIG_SMP */
471 * If we optimise away the clear of the reservation in system
472 * calls because we know the CPU tracks the address of the
473 * reservation, then we need to clear it here to cover the
474 * case that the kernel context switch path has no larx
479 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
481 #ifdef CONFIG_PPC_BOOK3S
482 /* Cancel all explict user streams as they will have no use after context
483 * switch and will stop the HW from creating streams itself
485 DCBT_STOP_ALL_STREAM_IDS(r6)
488 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
489 std r6,PACACURRENT(r13) /* Set new 'current' */
491 ld r8,KSP(r4) /* new stack pointer */
492 #ifdef CONFIG_PPC_BOOK3S
494 BEGIN_FTR_SECTION_NESTED(95)
495 clrrdi r6,r8,28 /* get its ESID */
496 clrrdi r9,r1,28 /* get current sp ESID */
497 FTR_SECTION_ELSE_NESTED(95)
498 clrrdi r6,r8,40 /* get its 1T ESID */
499 clrrdi r9,r1,40 /* get current sp 1T ESID */
500 ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
503 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
504 clrldi. r0,r6,2 /* is new ESID c00000000? */
505 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
507 beq 2f /* if yes, don't slbie it */
509 /* Bolt in the new stack SLB entry */
510 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
511 oris r0,r6,(SLB_ESID_V)@h
512 ori r0,r0,(SLB_NUM_BOLTED-1)@l
514 li r9,MMU_SEGSIZE_1T /* insert B field */
515 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
516 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
517 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
519 /* Update the last bolted SLB. No write barriers are needed
520 * here, provided we only update the current CPU's SLB shadow
523 ld r9,PACA_SLBSHADOWPTR(r13)
525 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
526 std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
527 std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
529 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
530 * we have 1TB segments, the only CPUs known to have the errata
531 * only support less than 1TB of system memory and we'll never
532 * actually hit this code path.
536 slbie r6 /* Workaround POWER5 < DD2.1 issue */
540 #endif /* !CONFIG_PPC_BOOK3S */
542 CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
543 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
544 because we don't need to leave the 288-byte ABI gap at the
545 top of the kernel stack. */
546 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
548 mr r1,r8 /* start using new stack pointer */
549 std r7,PACAKSAVE(r13)
551 #ifdef CONFIG_PPC_BOOK3S_64
553 /* Event based branch registers */
554 ld r0, THREAD_BESCR(r4)
556 ld r0, THREAD_EBBHR(r4)
558 ld r0, THREAD_EBBRR(r4)
563 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
566 #ifdef CONFIG_ALTIVEC
568 ld r0,THREAD_VRSAVE(r4)
569 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
570 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
571 #endif /* CONFIG_ALTIVEC */
574 lwz r6,THREAD_DSCR_INHERIT(r4)
575 ld r7,DSCR_DEFAULT@toc(2)
576 ld r0,THREAD_DSCR(r4)
583 BEGIN_FTR_SECTION_NESTED(70)
587 BEGIN_FTR_SECTION_NESTED(69)
591 END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
593 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
595 BEGIN_FTR_SECTION_NESTED(70)
599 BEGIN_FTR_SECTION_NESTED(69)
603 END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
604 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
609 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
615 /* r3-r13 are destroyed -- Cort */
619 /* convert old thread to its task_struct for return value */
621 ld r7,_NIP(r1) /* Return to _switch caller in new task */
623 addi r1,r1,SWITCH_FRAME_SIZE
627 _GLOBAL(ret_from_except)
630 bne .ret_from_except_lite
633 _GLOBAL(ret_from_except_lite)
635 * Disable interrupts so that current_thread_info()->flags
636 * can't change between when we test it and when we return
637 * from the interrupt.
639 #ifdef CONFIG_PPC_BOOK3E
642 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
643 mtmsrd r10,1 /* Update machine state */
644 #endif /* CONFIG_PPC_BOOK3E */
646 CURRENT_THREAD_INFO(r9, r1)
652 /* Check current_thread_info()->flags */
653 andi. r0,r4,_TIF_USER_WORK_MASK
656 andi. r0,r4,_TIF_NEED_RESCHED
658 bl .restore_interrupts
660 b .ret_from_except_lite
663 bl .restore_interrupts
664 addi r3,r1,STACK_FRAME_OVERHEAD
669 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
670 CURRENT_THREAD_INFO(r9, r1)
672 andis. r8,r8,_TIF_EMULATE_STACK_STORE@h
675 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
678 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
679 mr r4,r1 /* src: current exception frame */
680 mr r1,r3 /* Reroute the trampoline frame to r1 */
682 /* Copy from the original to the trampoline. */
683 li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
684 li r6,0 /* start offset: 0 */
691 /* Do real store operation to complete stwu */
695 /* Clear _TIF_EMULATE_STACK_STORE flag */
696 lis r11,_TIF_EMULATE_STACK_STORE@h
704 #ifdef CONFIG_PREEMPT
705 /* Check if we need to preempt */
706 andi. r0,r4,_TIF_NEED_RESCHED
708 /* Check that preempt_count() == 0 and interrupts are enabled */
709 lwz r8,TI_PREEMPT(r9)
713 crandc eq,cr1*4+eq,eq
717 * Here we are preempting the current task. We want to make
718 * sure we are soft-disabled first
720 SOFT_DISABLE_INTS(r3,r4)
721 1: bl .preempt_schedule_irq
723 /* Re-test flags and eventually loop */
724 CURRENT_THREAD_INFO(r9, r1)
726 andi. r0,r4,_TIF_NEED_RESCHED
730 * arch_local_irq_restore() from preempt_schedule_irq above may
731 * enable hard interrupt but we really should disable interrupts
732 * when we return from the interrupt, and so that we don't get
733 * interrupted after loading SRR0/1.
735 #ifdef CONFIG_PPC_BOOK3E
738 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
739 mtmsrd r10,1 /* Update machine state */
740 #endif /* CONFIG_PPC_BOOK3E */
741 #endif /* CONFIG_PREEMPT */
743 .globl fast_exc_return_irq
747 * This is the main kernel exit path. First we check if we
748 * are about to re-enable interrupts
751 lbz r6,PACASOFTIRQEN(r13)
755 /* We are enabling, were we already enabled ? Yes, just return */
760 * We are about to soft-enable interrupts (we are hard disabled
761 * at this point). We check if there's anything that needs to
764 lbz r0,PACAIRQHAPPENED(r13)
766 bne- restore_check_irq_replay
769 * Get here when nothing happened while soft-disabled, just
770 * soft-enable and move-on. We will hard-enable as a side
776 stb r0,PACASOFTIRQEN(r13);
779 * Final return path. BookE is handled in a different file
782 #ifdef CONFIG_PPC_BOOK3E
783 b .exception_return_book3e
786 * Clear the reservation. If we know the CPU tracks the address of
787 * the reservation then we can potentially save some cycles and use
788 * a larx. On POWER6 and POWER7 this is significantly faster.
791 stdcx. r0,0,r1 /* to clear the reservation */
794 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
797 * Some code path such as load_up_fpu or altivec return directly
798 * here. They run entirely hard disabled and do not alter the
799 * interrupt state. They also don't use lwarx/stwcx. and thus
800 * are known not to leave dangling reservations.
802 .globl fast_exception_return
803 fast_exception_return:
818 * Clear RI before restoring r13. If we are returning to
819 * userspace and we take an exception after restoring r13,
820 * we end up corrupting the userspace r13 value.
822 ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */
823 andc r4,r4,r0 /* r0 contains MSR_RI here */
826 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
828 std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
831 * r13 is our per cpu area, only restore it if we are returning to
832 * userspace the value stored in the stack frame may belong to
837 ACCOUNT_CPU_USER_EXIT(r2, r4)
855 b . /* prevent speculative execution */
857 #endif /* CONFIG_PPC_BOOK3E */
860 * We are returning to a context with interrupts soft disabled.
862 * However, we may also about to hard enable, so we need to
863 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
864 * or that bit can get out of sync and bad things will happen
868 lbz r7,PACAIRQHAPPENED(r13)
871 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
872 stb r7,PACAIRQHAPPENED(r13)
874 stb r0,PACASOFTIRQEN(r13);
879 * Something did happen, check if a re-emit is needed
880 * (this also clears paca->irq_happened)
882 restore_check_irq_replay:
883 /* XXX: We could implement a fast path here where we check
884 * for irq_happened being just 0x01, in which case we can
885 * clear it and return. That means that we would potentially
886 * miss a decrementer having wrapped all the way around.
888 * Still, this might be useful for things like hash_page
890 bl .__check_irq_replay
892 beq restore_no_replay
895 * We need to re-emit an interrupt. We do so by re-using our
896 * existing exception frame. We first change the trap value,
897 * but we need to ensure we preserve the low nibble of it
905 * Then find the right handler and call it. Interrupts are
906 * still soft-disabled and we keep them that way.
910 addi r3,r1,STACK_FRAME_OVERHEAD;
913 1: cmpwi cr0,r3,0x900
915 addi r3,r1,STACK_FRAME_OVERHEAD;
918 #ifdef CONFIG_PPC_DOORBELL
920 #ifdef CONFIG_PPC_BOOK3E
927 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
928 #endif /* CONFIG_PPC_BOOK3E */
930 addi r3,r1,STACK_FRAME_OVERHEAD;
931 bl .doorbell_exception
933 #endif /* CONFIG_PPC_DOORBELL */
934 1: b .ret_from_except /* What else to do here ? */
937 addi r3,r1,STACK_FRAME_OVERHEAD
938 bl .unrecoverable_exception
941 #ifdef CONFIG_PPC_RTAS
943 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
944 * called with the MMU off.
946 * In addition, we need to be in 32b mode, at least for now.
948 * Note: r3 is an input parameter to rtas, so don't trash it...
953 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
955 /* Because RTAS is running in 32b mode, it clobbers the high order half
956 * of all registers that it saves. We therefore save those registers
957 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
959 SAVE_GPR(2, r1) /* Save the TOC */
960 SAVE_GPR(13, r1) /* Save paca */
961 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
962 SAVE_10GPRS(22, r1) /* ditto */
975 /* Temporary workaround to clear CR until RTAS can be modified to
982 /* There is no way it is acceptable to get here with interrupts enabled,
983 * check it with the asm equivalent of WARN_ON
985 lbz r0,PACASOFTIRQEN(r13)
987 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
990 /* Hard-disable interrupts */
996 /* Unfortunately, the stack pointer and the MSR are also clobbered,
997 * so they are saved in the PACA which allows us to restore
998 * our original state after RTAS returns.
1001 std r6,PACASAVEDMSR(r13)
1003 /* Setup our real return addr */
1004 LOAD_REG_ADDR(r4,.rtas_return_loc)
1005 clrldi r4,r4,2 /* convert to realmode address */
1009 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
1013 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
1014 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI
1016 sync /* disable interrupts so SRR0/1 */
1017 mtmsrd r0 /* don't get trashed */
1019 LOAD_REG_ADDR(r4, rtas)
1020 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
1021 ld r4,RTASBASE(r4) /* get the rtas->base value */
1026 b . /* prevent speculative execution */
1028 _STATIC(rtas_return_loc)
1029 /* relocation is off at this point */
1031 clrldi r4,r4,2 /* convert to realmode address */
1035 ld r3,(1f-0b)(r3) /* get &.rtas_restore_regs */
1043 ld r1,PACAR1(r4) /* Restore our SP */
1044 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
1049 b . /* prevent speculative execution */
1052 1: .llong .rtas_restore_regs
1054 _STATIC(rtas_restore_regs)
1055 /* relocation is on at this point */
1056 REST_GPR(2, r1) /* Restore the TOC */
1057 REST_GPR(13, r1) /* Restore paca */
1058 REST_8GPRS(14, r1) /* Restore the non-volatiles */
1059 REST_10GPRS(22, r1) /* ditto */
1074 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
1075 ld r0,16(r1) /* get return address */
1078 blr /* return to caller */
1080 #endif /* CONFIG_PPC_RTAS */
1085 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
1087 /* Because PROM is running in 32b mode, it clobbers the high order half
1088 * of all registers that it saves. We therefore save those registers
1089 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
1100 /* Get the PROM entrypoint */
1103 /* Switch MSR to 32 bits mode
1105 #ifdef CONFIG_PPC_BOOK3E
1106 rlwinm r11,r11,0,1,31
1108 #else /* CONFIG_PPC_BOOK3E */
1111 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1114 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1117 #endif /* CONFIG_PPC_BOOK3E */
1120 /* Enter PROM here... */
1123 /* Just make sure that r1 top 32 bits didn't get
1128 /* Restore the MSR (back to 64 bits) */
1133 /* Restore other registers */
1141 addi r1,r1,PROM_FRAME_SIZE
1146 #ifdef CONFIG_FUNCTION_TRACER
1147 #ifdef CONFIG_DYNAMIC_FTRACE
1152 _GLOBAL(ftrace_caller)
1153 /* Taken from output of objdump from lib64/glibc */
1159 subi r3, r3, MCOUNT_INSN_SIZE
1164 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1165 .globl ftrace_graph_call
1168 _GLOBAL(ftrace_graph_stub)
1173 _GLOBAL(ftrace_stub)
1180 /* Taken from output of objdump from lib64/glibc */
1187 subi r3, r3, MCOUNT_INSN_SIZE
1188 LOAD_REG_ADDR(r5,ftrace_trace_function)
1196 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1197 b ftrace_graph_caller
1202 _GLOBAL(ftrace_stub)
1205 #endif /* CONFIG_DYNAMIC_FTRACE */
1207 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1208 _GLOBAL(ftrace_graph_caller)
1209 /* load r4 with local address */
1211 subi r4, r4, MCOUNT_INSN_SIZE
1213 /* get the parent address */
1217 bl .prepare_ftrace_return
1225 _GLOBAL(return_to_handler)
1226 /* need to save return values */
1233 bl .ftrace_return_to_handler
1236 /* return value has real return address */
1244 /* Jump back to real return address */
1247 _GLOBAL(mod_return_to_handler)
1248 /* need to save return values */
1258 * We are in a module using the module's TOC.
1259 * Switch to our TOC to run inside the core kernel.
1263 bl .ftrace_return_to_handler
1266 /* return value has real return address */
1275 /* Jump back to real return address */
1277 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1278 #endif /* CONFIG_FUNCTION_TRACER */