2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
4 #ifndef _ASM_POWERPC_PPC_ASM_H
5 #define _ASM_POWERPC_PPC_ASM_H
7 #include <linux/init.h>
8 #include <linux/stringify.h>
9 #include <asm/asm-compat.h>
10 #include <asm/processor.h>
11 #include <asm/ppc-opcode.h>
12 #include <asm/firmware.h>
15 #error __FILE__ should only be used in assembler files
18 #define SZL (BITS_PER_LONG/8)
21 * Stuff for accurate CPU time accounting.
22 * These macros handle transitions between user and system state
23 * in exception entry and exit and accumulate time to the
24 * user_time and system_time fields in the paca.
27 #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
28 #define ACCOUNT_CPU_USER_ENTRY(ra, rb)
29 #define ACCOUNT_CPU_USER_EXIT(ra, rb)
30 #define ACCOUNT_STOLEN_TIME
32 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \
33 MFTB(ra); /* get timebase */ \
34 ld rb,PACA_STARTTIME_USER(r13); \
35 std ra,PACA_STARTTIME(r13); \
36 subf rb,rb,ra; /* subtract start value */ \
37 ld ra,PACA_USER_TIME(r13); \
38 add ra,ra,rb; /* add on to user time */ \
39 std ra,PACA_USER_TIME(r13); \
41 #define ACCOUNT_CPU_USER_EXIT(ra, rb) \
42 MFTB(ra); /* get timebase */ \
43 ld rb,PACA_STARTTIME(r13); \
44 std ra,PACA_STARTTIME_USER(r13); \
45 subf rb,rb,ra; /* subtract start value */ \
46 ld ra,PACA_SYSTEM_TIME(r13); \
47 add ra,ra,rb; /* add on to system time */ \
48 std ra,PACA_SYSTEM_TIME(r13)
50 #ifdef CONFIG_PPC_SPLPAR
51 #define ACCOUNT_STOLEN_TIME \
52 BEGIN_FW_FTR_SECTION; \
54 /* from user - see if there are any DTL entries to process */ \
55 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \
56 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \
57 ld r10,LPPACA_DTLIDX(r10); /* get log write index */ \
60 bl .accumulate_stolen_time; \
62 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \
64 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
66 #else /* CONFIG_PPC_SPLPAR */
67 #define ACCOUNT_STOLEN_TIME
69 #endif /* CONFIG_PPC_SPLPAR */
71 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
74 * Macros for storing registers into and loading registers from
78 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
79 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
80 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
81 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
83 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
84 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
85 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
87 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
91 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
92 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
93 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
94 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
95 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
96 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
97 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
98 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
100 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
101 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
102 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
103 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
104 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
105 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
106 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
107 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
108 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
109 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
110 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
111 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
113 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,base,b
114 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
115 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
116 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
117 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
118 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
119 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,base,b
120 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
121 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
122 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
123 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
124 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
126 /* Save/restore FPRs, VRs and VSRs from their checkpointed backups in
129 #define SAVE_FPR_TRANSACT(n, base) stfd n,THREAD_TRANSACT_FPR0+ \
130 8*TS_FPRWIDTH*(n)(base)
131 #define SAVE_2FPRS_TRANSACT(n, base) SAVE_FPR_TRANSACT(n, base); \
132 SAVE_FPR_TRANSACT(n+1, base)
133 #define SAVE_4FPRS_TRANSACT(n, base) SAVE_2FPRS_TRANSACT(n, base); \
134 SAVE_2FPRS_TRANSACT(n+2, base)
135 #define SAVE_8FPRS_TRANSACT(n, base) SAVE_4FPRS_TRANSACT(n, base); \
136 SAVE_4FPRS_TRANSACT(n+4, base)
137 #define SAVE_16FPRS_TRANSACT(n, base) SAVE_8FPRS_TRANSACT(n, base); \
138 SAVE_8FPRS_TRANSACT(n+8, base)
139 #define SAVE_32FPRS_TRANSACT(n, base) SAVE_16FPRS_TRANSACT(n, base); \
140 SAVE_16FPRS_TRANSACT(n+16, base)
142 #define REST_FPR_TRANSACT(n, base) lfd n,THREAD_TRANSACT_FPR0+ \
143 8*TS_FPRWIDTH*(n)(base)
144 #define REST_2FPRS_TRANSACT(n, base) REST_FPR_TRANSACT(n, base); \
145 REST_FPR_TRANSACT(n+1, base)
146 #define REST_4FPRS_TRANSACT(n, base) REST_2FPRS_TRANSACT(n, base); \
147 REST_2FPRS_TRANSACT(n+2, base)
148 #define REST_8FPRS_TRANSACT(n, base) REST_4FPRS_TRANSACT(n, base); \
149 REST_4FPRS_TRANSACT(n+4, base)
150 #define REST_16FPRS_TRANSACT(n, base) REST_8FPRS_TRANSACT(n, base); \
151 REST_8FPRS_TRANSACT(n+8, base)
152 #define REST_32FPRS_TRANSACT(n, base) REST_16FPRS_TRANSACT(n, base); \
153 REST_16FPRS_TRANSACT(n+16, base)
156 #define SAVE_VR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VR0+(16*(n)); \
158 #define SAVE_2VRS_TRANSACT(n,b,base) SAVE_VR_TRANSACT(n,b,base); \
159 SAVE_VR_TRANSACT(n+1,b,base)
160 #define SAVE_4VRS_TRANSACT(n,b,base) SAVE_2VRS_TRANSACT(n,b,base); \
161 SAVE_2VRS_TRANSACT(n+2,b,base)
162 #define SAVE_8VRS_TRANSACT(n,b,base) SAVE_4VRS_TRANSACT(n,b,base); \
163 SAVE_4VRS_TRANSACT(n+4,b,base)
164 #define SAVE_16VRS_TRANSACT(n,b,base) SAVE_8VRS_TRANSACT(n,b,base); \
165 SAVE_8VRS_TRANSACT(n+8,b,base)
166 #define SAVE_32VRS_TRANSACT(n,b,base) SAVE_16VRS_TRANSACT(n,b,base); \
167 SAVE_16VRS_TRANSACT(n+16,b,base)
169 #define REST_VR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VR0+(16*(n)); \
171 #define REST_2VRS_TRANSACT(n,b,base) REST_VR_TRANSACT(n,b,base); \
172 REST_VR_TRANSACT(n+1,b,base)
173 #define REST_4VRS_TRANSACT(n,b,base) REST_2VRS_TRANSACT(n,b,base); \
174 REST_2VRS_TRANSACT(n+2,b,base)
175 #define REST_8VRS_TRANSACT(n,b,base) REST_4VRS_TRANSACT(n,b,base); \
176 REST_4VRS_TRANSACT(n+4,b,base)
177 #define REST_16VRS_TRANSACT(n,b,base) REST_8VRS_TRANSACT(n,b,base); \
178 REST_8VRS_TRANSACT(n+8,b,base)
179 #define REST_32VRS_TRANSACT(n,b,base) REST_16VRS_TRANSACT(n,b,base); \
180 REST_16VRS_TRANSACT(n+16,b,base)
183 #define SAVE_VSR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VSR0+(16*(n)); \
184 STXVD2X(n,R##base,R##b)
185 #define SAVE_2VSRS_TRANSACT(n,b,base) SAVE_VSR_TRANSACT(n,b,base); \
186 SAVE_VSR_TRANSACT(n+1,b,base)
187 #define SAVE_4VSRS_TRANSACT(n,b,base) SAVE_2VSRS_TRANSACT(n,b,base); \
188 SAVE_2VSRS_TRANSACT(n+2,b,base)
189 #define SAVE_8VSRS_TRANSACT(n,b,base) SAVE_4VSRS_TRANSACT(n,b,base); \
190 SAVE_4VSRS_TRANSACT(n+4,b,base)
191 #define SAVE_16VSRS_TRANSACT(n,b,base) SAVE_8VSRS_TRANSACT(n,b,base); \
192 SAVE_8VSRS_TRANSACT(n+8,b,base)
193 #define SAVE_32VSRS_TRANSACT(n,b,base) SAVE_16VSRS_TRANSACT(n,b,base); \
194 SAVE_16VSRS_TRANSACT(n+16,b,base)
196 #define REST_VSR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VSR0+(16*(n)); \
197 LXVD2X(n,R##base,R##b)
198 #define REST_2VSRS_TRANSACT(n,b,base) REST_VSR_TRANSACT(n,b,base); \
199 REST_VSR_TRANSACT(n+1,b,base)
200 #define REST_4VSRS_TRANSACT(n,b,base) REST_2VSRS_TRANSACT(n,b,base); \
201 REST_2VSRS_TRANSACT(n+2,b,base)
202 #define REST_8VSRS_TRANSACT(n,b,base) REST_4VSRS_TRANSACT(n,b,base); \
203 REST_4VSRS_TRANSACT(n+4,b,base)
204 #define REST_16VSRS_TRANSACT(n,b,base) REST_8VSRS_TRANSACT(n,b,base); \
205 REST_8VSRS_TRANSACT(n+8,b,base)
206 #define REST_32VSRS_TRANSACT(n,b,base) REST_16VSRS_TRANSACT(n,b,base); \
207 REST_16VSRS_TRANSACT(n+16,b,base)
209 /* Save the lower 32 VSRs in the thread VSR region */
210 #define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,R##base,R##b)
211 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
212 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
213 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
214 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
215 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
216 #define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,R##base,R##b)
217 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
218 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
219 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
220 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
221 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
222 /* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
223 #define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,R##base,R##b)
224 #define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
225 #define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
226 #define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
227 #define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
228 #define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
229 #define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,R##base,R##b)
230 #define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
231 #define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
232 #define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
233 #define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base)
234 #define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base)
237 * b = base register for addressing, o = base offset from register of 1st EVR
238 * n = first EVR, s = scratch
240 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b)
241 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
242 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
243 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
244 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
245 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
246 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n
247 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
248 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
249 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
250 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
251 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
253 /* Macros to adjust thread priority for hardware multithreading */
254 #define HMT_VERY_LOW or 31,31,31 # very low priority
255 #define HMT_LOW or 1,1,1
256 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
257 #define HMT_MEDIUM or 2,2,2
258 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
259 #define HMT_HIGH or 3,3,3
260 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only
267 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
268 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n)
273 #define STACKFRAMESIZE 256
274 #define __STK_REG(i) (112 + ((i)-14)*8)
275 #define STK_REG(i) __STK_REG(__REG_##i)
277 #define __STK_PARAM(i) (48 + ((i)-3)*8)
278 #define STK_PARAM(i) __STK_PARAM(__REG_##i)
280 #define XGLUE(a,b) a##b
281 #define GLUE(a,b) XGLUE(a,b)
283 #define _GLOBAL(name) \
287 .globl GLUE(.,name); \
288 .section ".opd","aw"; \
290 .quad GLUE(.,name); \
291 .quad .TOC.@tocbase; \
294 .type GLUE(.,name),@function; \
297 #define _INIT_GLOBAL(name) \
301 .globl GLUE(.,name); \
302 .section ".opd","aw"; \
304 .quad GLUE(.,name); \
305 .quad .TOC.@tocbase; \
308 .type GLUE(.,name),@function; \
311 #define _KPROBE(name) \
312 .section ".kprobes.text","a"; \
315 .globl GLUE(.,name); \
316 .section ".opd","aw"; \
318 .quad GLUE(.,name); \
319 .quad .TOC.@tocbase; \
322 .type GLUE(.,name),@function; \
325 #define _STATIC(name) \
328 .section ".opd","aw"; \
330 .quad GLUE(.,name); \
331 .quad .TOC.@tocbase; \
334 .type GLUE(.,name),@function; \
337 #define _INIT_STATIC(name) \
340 .section ".opd","aw"; \
342 .quad GLUE(.,name); \
343 .quad .TOC.@tocbase; \
346 .type GLUE(.,name),@function; \
357 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
362 .section ".kprobes.text","a"; \
369 * LOAD_REG_IMMEDIATE(rn, expr)
370 * Loads the value of the constant expression 'expr' into register 'rn'
371 * using immediate instructions only. Use this when it's important not
372 * to reference other data (i.e. on ppc64 when the TOC pointer is not
373 * valid) and when 'expr' is a constant or absolute address.
375 * LOAD_REG_ADDR(rn, name)
376 * Loads the address of label 'name' into register 'rn'. Use this when
377 * you don't particularly need immediate instructions only, but you need
378 * the whole address in one register (e.g. it's a structure address and
379 * you want to access various offsets within it). On ppc32 this is
380 * identical to LOAD_REG_IMMEDIATE.
382 * LOAD_REG_ADDRBASE(rn, name)
384 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
385 * register 'rn'. ADDROFF(name) returns the remainder of the address as
386 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
387 * in size, so is suitable for use directly as an offset in load and store
388 * instructions. Use this when loading/storing a single word or less as:
389 * LOAD_REG_ADDRBASE(rX, name)
390 * ld rY,ADDROFF(name)(rX)
393 #ifdef HAVE_AS_ATHIGH
394 #define __AS_ATHIGH high
396 #define __AS_ATHIGH h
398 #define LOAD_REG_IMMEDIATE(reg,expr) \
399 lis reg,(expr)@highest; \
400 ori reg,reg,(expr)@higher; \
401 rldicr reg,reg,32,31; \
402 oris reg,reg,(expr)@__AS_ATHIGH; \
403 ori reg,reg,(expr)@l;
405 #define LOAD_REG_ADDR(reg,name) \
408 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
409 #define ADDROFF(name) 0
411 /* offsets for stack frame layout */
416 #define LOAD_REG_IMMEDIATE(reg,expr) \
418 addi reg,reg,(expr)@l;
420 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
422 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha
423 #define ADDROFF(name) name@l
425 /* offsets for stack frame layout */
430 /* various errata or part fixups */
431 #ifdef CONFIG_PPC601_SYNC_FIX
436 END_FTR_SECTION_IFSET(CPU_FTR_601)
440 END_FTR_SECTION_IFSET(CPU_FTR_601)
444 END_FTR_SECTION_IFSET(CPU_FTR_601)
451 #ifdef CONFIG_PPC_CELL
454 BEGIN_FTR_SECTION_NESTED(96); \
457 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
459 #define MFTB(dest) mftb dest
464 #else /* CONFIG_SMP */
465 /* tlbsync is not implemented on 601 */
470 END_FTR_SECTION_IFCLR(CPU_FTR_601)
474 #define MTOCRF(FXM, RS) \
475 BEGIN_FTR_SECTION_NESTED(848); \
477 FTR_SECTION_ELSE_NESTED(848); \
479 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
482 * PPR restore macros used in entry_64.S
483 * Used for P7 or later processors
485 #define HMT_MEDIUM_LOW_HAS_PPR \
486 BEGIN_FTR_SECTION_NESTED(944) \
488 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,944)
490 #define SET_DEFAULT_THREAD_PPR(ra, rb) \
491 BEGIN_FTR_SECTION_NESTED(945) \
492 lis ra,INIT_PPR@highest; /* default ppr=3 */ \
493 ld rb,PACACURRENT(r13); \
494 sldi ra,ra,32; /* 11- 13 bits are used for ppr */ \
495 std ra,TASKTHREADPPR(rb); \
496 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,945)
498 #define RESTORE_PPR(ra, rb) \
499 BEGIN_FTR_SECTION_NESTED(946) \
500 ld ra,PACACURRENT(r13); \
501 ld rb,TASKTHREADPPR(ra); \
502 mtspr SPRN_PPR,rb; /* Restore PPR */ \
503 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,946)
508 * This instruction is not implemented on the PPC 603 or 601; however, on
509 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
510 * All of these instructions exist in the 8xx, they have magical powers,
511 * and they must be used.
514 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
518 lis r4,KERNELBASE@h; \
525 #ifdef CONFIG_IBM440EP_ERR42
526 #define PPC440EP_ERR42 isync
528 #define PPC440EP_ERR42
531 /* The following stops all load and store data streams associated with stream
532 * ID (ie. streams created explicitly). The embedded and server mnemonics for
533 * dcbt are different so we use machine "power4" here explicitly.
535 #define DCBT_STOP_ALL_STREAM_IDS(scratch) \
537 .machine "power4" ; \
538 lis scratch,0x60000000@h; \
539 dcbt r0,scratch,0b01010; \
543 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
544 * keep the address intact to be compatible with code shared with
547 * On the other hand, I find it useful to have them behave as expected
548 * by their name (ie always do the addition) on 64-bit BookE
550 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
555 * We use addis to ensure compatibility with the "classic" ppc versions of
556 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
557 * converting the address in r0, and so this version has to do that too
558 * (i.e. set register rd to 0 when rs == 0).
560 #define tophys(rd,rs) \
563 #define tovirt(rd,rs) \
566 #elif defined(CONFIG_PPC64)
567 #define toreal(rd) /* we can access c000... in real mode */
570 #define tophys(rd,rs) \
573 #define tovirt(rd,rs) \
575 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
579 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
580 * physical base address of RAM at compile time.
582 #define toreal(rd) tophys(rd,rd)
583 #define fromreal(rd) tovirt(rd,rd)
585 #define tophys(rd,rs) \
586 0: addis rd,rs,-PAGE_OFFSET@h; \
587 .section ".vtop_fixup","aw"; \
592 #define tovirt(rd,rs) \
593 0: addis rd,rs,PAGE_OFFSET@h; \
594 .section ".ptov_fixup","aw"; \
600 #ifdef CONFIG_PPC_BOOK3S_64
602 #define MTMSRD(r) mtmsrd r
603 #define MTMSR_EERI(reg) mtmsrd reg,1
605 #define FIX_SRR1(ra, rb)
609 #define RFI rfi; b . /* Prevent prefetch past rfi */
611 #define MTMSRD(r) mtmsr r
612 #define MTMSR_EERI(reg) mtmsr reg
616 #endif /* __KERNEL__ */
618 /* The boring bits... */
620 /* Condition Register Bit Fields */
633 * General Purpose Registers (GPRs)
635 * The lower case r0-r31 should be used in preference to the upper
636 * case R0-R31 as they provide more error checking in the assembler.
637 * Use R0-31 only when really nessesary.
674 /* Floating Point Registers (FPRs) */
709 /* AltiVec Registers (VPRs) */
744 /* VSX Registers (VSRs) */
811 /* SPE Registers (EVPRs) */
846 /* some stab codes */
852 #endif /* __ASSEMBLY__ */
854 #endif /* _ASM_POWERPC_PPC_ASM_H */