1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
11 #include <linux/list.h>
12 #include <linux/ioport.h>
13 #include <asm-generic/pci-bridge.h>
18 * Structure of a PCI controller (host bridge)
20 struct pci_controller {
26 struct device_node *dn;
27 struct list_head list_node;
28 struct device *parent;
35 void __iomem *io_base_virt;
39 resource_size_t io_base_phys;
40 resource_size_t pci_io_size;
42 /* Some machines (PReP) have a non 1:1 mapping of
43 * the PCI memory space in the CPU bus space
45 resource_size_t pci_mem_offset;
47 /* Some machines have a special region to forward the ISA
48 * "memory" cycles such as VGA memory regions. Left to 0
51 resource_size_t isa_mem_phys;
52 resource_size_t isa_mem_size;
55 unsigned int __iomem *cfg_addr;
56 void __iomem *cfg_data;
59 * Used for variants of PCI indirect handling and possible quirks:
60 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
61 * EXT_REG - provides access to PCI-e extended registers
62 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
63 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
64 * to determine which bus number to match on when generating type0
66 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
67 * hanging if we don't have link and try to do config cycles to
68 * anything but the PHB. Only allow talking to the PHB if this is
70 * BIG_ENDIAN - cfg_addr is a big endian register
71 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
72 * the PLB4. Effectively disable MRM commands by setting this.
73 * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
74 * link status is in a RC PCIe cfg register (vs being a SoC register)
76 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
77 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
78 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
79 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
80 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
81 #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
82 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
84 /* Currently, we limit ourselves to 1 IO range and 3 mem
85 * ranges since the common pci_bus structure can't handle more
87 struct resource io_resource;
88 struct resource mem_resources[3];
89 int global_number; /* PCI domain number */
91 resource_size_t dma_window_base_cur;
92 resource_size_t dma_window_size;
96 #endif /* CONFIG_PPC64 */
101 /* These are used for config access before all the PCI probing
103 extern int early_read_config_byte(struct pci_controller *hose, int bus,
104 int dev_fn, int where, u8 *val);
105 extern int early_read_config_word(struct pci_controller *hose, int bus,
106 int dev_fn, int where, u16 *val);
107 extern int early_read_config_dword(struct pci_controller *hose, int bus,
108 int dev_fn, int where, u32 *val);
109 extern int early_write_config_byte(struct pci_controller *hose, int bus,
110 int dev_fn, int where, u8 val);
111 extern int early_write_config_word(struct pci_controller *hose, int bus,
112 int dev_fn, int where, u16 val);
113 extern int early_write_config_dword(struct pci_controller *hose, int bus,
114 int dev_fn, int where, u32 val);
116 extern int early_find_capability(struct pci_controller *hose, int bus,
117 int dev_fn, int cap);
119 extern void setup_indirect_pci(struct pci_controller* hose,
120 resource_size_t cfg_addr,
121 resource_size_t cfg_data, u32 flags);
123 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
130 extern int pci_device_from_OF_node(struct device_node *node,
132 extern void pci_create_OF_bus_map(void);
134 static inline int isa_vaddr_is_ioport(void __iomem *address)
136 /* No specific ISA handling on ppc32 at this stage, it
137 * all goes through PCI
142 #else /* CONFIG_PPC64 */
145 * PCI stuff, for nodes representing PCI devices, pointed to
146 * by device_node->data.
151 int busno; /* pci bus number */
152 int devfn; /* pci device and function number */
154 struct pci_controller *phb; /* for pci devices */
155 struct iommu_table *iommu_table; /* for phb's or bridges */
156 struct device_node *node; /* back-pointer to the device_node */
158 int pci_ext_config_space; /* for pci devices */
160 struct pci_dev *pcidev; /* back-pointer to the pci device */
162 struct eeh_dev *edev; /* eeh device */
164 #define IODA_INVALID_PE (-1)
165 #ifdef CONFIG_PPC_POWERNV
170 /* Get the pointer to a device_node's pci_dn */
171 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
173 extern void * update_dn_pci_info(struct device_node *dn, void *data);
175 static inline int pci_device_from_OF_node(struct device_node *np,
180 *bus = PCI_DN(np)->busno;
181 *devfn = PCI_DN(np)->devfn;
185 #if defined(CONFIG_EEH)
186 static inline struct eeh_dev *of_node_to_eeh_dev(struct device_node *dn)
189 * For those OF nodes whose parent isn't PCI bridge, they
190 * don't have PCI_DN actually. So we have to skip them for
191 * any EEH operations.
193 if (!dn || !PCI_DN(dn))
196 return PCI_DN(dn)->edev;
199 #define of_node_to_eeh_dev(x) (NULL)
202 /** Find the bus corresponding to the indicated device node */
203 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
205 /** Remove all of the PCI devices under this bus */
206 extern void __pcibios_remove_pci_devices(struct pci_bus *bus, int purge_pe);
207 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
209 /** Discover new pci devices under this bus, and add them */
210 extern void pcibios_add_pci_devices(struct pci_bus *bus);
213 extern void isa_bridge_find_early(struct pci_controller *hose);
215 static inline int isa_vaddr_is_ioport(void __iomem *address)
217 /* Check if address hits the reserved legacy IO range */
218 unsigned long ea = (unsigned long)address;
219 return ea >= ISA_IO_BASE && ea < ISA_IO_END;
222 extern int pcibios_unmap_io_space(struct pci_bus *bus);
223 extern int pcibios_map_io_space(struct pci_bus *bus);
226 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
228 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
231 #endif /* CONFIG_PPC64 */
233 /* Get the PCI host controller for an OF device */
234 extern struct pci_controller *pci_find_hose_for_OF_device(
235 struct device_node* node);
237 /* Fill up host controller resources from the OF node */
238 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
239 struct device_node *dev, int primary);
241 /* Allocate & free a PCI host bridge structure */
242 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
243 extern void pcibios_free_controller(struct pci_controller *phb);
246 extern int pcibios_vaddr_is_ioport(void __iomem *address);
248 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
252 #endif /* CONFIG_PCI */
254 #endif /* __KERNEL__ */
255 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */