2 * PowerNV OPAL definitions.
4 * Copyright 2011 IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
15 /****** Takeover interface ********/
17 /* PAPR H-Call used to querty the HAL existence and/or instanciate
18 * it from within pHyp (tech preview only).
20 * This is exclusively used in prom_init.c
25 struct opal_takeover_args {
29 u64 k_entry2; /* r7 */
30 u64 hal_addr; /* r8 */
31 u64 rd_image; /* r9 */
32 u64 rd_size; /* r10 */
39 * WARNING: The current implementation requires each entry
40 * to represent a block that is 4k aligned *and* each block
41 * size except the last one in the list to be as well.
43 struct opal_sg_entry {
50 unsigned long num_entries;
51 struct opal_sg_list *next;
52 struct opal_sg_entry entry[];
55 /* We calculate number of sg entries based on PAGE_SIZE */
56 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
58 extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
60 extern long opal_do_takeover(struct opal_takeover_args *args);
63 extern int opal_enter_rtas(struct rtas_args *args,
67 #endif /* __ASSEMBLY__ */
69 /****** OPAL APIs ******/
72 #define OPAL_SUCCESS 0
73 #define OPAL_PARAMETER -1
75 #define OPAL_PARTIAL -3
76 #define OPAL_CONSTRAINED -4
77 #define OPAL_CLOSED -5
78 #define OPAL_HARDWARE -6
79 #define OPAL_UNSUPPORTED -7
80 #define OPAL_PERMISSION -8
81 #define OPAL_NO_MEM -9
82 #define OPAL_RESOURCE -10
83 #define OPAL_INTERNAL_ERROR -11
84 #define OPAL_BUSY_EVENT -12
85 #define OPAL_HARDWARE_FROZEN -13
86 #define OPAL_WRONG_STATE -14
87 #define OPAL_ASYNC_COMPLETION -15
89 /* API Tokens (in r0) */
90 #define OPAL_INVALID_CALL -1
91 #define OPAL_CONSOLE_WRITE 1
92 #define OPAL_CONSOLE_READ 2
93 #define OPAL_RTC_READ 3
94 #define OPAL_RTC_WRITE 4
95 #define OPAL_CEC_POWER_DOWN 5
96 #define OPAL_CEC_REBOOT 6
97 #define OPAL_READ_NVRAM 7
98 #define OPAL_WRITE_NVRAM 8
99 #define OPAL_HANDLE_INTERRUPT 9
100 #define OPAL_POLL_EVENTS 10
101 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
102 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
103 #define OPAL_PCI_CONFIG_READ_BYTE 13
104 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
105 #define OPAL_PCI_CONFIG_READ_WORD 15
106 #define OPAL_PCI_CONFIG_WRITE_BYTE 16
107 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
108 #define OPAL_PCI_CONFIG_WRITE_WORD 18
109 #define OPAL_SET_XIVE 19
110 #define OPAL_GET_XIVE 20
111 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
112 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
113 #define OPAL_PCI_EEH_FREEZE_STATUS 23
114 #define OPAL_PCI_SHPC 24
115 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
116 #define OPAL_PCI_EEH_FREEZE_CLEAR 26
117 #define OPAL_PCI_PHB_MMIO_ENABLE 27
118 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
119 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
120 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
121 #define OPAL_PCI_SET_PE 31
122 #define OPAL_PCI_SET_PELTV 32
123 #define OPAL_PCI_SET_MVE 33
124 #define OPAL_PCI_SET_MVE_ENABLE 34
125 #define OPAL_PCI_GET_XIVE_REISSUE 35
126 #define OPAL_PCI_SET_XIVE_REISSUE 36
127 #define OPAL_PCI_SET_XIVE_PE 37
128 #define OPAL_GET_XIVE_SOURCE 38
129 #define OPAL_GET_MSI_32 39
130 #define OPAL_GET_MSI_64 40
131 #define OPAL_START_CPU 41
132 #define OPAL_QUERY_CPU_STATUS 42
133 #define OPAL_WRITE_OPPANEL 43
134 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
135 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
136 #define OPAL_PCI_RESET 49
137 #define OPAL_PCI_GET_HUB_DIAG_DATA 50
138 #define OPAL_PCI_GET_PHB_DIAG_DATA 51
139 #define OPAL_PCI_FENCE_PHB 52
140 #define OPAL_PCI_REINIT 53
141 #define OPAL_PCI_MASK_PE_ERROR 54
142 #define OPAL_SET_SLOT_LED_STATUS 55
143 #define OPAL_GET_EPOW_STATUS 56
144 #define OPAL_SET_SYSTEM_ATTENTION_LED 57
145 #define OPAL_RESERVED1 58
146 #define OPAL_RESERVED2 59
147 #define OPAL_PCI_NEXT_ERROR 60
148 #define OPAL_PCI_EEH_FREEZE_STATUS2 61
149 #define OPAL_PCI_POLL 62
150 #define OPAL_PCI_MSI_EOI 63
151 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
152 #define OPAL_XSCOM_READ 65
153 #define OPAL_XSCOM_WRITE 66
154 #define OPAL_LPC_READ 67
155 #define OPAL_LPC_WRITE 68
156 #define OPAL_RETURN_CPU 69
157 #define OPAL_ELOG_READ 71
158 #define OPAL_ELOG_WRITE 72
159 #define OPAL_ELOG_ACK 73
160 #define OPAL_ELOG_RESEND 74
161 #define OPAL_ELOG_SIZE 75
162 #define OPAL_FLASH_VALIDATE 76
163 #define OPAL_FLASH_MANAGE 77
164 #define OPAL_FLASH_UPDATE 78
165 #define OPAL_RESYNC_TIMEBASE 79
166 #define OPAL_DUMP_INIT 81
167 #define OPAL_DUMP_INFO 82
168 #define OPAL_DUMP_READ 83
169 #define OPAL_DUMP_ACK 84
170 #define OPAL_GET_MSG 85
171 #define OPAL_CHECK_ASYNC_COMPLETION 86
172 #define OPAL_SYNC_HOST_REBOOT 87
173 #define OPAL_SENSOR_READ 88
174 #define OPAL_GET_PARAM 89
175 #define OPAL_SET_PARAM 90
176 #define OPAL_DUMP_RESEND 91
177 #define OPAL_DUMP_INFO2 94
181 #include <linux/notifier.h>
184 enum OpalVendorApiTokens {
185 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
188 enum OpalFreezeState {
189 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
190 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
191 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
192 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
193 OPAL_EEH_STOPPED_RESET = 4,
194 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
195 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
198 enum OpalEehFreezeActionToken {
199 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
200 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
201 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
204 enum OpalPciStatusToken {
205 OPAL_EEH_NO_ERROR = 0,
206 OPAL_EEH_IOC_ERROR = 1,
207 OPAL_EEH_PHB_ERROR = 2,
208 OPAL_EEH_PE_ERROR = 3,
209 OPAL_EEH_PE_MMIO_ERROR = 4,
210 OPAL_EEH_PE_DMA_ERROR = 5
213 enum OpalPciErrorSeverity {
214 OPAL_EEH_SEV_NO_ERROR = 0,
215 OPAL_EEH_SEV_IOC_DEAD = 1,
216 OPAL_EEH_SEV_PHB_DEAD = 2,
217 OPAL_EEH_SEV_PHB_FENCED = 3,
218 OPAL_EEH_SEV_PE_ER = 4,
222 enum OpalShpcAction {
223 OPAL_SHPC_GET_LINK_STATE = 0,
224 OPAL_SHPC_GET_SLOT_STATE = 1
227 enum OpalShpcLinkState {
228 OPAL_SHPC_LINK_DOWN = 0,
229 OPAL_SHPC_LINK_UP = 1
232 enum OpalMmioWindowType {
233 OPAL_M32_WINDOW_TYPE = 1,
234 OPAL_M64_WINDOW_TYPE = 2,
235 OPAL_IO_WINDOW_TYPE = 3
238 enum OpalShpcSlotState {
239 OPAL_SHPC_DEV_NOT_PRESENT = 0,
240 OPAL_SHPC_DEV_PRESENT = 1
243 enum OpalExceptionHandler {
244 OPAL_MACHINE_CHECK_HANDLER = 1,
245 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
246 OPAL_SOFTPATCH_HANDLER = 3
249 enum OpalPendingState {
250 OPAL_EVENT_OPAL_INTERNAL = 0x1,
251 OPAL_EVENT_NVRAM = 0x2,
252 OPAL_EVENT_RTC = 0x4,
253 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
254 OPAL_EVENT_CONSOLE_INPUT = 0x10,
255 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
256 OPAL_EVENT_ERROR_LOG = 0x40,
257 OPAL_EVENT_EPOW = 0x80,
258 OPAL_EVENT_LED_STATUS = 0x100,
259 OPAL_EVENT_PCI_ERROR = 0x200,
260 OPAL_EVENT_DUMP_AVAIL = 0x400,
261 OPAL_EVENT_MSG_PENDING = 0x800,
264 enum OpalMessageType {
265 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
266 * additional params function-specific
274 /* Machine check related definitions */
275 enum OpalMCE_Version {
279 enum OpalMCE_Severity {
280 OpalMCE_SEV_NO_ERROR = 0,
281 OpalMCE_SEV_WARNING = 1,
282 OpalMCE_SEV_ERROR_SYNC = 2,
283 OpalMCE_SEV_FATAL = 3,
286 enum OpalMCE_Disposition {
287 OpalMCE_DISPOSITION_RECOVERED = 0,
288 OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
291 enum OpalMCE_Initiator {
292 OpalMCE_INITIATOR_UNKNOWN = 0,
293 OpalMCE_INITIATOR_CPU = 1,
296 enum OpalMCE_ErrorType {
297 OpalMCE_ERROR_TYPE_UNKNOWN = 0,
298 OpalMCE_ERROR_TYPE_UE = 1,
299 OpalMCE_ERROR_TYPE_SLB = 2,
300 OpalMCE_ERROR_TYPE_ERAT = 3,
301 OpalMCE_ERROR_TYPE_TLB = 4,
304 enum OpalMCE_UeErrorType {
305 OpalMCE_UE_ERROR_INDETERMINATE = 0,
306 OpalMCE_UE_ERROR_IFETCH = 1,
307 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
308 OpalMCE_UE_ERROR_LOAD_STORE = 3,
309 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
312 enum OpalMCE_SlbErrorType {
313 OpalMCE_SLB_ERROR_INDETERMINATE = 0,
314 OpalMCE_SLB_ERROR_PARITY = 1,
315 OpalMCE_SLB_ERROR_MULTIHIT = 2,
318 enum OpalMCE_EratErrorType {
319 OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
320 OpalMCE_ERAT_ERROR_PARITY = 1,
321 OpalMCE_ERAT_ERROR_MULTIHIT = 2,
324 enum OpalMCE_TlbErrorType {
325 OpalMCE_TLB_ERROR_INDETERMINATE = 0,
326 OpalMCE_TLB_ERROR_PARITY = 1,
327 OpalMCE_TLB_ERROR_MULTIHIT = 2,
330 enum OpalThreadStatus {
331 OPAL_THREAD_INACTIVE = 0x0,
332 OPAL_THREAD_STARTED = 0x1,
333 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
336 enum OpalPciBusCompare {
337 OpalPciBusAny = 0, /* Any bus number match */
338 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
339 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
340 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
341 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
342 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
343 OpalPciBusAll = 7, /* Match bus number exactly */
346 enum OpalDeviceCompare {
347 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
348 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
351 enum OpalFuncCompare {
352 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
353 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
361 enum OpalPeltvAction {
362 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
363 OPAL_ADD_PE_TO_DOMAIN = 1
366 enum OpalMveEnableAction {
367 OPAL_DISABLE_MVE = 0,
371 enum OpalPciResetScope {
372 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
373 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
374 OPAL_PCI_IODA_TABLE_RESET = 6,
377 enum OpalPciReinitScope {
378 OPAL_REINIT_PCI_DEV = 1000
381 enum OpalPciResetState {
382 OPAL_DEASSERT_RESET = 0,
383 OPAL_ASSERT_RESET = 1
386 enum OpalPciMaskAction {
387 OPAL_UNMASK_ERROR_TYPE = 0,
388 OPAL_MASK_ERROR_TYPE = 1
391 enum OpalSlotLedType {
392 OPAL_SLOT_LED_ID_TYPE = 0,
393 OPAL_SLOT_LED_FAULT_TYPE = 1
397 OPAL_TURN_OFF_LED = 0,
398 OPAL_TURN_ON_LED = 1,
399 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
402 enum OpalEpowStatus {
405 OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
406 OPAL_EPOW_OVER_INTERNAL_TEMP = 3
410 * Address cycle types for LPC accesses. These also correspond
411 * to the content of the first cell of the "reg" property for
412 * device nodes on the LPC bus
414 enum OpalLPCAddressType {
420 /* System parameter permission */
421 enum OpalSysparamPerm {
422 OPAL_SYSPARAM_READ = 0x1,
423 OPAL_SYSPARAM_WRITE = 0x2,
424 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
433 struct opal_machine_check_event {
434 enum OpalMCE_Version version:8; /* 0x00 */
435 uint8_t in_use; /* 0x01 */
436 enum OpalMCE_Severity severity:8; /* 0x02 */
437 enum OpalMCE_Initiator initiator:8; /* 0x03 */
438 enum OpalMCE_ErrorType error_type:8; /* 0x04 */
439 enum OpalMCE_Disposition disposition:8; /* 0x05 */
440 uint8_t reserved_1[2]; /* 0x06 */
441 uint64_t gpr3; /* 0x08 */
442 uint64_t srr0; /* 0x10 */
443 uint64_t srr1; /* 0x18 */
446 enum OpalMCE_UeErrorType ue_error_type:8;
447 uint8_t effective_address_provided;
448 uint8_t physical_address_provided;
449 uint8_t reserved_1[5];
450 uint64_t effective_address;
451 uint64_t physical_address;
452 uint8_t reserved_2[8];
456 enum OpalMCE_SlbErrorType slb_error_type:8;
457 uint8_t effective_address_provided;
458 uint8_t reserved_1[6];
459 uint64_t effective_address;
460 uint8_t reserved_2[16];
464 enum OpalMCE_EratErrorType erat_error_type:8;
465 uint8_t effective_address_provided;
466 uint8_t reserved_1[6];
467 uint64_t effective_address;
468 uint8_t reserved_2[16];
472 enum OpalMCE_TlbErrorType tlb_error_type:8;
473 uint8_t effective_address_provided;
474 uint8_t reserved_1[6];
475 uint64_t effective_address;
476 uint8_t reserved_2[16];
481 /* FSP memory errors handling */
482 enum OpalMemErr_Version {
486 enum OpalMemErrType {
487 OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
488 OPAL_MEM_ERR_TYPE_DYN_DALLOC,
489 OPAL_MEM_ERR_TYPE_SCRUB,
492 /* Memory Reilience error type */
493 enum OpalMemErr_ResilErrType {
494 OPAL_MEM_RESILIENCE_CE = 0,
495 OPAL_MEM_RESILIENCE_UE,
496 OPAL_MEM_RESILIENCE_UE_SCRUB,
499 /* Dynamic Memory Deallocation type */
500 enum OpalMemErr_DynErrType {
501 OPAL_MEM_DYNAMIC_DEALLOC = 0,
504 /* OpalMemoryErrorData->flags */
505 #define OPAL_MEM_CORRECTED_ERROR 0x0001
506 #define OPAL_MEM_THRESHOLD_EXCEEDED 0x0002
507 #define OPAL_MEM_ACK_REQUIRED 0x8000
509 struct OpalMemoryErrorData {
510 enum OpalMemErr_Version version:8; /* 0x00 */
511 enum OpalMemErrType type:8; /* 0x01 */
512 uint16_t flags; /* 0x02 */
513 uint8_t reserved_1[4]; /* 0x04 */
516 /* Memory Resilience corrected/uncorrected error info */
518 enum OpalMemErr_ResilErrType resil_err_type:8;
519 uint8_t reserved_1[7];
520 uint64_t physical_address_start;
521 uint64_t physical_address_end;
523 /* Dynamic memory deallocation error info */
525 enum OpalMemErr_DynErrType dyn_err_type:8;
526 uint8_t reserved_1[7];
527 uint64_t physical_address_start;
528 uint64_t physical_address_end;
534 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
535 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
536 OPAL_P7IOC_DIAG_TYPE_BI = 2,
537 OPAL_P7IOC_DIAG_TYPE_CI = 3,
538 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
539 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
540 OPAL_P7IOC_DIAG_TYPE_LAST = 6
543 struct OpalIoP7IOCErrorData {
561 struct OpalIoP7IOCRgcErrorData {
562 uint64_t rgcStatus; /* 3E1C10 */
563 uint64_t rgcLdcp; /* 3E1C18 */
565 struct OpalIoP7IOCBiErrorData {
566 uint64_t biLdcp0; /* 3C0100, 3C0118 */
567 uint64_t biLdcp1; /* 3C0108, 3C0120 */
568 uint64_t biLdcp2; /* 3C0110, 3C0128 */
569 uint64_t biFenceStatus; /* 3C0130, 3C0130 */
571 uint8_t biDownbound; /* BI Downbound or Upbound */
573 struct OpalIoP7IOCCiErrorData {
574 uint64_t ciPortStatus; /* 3Dn008 */
575 uint64_t ciPortLdcp; /* 3Dn010 */
577 uint8_t ciPort; /* Index of CI port: 0/1 */
583 * This structure defines the overlay which will be used to store PHB error
587 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
591 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
592 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
596 OPAL_P7IOC_NUM_PEST_REGS = 128,
597 OPAL_PHB3_NUM_PEST_REGS = 256
600 struct OpalIoPhbErrorCommon {
606 struct OpalIoP7IOCPhbErrorData {
607 struct OpalIoPhbErrorCommon common;
612 uint32_t portStatusReg;
613 uint32_t rootCmplxStatus;
614 uint32_t busAgentStatus;
617 uint32_t deviceStatus;
620 uint32_t devCmdStatus;
621 uint32_t devSecStatus;
624 uint32_t rootErrorStatus;
625 uint32_t uncorrErrorStatus;
626 uint32_t corrErrorStatus;
635 // Record data about the call to allocate a buffer.
639 //P7IOC MMIO Error Regs
640 uint64_t p7iocPlssr; // n120
641 uint64_t p7iocCsr; // n110
642 uint64_t lemFir; // nC00
643 uint64_t lemErrorMask; // nC18
644 uint64_t lemWOF; // nC40
645 uint64_t phbErrorStatus; // nC80
646 uint64_t phbFirstErrorStatus; // nC88
647 uint64_t phbErrorLog0; // nCC0
648 uint64_t phbErrorLog1; // nCC8
649 uint64_t mmioErrorStatus; // nD00
650 uint64_t mmioFirstErrorStatus; // nD08
651 uint64_t mmioErrorLog0; // nD40
652 uint64_t mmioErrorLog1; // nD48
653 uint64_t dma0ErrorStatus; // nD80
654 uint64_t dma0FirstErrorStatus; // nD88
655 uint64_t dma0ErrorLog0; // nDC0
656 uint64_t dma0ErrorLog1; // nDC8
657 uint64_t dma1ErrorStatus; // nE00
658 uint64_t dma1FirstErrorStatus; // nE08
659 uint64_t dma1ErrorLog0; // nE40
660 uint64_t dma1ErrorLog1; // nE48
661 uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
662 uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
665 struct OpalIoPhb3ErrorData {
666 struct OpalIoPhbErrorCommon common;
671 uint32_t portStatusReg;
672 uint32_t rootCmplxStatus;
673 uint32_t busAgentStatus;
676 uint32_t deviceStatus;
679 uint32_t devCmdStatus;
680 uint32_t devSecStatus;
683 uint32_t rootErrorStatus;
684 uint32_t uncorrErrorStatus;
685 uint32_t corrErrorStatus;
694 /* Record data about the call to allocate a buffer */
698 uint64_t nFir; /* 000 */
699 uint64_t nFirMask; /* 003 */
700 uint64_t nFirWOF; /* 008 */
702 /* PHB3 MMIO Error Regs */
703 uint64_t phbPlssr; /* 120 */
704 uint64_t phbCsr; /* 110 */
705 uint64_t lemFir; /* C00 */
706 uint64_t lemErrorMask; /* C18 */
707 uint64_t lemWOF; /* C40 */
708 uint64_t phbErrorStatus; /* C80 */
709 uint64_t phbFirstErrorStatus; /* C88 */
710 uint64_t phbErrorLog0; /* CC0 */
711 uint64_t phbErrorLog1; /* CC8 */
712 uint64_t mmioErrorStatus; /* D00 */
713 uint64_t mmioFirstErrorStatus; /* D08 */
714 uint64_t mmioErrorLog0; /* D40 */
715 uint64_t mmioErrorLog1; /* D48 */
716 uint64_t dma0ErrorStatus; /* D80 */
717 uint64_t dma0FirstErrorStatus; /* D88 */
718 uint64_t dma0ErrorLog0; /* DC0 */
719 uint64_t dma0ErrorLog1; /* DC8 */
720 uint64_t dma1ErrorStatus; /* E00 */
721 uint64_t dma1FirstErrorStatus; /* E08 */
722 uint64_t dma1ErrorLog0; /* E40 */
723 uint64_t dma1ErrorLog1; /* E48 */
724 uint64_t pestA[OPAL_PHB3_NUM_PEST_REGS];
725 uint64_t pestB[OPAL_PHB3_NUM_PEST_REGS];
728 typedef struct oppanel_line {
733 /* /sys/firmware/opal */
734 extern struct kobject *opal_kobj;
737 extern struct device_node *opal_node;
740 int64_t opal_invalid_call(void);
741 int64_t opal_console_write(int64_t term_number, __be64 *length,
742 const uint8_t *buffer);
743 int64_t opal_console_read(int64_t term_number, __be64 *length,
745 int64_t opal_console_write_buffer_space(int64_t term_number,
747 int64_t opal_rtc_read(__be32 *year_month_day,
748 __be64 *hour_minute_second_millisecond);
749 int64_t opal_rtc_write(uint32_t year_month_day,
750 uint64_t hour_minute_second_millisecond);
751 int64_t opal_cec_power_down(uint64_t request);
752 int64_t opal_cec_reboot(void);
753 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
754 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
755 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
756 int64_t opal_poll_events(__be64 *outstanding_event_mask);
757 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
758 uint64_t tce_mem_size);
759 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
760 uint64_t tce_mem_size);
761 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
762 uint64_t offset, uint8_t *data);
763 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
764 uint64_t offset, __be16 *data);
765 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
766 uint64_t offset, __be32 *data);
767 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
768 uint64_t offset, uint8_t data);
769 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
770 uint64_t offset, uint16_t data);
771 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
772 uint64_t offset, uint32_t data);
773 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
774 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
775 int64_t opal_register_exception_handler(uint64_t opal_exception,
776 uint64_t handler_address,
777 uint64_t glue_cache_line);
778 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
779 uint8_t *freeze_state,
780 __be16 *pci_error_type,
782 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
783 uint64_t eeh_action_token);
784 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
788 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
789 uint16_t window_num, uint16_t enable);
790 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
792 uint64_t starting_real_address,
793 uint64_t starting_pci_address,
794 uint16_t segment_size);
795 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
796 uint16_t window_type, uint16_t window_num,
797 uint16_t segment_num);
798 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
799 uint64_t ivt_addr, uint64_t ivt_len,
800 uint64_t reject_array_addr,
801 uint64_t peltv_addr);
802 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
803 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
805 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
807 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
808 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
810 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
811 uint8_t *p_bit, uint8_t *q_bit);
812 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
813 uint8_t p_bit, uint8_t q_bit);
814 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
815 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
817 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
818 __be32 *interrupt_source_number);
819 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
820 uint8_t msi_range, __be32 *msi_address,
821 __be32 *message_data);
822 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
823 uint32_t xive_num, uint8_t msi_range,
824 __be64 *msi_address, __be32 *message_data);
825 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
826 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
827 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
828 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
829 uint16_t tce_levels, uint64_t tce_table_addr,
830 uint64_t tce_table_size, uint64_t tce_page_size);
831 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
832 uint16_t dma_window_number, uint64_t pci_start_addr,
833 uint64_t pci_mem_size);
834 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
836 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
837 uint64_t diag_buffer_len);
838 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
839 uint64_t diag_buffer_len);
840 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
841 uint64_t diag_buffer_len);
842 int64_t opal_pci_fence_phb(uint64_t phb_id);
843 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
844 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
845 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
846 int64_t opal_get_epow_status(__be64 *status);
847 int64_t opal_set_system_attention_led(uint8_t led_action);
848 int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
849 uint16_t *pci_error_type, uint16_t *severity);
850 int64_t opal_pci_poll(uint64_t phb_id);
851 int64_t opal_return_cpu(void);
853 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
854 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
856 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
857 uint32_t addr, uint32_t data, uint32_t sz);
858 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
859 uint32_t addr, __be32 *data, uint32_t sz);
861 int64_t opal_read_elog(uint64_t buffer, size_t size, uint64_t log_id);
862 int64_t opal_get_elog_size(uint64_t *log_id, size_t *size, uint64_t *elog_type);
863 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
864 int64_t opal_send_ack_elog(uint64_t log_id);
865 void opal_resend_pending_logs(void);
867 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
868 int64_t opal_manage_flash(uint8_t op);
869 int64_t opal_update_flash(uint64_t blk_list);
870 int64_t opal_dump_init(uint8_t dump_type);
871 int64_t opal_dump_info(uint32_t *dump_id, uint32_t *dump_size);
872 int64_t opal_dump_info2(uint32_t *dump_id, uint32_t *dump_size, uint32_t *dump_type);
873 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
874 int64_t opal_dump_ack(uint32_t dump_id);
875 int64_t opal_dump_resend_notification(void);
877 int64_t opal_get_msg(uint64_t buffer, size_t size);
878 int64_t opal_check_completion(uint64_t buffer, size_t size, uint64_t token);
879 int64_t opal_sync_host_reboot(void);
880 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
882 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
884 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
886 /* Internal functions */
887 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
888 extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
889 const char *uname, int depth, void *data);
891 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
892 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
894 extern void hvc_opal_init_early(void);
896 /* Internal functions */
897 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
898 int depth, void *data);
900 extern int opal_notifier_register(struct notifier_block *nb);
901 extern int opal_notifier_unregister(struct notifier_block *nb);
903 extern int opal_message_notifier_register(enum OpalMessageType msg_type,
904 struct notifier_block *nb);
905 extern void opal_notifier_enable(void);
906 extern void opal_notifier_disable(void);
907 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
909 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
910 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
912 extern int __opal_async_get_token(void);
913 extern int opal_async_get_token_interruptible(void);
914 extern int __opal_async_release_token(int token);
915 extern int opal_async_release_token(int token);
916 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
917 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
919 extern void hvc_opal_init_early(void);
922 extern int opal_set_rtc_time(struct rtc_time *tm);
923 extern void opal_get_rtc_time(struct rtc_time *tm);
924 extern unsigned long opal_get_boot_time(void);
925 extern void opal_nvram_init(void);
926 extern void opal_flash_init(void);
927 extern int opal_elog_init(void);
928 extern void opal_platform_dump_init(void);
929 extern void opal_sys_param_init(void);
930 extern void opal_msglog_init(void);
932 extern int opal_machine_check(struct pt_regs *regs);
933 extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
935 extern void opal_shutdown(void);
936 extern int opal_resync_timebase(void);
938 extern void opal_lpc_init(void);
940 #endif /* __ASSEMBLY__ */
942 #endif /* __OPAL_H */