2 * Device Tree for Bluestone (APM821xx) board.
4 * Copyright (c) 2010, Applied Micro Circuits Corporation
5 * Author: Tirumala R Marri <tmarri@apm.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 model = "apm,bluestone";
30 compatible = "apm,bluestone";
31 dcr-parent = <&{/cpus/cpu@0}>;
45 model = "PowerPC,apm821xx";
47 clock-frequency = <0>; /* Filled in by U-Boot */
48 timebase-frequency = <0>; /* Filled in by U-Boot */
49 i-cache-line-size = <32>;
50 d-cache-line-size = <32>;
51 i-cache-size = <32768>;
52 d-cache-size = <32768>;
54 dcr-access-method = "native";
55 next-level-cache = <&L2C0>;
60 device_type = "memory";
61 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
64 UIC0: interrupt-controller0 {
65 compatible = "ibm,uic";
68 dcr-reg = <0x0c0 0x009>;
71 #interrupt-cells = <2>;
74 UIC1: interrupt-controller1 {
75 compatible = "ibm,uic";
78 dcr-reg = <0x0d0 0x009>;
81 #interrupt-cells = <2>;
82 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
83 interrupt-parent = <&UIC0>;
86 UIC2: interrupt-controller2 {
87 compatible = "ibm,uic";
90 dcr-reg = <0x0e0 0x009>;
93 #interrupt-cells = <2>;
94 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
95 interrupt-parent = <&UIC0>;
98 UIC3: interrupt-controller3 {
99 compatible = "ibm,uic";
100 interrupt-controller;
102 dcr-reg = <0x0f0 0x009>;
103 #address-cells = <0>;
105 #interrupt-cells = <2>;
106 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
107 interrupt-parent = <&UIC0>;
111 compatible = "ibm,sdr-apm821xx";
112 dcr-reg = <0x00e 0x002>;
116 compatible = "ibm,cpr-apm821xx";
117 dcr-reg = <0x00c 0x002>;
121 compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
122 dcr-reg = <0x020 0x008
124 cache-line-size = <32>;
125 cache-size = <262144>;
126 interrupt-parent = <&UIC1>;
131 compatible = "ibm,plb4";
132 #address-cells = <2>;
135 clock-frequency = <0>; /* Filled in by U-Boot */
138 compatible = "ibm,sdram-apm821xx";
139 dcr-reg = <0x010 0x002>;
143 compatible = "ibm,mcmal2";
144 descriptor-memory = "ocm";
145 dcr-reg = <0x180 0x062>;
148 #address-cells = <0>;
150 interrupt-parent = <&UIC2>;
151 interrupts = < /*TXEOB*/ 0x6 0x4
159 compatible = "ibm,opb";
160 #address-cells = <1>;
162 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
163 clock-frequency = <0>; /* Filled in by U-Boot */
166 compatible = "ibm,ebc";
167 dcr-reg = <0x012 0x002>;
168 #address-cells = <2>;
170 clock-frequency = <0>; /* Filled in by U-Boot */
171 /* ranges property is supplied by U-Boot */
172 ranges = < 0x00000003 0x00000000 0xe0000000 0x8000000>;
173 interrupts = <0x6 0x4>;
174 interrupt-parent = <&UIC1>;
177 compatible = "amd,s29gl512n", "cfi-flash";
179 reg = <0x00000000 0x00000000 0x00400000>;
180 #address-cells = <1>;
184 reg = <0x00000000 0x00180000>;
188 reg = <0x00180000 0x00020000>;
192 reg = <0x001a0000 0x00060000>;
197 compatible = "ibm,ndfc";
198 reg = <0x00000003 0x00000000 0x00002000>;
200 bank-settings = <0x80002222>;
201 #address-cells = <1>;
205 #address-cells = <1>;
210 reg = <0x00000000 0x00C00000>;
213 label = "environment";
214 reg = <0x00C00000 0x00B00000>;
218 reg = <0x01700000 0x00E00000>;
222 reg = <0x02500000 0x08200000>;
225 label = "device-tree";
226 reg = <0x0A700000 0x00B00000>;
230 reg = <0x0B200000 0x00D00000>;
234 reg = <0x0BF00000 0x00C00000>;
238 reg = <0x0CB00000 0x3500000>;
244 UART0: serial@ef600300 {
245 device_type = "serial";
246 compatible = "ns16550";
247 reg = <0xef600300 0x00000008>;
248 virtual-reg = <0xef600300>;
249 clock-frequency = <0>; /* Filled in by U-Boot */
250 current-speed = <0>; /* Filled in by U-Boot */
251 interrupt-parent = <&UIC1>;
252 interrupts = <0x1 0x4>;
255 UART1: serial@ef600400 {
256 device_type = "serial";
257 compatible = "ns16550";
258 reg = <0xef600400 0x00000008>;
259 virtual-reg = <0xef600400>;
260 clock-frequency = <0>; /* Filled in by U-Boot */
261 current-speed = <0>; /* Filled in by U-Boot */
262 interrupt-parent = <&UIC0>;
263 interrupts = <0x1 0x4>;
267 compatible = "ibm,iic";
268 reg = <0xef600700 0x00000014>;
269 interrupt-parent = <&UIC0>;
270 interrupts = <0x2 0x4>;
271 #address-cells = <1>;
274 compatible = "stm,m41t80";
276 interrupt-parent = <&UIC0>;
277 interrupts = <0x9 0x8>;
280 compatible = "adm,adm1032";
282 interrupt-parent = <&UIC1>;
283 interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
288 compatible = "ibm,iic";
289 reg = <0xef600800 0x00000014>;
290 interrupt-parent = <&UIC0>;
291 interrupts = <0x3 0x4>;
294 RGMII0: emac-rgmii@ef601500 {
295 compatible = "ibm,rgmii";
296 reg = <0xef601500 0x00000008>;
300 TAH0: emac-tah@ef601350 {
301 compatible = "ibm,tah";
302 reg = <0xef601350 0x00000030>;
305 EMAC0: ethernet@ef600c00 {
306 device_type = "network";
307 compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
308 interrupt-parent = <&EMAC0>;
309 interrupts = <0x0 0x1>;
310 #interrupt-cells = <1>;
311 #address-cells = <0>;
313 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
314 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
315 reg = <0xef600c00 0x000000c4>;
316 local-mac-address = [000000000000]; /* Filled in by U-Boot */
317 mal-device = <&MAL0>;
318 mal-tx-channel = <0>;
319 mal-rx-channel = <0>;
321 max-frame-size = <9000>;
322 rx-fifo-size = <16384>;
323 tx-fifo-size = <2048>;
325 phy-map = <0x00000000>;
326 rgmii-device = <&RGMII0>;
328 tah-device = <&TAH0>;
330 has-inverted-stacr-oc;
331 has-new-stacr-staopc;
335 PCIE0: pciex@d00000000 {
337 #interrupt-cells = <1>;
339 #address-cells = <3>;
340 compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
342 port = <0x0>; /* port number */
343 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
344 0x0000000c 0x08010000 0x00001000>; /* Registers */
345 dcr-reg = <0x100 0x020>;
348 /* Outbound ranges, one memory and one IO,
349 * later cannot be changed
351 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
352 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
353 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
355 /* Inbound 2GB range starting at 0 */
356 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
358 /* This drives busses 40 to 0x7f */
359 bus-range = <0x40 0x7f>;
361 /* Legacy interrupts (note the weird polarity, the bridge seems
362 * to invert PCIe legacy interrupts).
363 * We are de-swizzling here because the numbers are actually for
364 * port of the root complex virtual P2P bridge. But I want
365 * to avoid putting a node for it in the tree, so the numbers
366 * below are basically de-swizzled numbers.
367 * The real slot is on idsel 0, so the swizzling is 1:1
369 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
371 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
372 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
373 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
374 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;