1 /* MN10300 Arch-specific interrupt handling
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/seq_file.h>
15 #include <linux/cpumask.h>
16 #include <asm/setup.h>
17 #include <asm/serial-regs.h>
19 unsigned long __mn10300_irq_enabled_epsw[NR_CPUS] __cacheline_aligned_in_smp = {
20 [0 ... NR_CPUS - 1] = EPSW_IE | EPSW_IM_7
22 EXPORT_SYMBOL(__mn10300_irq_enabled_epsw);
25 static char irq_affinity_online[NR_IRQS] = {
26 [0 ... NR_IRQS - 1] = 0
29 #define NR_IRQ_WORDS ((NR_IRQS + 31) / 32)
30 static unsigned long irq_affinity_request[NR_IRQ_WORDS] = {
31 [0 ... NR_IRQ_WORDS - 1] = 0
33 #endif /* CONFIG_SMP */
35 atomic_t irq_err_count;
38 * MN10300 interrupt controller operations
40 static void mn10300_cpupic_ack(struct irq_data *d)
42 unsigned int irq = d->irq;
46 flags = arch_local_cli_save();
47 GxICR_u8(irq) = GxICR_DETECT;
49 arch_local_irq_restore(flags);
52 static void __mask_and_set_icr(unsigned int irq,
53 unsigned int mask, unsigned int set)
58 flags = arch_local_cli_save();
60 GxICR(irq) = (tmp & mask) | set;
62 arch_local_irq_restore(flags);
65 static void mn10300_cpupic_mask(struct irq_data *d)
67 __mask_and_set_icr(d->irq, GxICR_LEVEL, 0);
70 static void mn10300_cpupic_mask_ack(struct irq_data *d)
72 unsigned int irq = d->irq;
77 flags = arch_local_cli_save();
79 if (!test_and_clear_bit(irq, irq_affinity_request)) {
81 GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT;
86 GxICR(irq) = (tmp & GxICR_LEVEL);
89 irq_affinity_online[irq] =
90 any_online_cpu(*d->affinity);
91 CROSS_GxICR(irq, irq_affinity_online[irq]) =
92 (tmp & (GxICR_LEVEL | GxICR_ENABLE)) | GxICR_DETECT;
93 tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
96 arch_local_irq_restore(flags);
97 #else /* CONFIG_SMP */
98 __mask_and_set_icr(irq, GxICR_LEVEL, GxICR_DETECT);
99 #endif /* CONFIG_SMP */
102 static void mn10300_cpupic_unmask(struct irq_data *d)
104 __mask_and_set_icr(d->irq, GxICR_LEVEL, GxICR_ENABLE);
107 static void mn10300_cpupic_unmask_clear(struct irq_data *d)
109 unsigned int irq = d->irq;
110 /* the MN10300 PIC latches its interrupt request bit, even after the
111 * device has ceased to assert its interrupt line and the interrupt
112 * channel has been disabled in the PIC, so for level-triggered
113 * interrupts we need to clear the request bit when we re-enable */
118 flags = arch_local_cli_save();
120 if (!test_and_clear_bit(irq, irq_affinity_request)) {
122 GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT;
127 irq_affinity_online[irq] = any_online_cpu(*d->affinity);
128 CROSS_GxICR(irq, irq_affinity_online[irq]) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT;
129 tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
132 arch_local_irq_restore(flags);
133 #else /* CONFIG_SMP */
134 __mask_and_set_icr(irq, GxICR_LEVEL, GxICR_ENABLE | GxICR_DETECT);
135 #endif /* CONFIG_SMP */
140 mn10300_cpupic_setaffinity(struct irq_data *d, const struct cpumask *mask,
146 flags = arch_local_cli_save();
152 case CALL_FUNC_SINGLE_IPI:
153 case LOCAL_TIMER_IPI:
154 case FLUSH_CACHE_IPI:
155 case CALL_FUNCTION_NMI_IPI:
156 case DEBUGGER_NMI_IPI:
157 #ifdef CONFIG_MN10300_TTYSM0
160 #ifdef CONFIG_MN10300_TTYSM0_TIMER8
162 #elif CONFIG_MN10300_TTYSM0_TIMER2
164 #endif /* CONFIG_MN10300_TTYSM0_TIMER8 */
165 #endif /* CONFIG_MN10300_TTYSM0 */
167 #ifdef CONFIG_MN10300_TTYSM1
170 #ifdef CONFIG_MN10300_TTYSM1_TIMER12
172 #elif CONFIG_MN10300_TTYSM1_TIMER9
174 #elif CONFIG_MN10300_TTYSM1_TIMER3
176 #endif /* CONFIG_MN10300_TTYSM1_TIMER12 */
177 #endif /* CONFIG_MN10300_TTYSM1 */
179 #ifdef CONFIG_MN10300_TTYSM2
183 #endif /* CONFIG_MN10300_TTYSM2 */
188 set_bit(d->irq, irq_affinity_request);
193 arch_local_irq_restore(flags);
196 #endif /* CONFIG_SMP */
199 * MN10300 PIC level-triggered IRQ handling.
201 * The PIC has no 'ACK' function per se. It is possible to clear individual
202 * channel latches, but each latch relatches whether or not the channel is
203 * masked, so we need to clear the latch when we unmask the channel.
205 * Also for this reason, we don't supply an ack() op (it's unused anyway if
206 * mask_ack() is provided), and mask_ack() just masks.
208 static struct irq_chip mn10300_cpu_pic_level = {
210 .irq_disable = mn10300_cpupic_mask,
211 .irq_enable = mn10300_cpupic_unmask_clear,
213 .irq_mask = mn10300_cpupic_mask,
214 .irq_mask_ack = mn10300_cpupic_mask,
215 .irq_unmask = mn10300_cpupic_unmask_clear,
217 .irq_set_affinity = mn10300_cpupic_setaffinity,
222 * MN10300 PIC edge-triggered IRQ handling.
224 * We use the latch clearing function of the PIC as the 'ACK' function.
226 static struct irq_chip mn10300_cpu_pic_edge = {
228 .irq_disable = mn10300_cpupic_mask,
229 .irq_enable = mn10300_cpupic_unmask,
230 .irq_ack = mn10300_cpupic_ack,
231 .irq_mask = mn10300_cpupic_mask,
232 .irq_mask_ack = mn10300_cpupic_mask_ack,
233 .irq_unmask = mn10300_cpupic_unmask,
235 .irq_set_affinity = mn10300_cpupic_setaffinity,
240 * 'what should we do if we get a hw irq event on an illegal vector'.
241 * each architecture has to answer this themselves.
243 void ack_bad_irq(int irq)
245 printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq);
249 * change the level at which an IRQ executes
250 * - must not be called whilst interrupts are being processed!
252 void set_intr_level(int irq, u16 level)
254 BUG_ON(in_interrupt());
256 __mask_and_set_icr(irq, GxICR_ENABLE, level);
260 * mark an interrupt to be ACK'd after interrupt handlers have been run rather
262 * - see Documentation/mn10300/features.txt
264 void mn10300_set_lateack_irq_type(int irq)
266 irq_set_chip_and_handler(irq, &mn10300_cpu_pic_level,
271 * initialise the interrupt system
273 void __init init_IRQ(void)
277 for (irq = 0; irq < NR_IRQS; irq++)
278 if (irq_get_chip(irq) == &no_irq_chip)
279 /* due to the PIC latching interrupt requests, even
280 * when the IRQ is disabled, IRQ_PENDING is superfluous
281 * and we can use handle_level_irq() for edge-triggered
283 irq_set_chip_and_handler(irq, &mn10300_cpu_pic_edge,
290 * handle normal device IRQs
292 asmlinkage void do_IRQ(void)
294 unsigned long sp, epsw, irq_disabled_epsw, old_irq_enabled_epsw;
295 unsigned int cpu_id = smp_processor_id();
298 sp = current_stack_pointer();
299 BUG_ON(sp - (sp & ~(THREAD_SIZE - 1)) < STACK_WARN);
301 /* make sure local_irq_enable() doesn't muck up the interrupt priority
303 old_irq_enabled_epsw = __mn10300_irq_enabled_epsw[cpu_id];
304 local_save_flags(epsw);
305 __mn10300_irq_enabled_epsw[cpu_id] = EPSW_IE | (EPSW_IM & epsw);
306 irq_disabled_epsw = EPSW_IE | MN10300_CLI_LEVEL;
308 #ifdef CONFIG_MN10300_WD_TIMER
309 __IRQ_STAT(cpu_id, __irq_count)++;
315 /* ask the interrupt controller for the next IRQ to process
316 * - the result we get depends on EPSW.IM
318 irq = IAGR & IAGR_GN;
322 local_irq_restore(irq_disabled_epsw);
324 generic_handle_irq(irq >> 2);
326 /* restore IRQ controls for IAGR access */
327 local_irq_restore(epsw);
330 __mn10300_irq_enabled_epsw[cpu_id] = old_irq_enabled_epsw;
336 * Display interrupt management information through /proc/interrupts
338 int arch_show_interrupts(struct seq_file *p, int prec)
340 #ifdef CONFIG_MN10300_WD_TIMER
343 seq_printf(p, "%*s: ", prec, "NMI");
344 for (j = 0; j < NR_CPUS; j++)
346 seq_printf(p, "%10u ", nmi_count(j));
350 seq_printf(p, "%*s: ", prec, "ERR");
351 seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
355 #ifdef CONFIG_HOTPLUG_CPU
356 void migrate_irqs(void)
359 unsigned int self, new;
362 self = smp_processor_id();
363 for (irq = 0; irq < NR_IRQS; irq++) {
364 struct irq_data *data = irq_get_irq_data(irq);
366 if (irqd_is_per_cpu(data))
369 if (cpu_isset(self, data->affinity) &&
370 !cpus_intersects(irq_affinity[irq], cpu_online_map)) {
372 cpu_id = first_cpu(cpu_online_map);
373 cpu_set(cpu_id, data->affinity);
375 /* We need to operate irq_affinity_online atomically. */
376 arch_local_cli_save(flags);
377 if (irq_affinity_online[irq] == self) {
381 GxICR(irq) = x & GxICR_LEVEL;
384 new = any_online_cpu(data->affinity);
385 irq_affinity_online[irq] = new;
387 CROSS_GxICR(irq, new) =
388 (x & GxICR_LEVEL) | GxICR_DETECT;
389 tmp = CROSS_GxICR(irq, new);
391 x &= GxICR_LEVEL | GxICR_ENABLE;
392 if (GxICR(irq) & GxICR_REQUEST)
393 x |= GxICR_REQUEST | GxICR_DETECT;
394 CROSS_GxICR(irq, new) = x;
395 tmp = CROSS_GxICR(irq, new);
397 arch_local_irq_restore(flags);
400 #endif /* CONFIG_HOTPLUG_CPU */