2 * ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
4 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
5 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
6 * Copyright (C) 1999 - 2001 Kanoj Sarcar
8 #include <linux/config.h>
9 #include <linux/init.h>
10 #include <linux/irq.h>
11 #include <linux/errno.h>
12 #include <linux/signal.h>
13 #include <linux/sched.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/ioport.h>
17 #include <linux/timex.h>
18 #include <linux/slab.h>
19 #include <linux/random.h>
20 #include <linux/smp_lock.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/delay.h>
23 #include <linux/bitops.h>
25 #include <asm/bootinfo.h>
27 #include <asm/mipsregs.h>
28 #include <asm/system.h>
30 #include <asm/ptrace.h>
31 #include <asm/processor.h>
32 #include <asm/pci/bridge.h>
33 #include <asm/sn/addrs.h>
34 #include <asm/sn/agent.h>
35 #include <asm/sn/arch.h>
36 #include <asm/sn/hub.h>
37 #include <asm/sn/intr.h>
41 #define DBG(x...) printk(x)
47 * Linux has a controller-independent x86 interrupt architecture.
48 * every controller has a 'controller-template', that is used
49 * by the main code to do the right thing. Each driver-visible
50 * interrupt source is transparently wired to the apropriate
51 * controller. Thus drivers need not be aware of the
52 * interrupt-controller.
54 * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
55 * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
56 * (IO-APICs assumed to be messaging to Pentium local-APICs)
58 * the code is designed to be easily extended with new/different
59 * interrupt controllers, without having to do assembly magic.
62 extern asmlinkage void ip27_irq(void);
64 extern struct bridge_controller *irq_to_bridge[];
65 extern int irq_to_slot[];
68 * use these macros to get the encoded nasid and widget id
71 #define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)]
72 #define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i]
74 static inline int alloc_level(int cpu, int irq)
76 struct hub_data *hub = hub_data(cpu_to_node(cpu));
77 struct slice_data *si = cpu_data[cpu].data;
80 level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
81 if (level >= LEVELS_PER_SLICE)
82 panic("Cpu %d flooded with devices\n", cpu);
84 __set_bit(level, hub->irq_alloc_mask);
85 si->level_to_irq[level] = irq;
90 static inline int find_level(cpuid_t *cpunum, int irq)
94 for (cpu = 0; cpu <= NR_CPUS; cpu++) {
95 struct slice_data *si = cpu_data[cpu].data;
100 for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++)
101 if (si->level_to_irq[i] == irq) {
108 panic("Could not identify cpu/level for irq %d\n", irq);
114 static int ms1bit(unsigned long x)
118 s = 16; if (x >> 16 == 0) s = 0; b += s; x >>= s;
119 s = 8; if (x >> 8 == 0) s = 0; b += s; x >>= s;
120 s = 4; if (x >> 4 == 0) s = 0; b += s; x >>= s;
121 s = 2; if (x >> 2 == 0) s = 0; b += s; x >>= s;
122 s = 1; if (x >> 1 == 0) s = 0; b += s;
128 * This code is unnecessarily complex, because we do SA_INTERRUPT
129 * intr enabling. Basically, once we grab the set of intrs we need
130 * to service, we must mask _all_ these interrupts; firstly, to make
131 * sure the same intr does not intr again, causing recursion that
132 * can lead to stack overflow. Secondly, we can not just mask the
133 * one intr we are do_IRQing, because the non-masked intrs in the
134 * first set might intr again, causing multiple servicings of the
135 * same intr. This effect is mostly seen for intercpu intrs.
139 void ip27_do_irq_mask0(struct pt_regs *regs)
142 hubreg_t pend0, mask0;
143 cpuid_t cpu = smp_processor_id();
145 (cputoslice(cpu) == 0) ? PI_INT_MASK0_A : PI_INT_MASK0_B;
147 /* copied from Irix intpend0() */
148 pend0 = LOCAL_HUB_L(PI_INT_PEND0);
149 mask0 = LOCAL_HUB_L(pi_int_mask0);
151 pend0 &= mask0; /* Pick intrs we should look at */
155 swlevel = ms1bit(pend0);
157 if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) {
158 LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ);
159 } else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) {
160 LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ);
161 } else if (pend0 & (1UL << CPU_CALL_A_IRQ)) {
162 LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
163 smp_call_function_interrupt();
164 } else if (pend0 & (1UL << CPU_CALL_B_IRQ)) {
165 LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ);
166 smp_call_function_interrupt();
170 /* "map" swlevel to irq */
171 struct slice_data *si = cpu_data[cpu].data;
173 irq = si->level_to_irq[swlevel];
177 LOCAL_HUB_L(PI_INT_PEND0);
180 void ip27_do_irq_mask1(struct pt_regs *regs)
183 hubreg_t pend1, mask1;
184 cpuid_t cpu = smp_processor_id();
185 int pi_int_mask1 = (cputoslice(cpu) == 0) ? PI_INT_MASK1_A : PI_INT_MASK1_B;
186 struct slice_data *si = cpu_data[cpu].data;
188 /* copied from Irix intpend0() */
189 pend1 = LOCAL_HUB_L(PI_INT_PEND1);
190 mask1 = LOCAL_HUB_L(pi_int_mask1);
192 pend1 &= mask1; /* Pick intrs we should look at */
196 swlevel = ms1bit(pend1);
197 /* "map" swlevel to irq */
198 irq = si->level_to_irq[swlevel];
199 LOCAL_HUB_CLR_INTR(swlevel);
202 LOCAL_HUB_L(PI_INT_PEND1);
205 void ip27_prof_timer(struct pt_regs *regs)
207 panic("CPU %d got a profiling interrupt", smp_processor_id());
210 void ip27_hub_error(struct pt_regs *regs)
212 panic("CPU %d got a hub error interrupt", smp_processor_id());
215 static int intr_connect_level(int cpu, int bit)
217 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
218 struct slice_data *si = cpu_data[cpu].data;
221 set_bit(bit, si->irq_enable_mask);
223 local_irq_save(flags);
224 if (!cputoslice(cpu)) {
225 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
226 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
228 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
229 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
231 local_irq_restore(flags);
236 static int intr_disconnect_level(int cpu, int bit)
238 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
239 struct slice_data *si = cpu_data[cpu].data;
241 clear_bit(bit, si->irq_enable_mask);
243 if (!cputoslice(cpu)) {
244 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
245 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
247 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
248 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
254 /* Startup one of the (PCI ...) IRQs routes over a bridge. */
255 static unsigned int startup_bridge_irq(unsigned int irq)
257 struct bridge_controller *bc;
263 pin = SLOT_FROM_PCI_IRQ(irq);
264 bc = IRQ_TO_BRIDGE(irq);
267 DBG("bridge_startup(): irq= 0x%x pin=%d\n", irq, pin);
269 * "map" irq to a swlevel greater than 6 since the first 6 bits
270 * of INT_PEND0 are taken
272 swlevel = find_level(&cpu, irq);
273 bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));
274 bridge->b_int_enable |= (1 << pin);
275 bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */
278 * Enable sending of an interrupt clear packt to the hub on a high to
279 * low transition of the interrupt pin.
281 * IRIX sets additional bits in the address which are documented as
282 * reserved in the bridge docs.
284 bridge->b_int_mode |= (1UL << pin);
287 * We assume the bridge to have a 1:1 mapping between devices
288 * (slots) and intr pins.
290 device = bridge->b_int_device;
291 device &= ~(7 << (pin*3));
292 device |= (pin << (pin*3));
293 bridge->b_int_device = device;
295 bridge->b_wid_tflush;
297 return 0; /* Never anything pending. */
300 /* Shutdown one of the (PCI ...) IRQs routes over a bridge. */
301 static void shutdown_bridge_irq(unsigned int irq)
303 struct bridge_controller *bc = IRQ_TO_BRIDGE(irq);
304 struct hub_data *hub = hub_data(cpu_to_node(bc->irq_cpu));
305 bridge_t *bridge = bc->base;
306 struct slice_data *si = cpu_data[bc->irq_cpu].data;
310 DBG("bridge_shutdown: irq 0x%x\n", irq);
311 pin = SLOT_FROM_PCI_IRQ(irq);
314 * map irq to a swlevel greater than 6 since the first 6 bits
315 * of INT_PEND0 are taken
317 swlevel = find_level(&cpu, irq);
318 intr_disconnect_level(cpu, swlevel);
320 __clear_bit(swlevel, hub->irq_alloc_mask);
321 si->level_to_irq[swlevel] = -1;
323 bridge->b_int_enable &= ~(1 << pin);
324 bridge->b_wid_tflush;
327 static inline void enable_bridge_irq(unsigned int irq)
332 swlevel = find_level(&cpu, irq); /* Criminal offence */
333 intr_connect_level(cpu, swlevel);
336 static inline void disable_bridge_irq(unsigned int irq)
341 swlevel = find_level(&cpu, irq); /* Criminal offence */
342 intr_disconnect_level(cpu, swlevel);
345 static void mask_and_ack_bridge_irq(unsigned int irq)
347 disable_bridge_irq(irq);
350 static void end_bridge_irq(unsigned int irq)
352 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
353 irq_desc[irq].action)
354 enable_bridge_irq(irq);
357 static struct hw_interrupt_type bridge_irq_type = {
358 .typename = "bridge",
359 .startup = startup_bridge_irq,
360 .shutdown = shutdown_bridge_irq,
361 .enable = enable_bridge_irq,
362 .disable = disable_bridge_irq,
363 .ack = mask_and_ack_bridge_irq,
364 .end = end_bridge_irq,
367 static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
369 static int allocate_irqno(void)
374 irq = find_first_zero_bit(irq_map, NR_IRQS);
379 if (test_and_set_bit(irq, irq_map))
385 void free_irqno(unsigned int irq)
387 clear_bit(irq, irq_map);
390 void __devinit register_bridge_irq(unsigned int irq)
392 irq_desc[irq].status = IRQ_DISABLED;
393 irq_desc[irq].action = 0;
394 irq_desc[irq].depth = 1;
395 irq_desc[irq].handler = &bridge_irq_type;
398 int __devinit request_bridge_irq(struct bridge_controller *bc)
400 int irq = allocate_irqno();
408 * "map" irq to a swlevel greater than 6 since the first 6 bits
409 * of INT_PEND0 are taken
412 swlevel = alloc_level(cpu, irq);
413 if (unlikely(swlevel < 0)) {
419 /* Make sure it's not already pending when we connect it. */
420 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
421 REMOTE_HUB_CLR_INTR(nasid, swlevel);
423 intr_connect_level(cpu, swlevel);
425 register_bridge_irq(irq);
430 void __init arch_init_irq(void)
432 set_except_vector(0, ip27_irq);
435 void install_ipi(void)
437 int slice = LOCAL_HUB_L(PI_CPU_NUM);
438 int cpu = smp_processor_id();
439 struct slice_data *si = cpu_data[cpu].data;
440 struct hub_data *hub = hub_data(cpu_to_node(cpu));
443 resched = CPU_RESCHED_A_IRQ + slice;
444 __set_bit(resched, hub->irq_alloc_mask);
445 __set_bit(resched, si->irq_enable_mask);
446 LOCAL_HUB_CLR_INTR(resched);
448 call = CPU_CALL_A_IRQ + slice;
449 __set_bit(call, hub->irq_alloc_mask);
450 __set_bit(call, si->irq_enable_mask);
451 LOCAL_HUB_CLR_INTR(call);
454 LOCAL_HUB_S(PI_INT_MASK0_A, si->irq_enable_mask[0]);
455 LOCAL_HUB_S(PI_INT_MASK1_A, si->irq_enable_mask[1]);
457 LOCAL_HUB_S(PI_INT_MASK0_B, si->irq_enable_mask[0]);
458 LOCAL_HUB_S(PI_INT_MASK1_B, si->irq_enable_mask[1]);