2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
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12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
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22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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35 #include <linux/init.h>
36 #include <linux/kernel.h>
37 #include <linux/threads.h>
40 #include <asm/asm-offsets.h>
41 #include <asm/mipsregs.h>
42 #include <asm/addrspace.h>
43 #include <asm/string.h>
45 #include <asm/netlogic/haldefs.h>
46 #include <asm/netlogic/common.h>
47 #include <asm/netlogic/mips-extns.h>
49 #include <asm/netlogic/xlp-hal/iomap.h>
50 #include <asm/netlogic/xlp-hal/xlp.h>
51 #include <asm/netlogic/xlp-hal/pic.h>
52 #include <asm/netlogic/xlp-hal/sys.h>
54 static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
56 uint32_t coremask, value;
59 coremask = (1 << core);
61 /* Enable CPU clock in case of 8xx/3xx */
62 if (!cpu_is_xlpii()) {
63 value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
65 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
68 /* On 9XX, mark coherent first */
69 if (cpu_is_xlp9xx()) {
70 value = nlm_read_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE);
72 nlm_write_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE, value);
75 /* Remove CPU Reset */
76 resetreg = cpu_is_xlp9xx() ? SYS_9XX_CPU_RESET : SYS_CPU_RESET;
77 value = nlm_read_sys_reg(sysbase, resetreg);
79 nlm_write_sys_reg(sysbase, resetreg, value);
81 /* We are done on 9XX */
85 /* Poll for CPU to mark itself coherent on other type of XLP */
88 value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
89 } while ((value & coremask) != 0 && --count > 0);
94 static int wait_for_cpus(int cpu, int bootcpu)
96 volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
97 int i, count, notready;
101 notready = nlm_threads_per_core;
102 for (i = 0; i < nlm_threads_per_core; i++)
103 if (cpu_ready[cpu + i] || cpu == bootcpu)
105 } while (notready != 0 && --count > 0);
110 static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
112 struct nlm_soc_info *nodep;
113 uint64_t syspcibase, fusebase;
114 uint32_t syscoremask, mask, fusemask;
117 for (n = 0; n < NLM_NR_NODES; n++) {
119 /* check if node exists and is online */
120 if (cpu_is_xlp9xx()) {
121 int b = xlp9xx_get_socbus(n);
122 pr_info("Node %d SoC PCI bus %d.\n", n, b);
126 syspcibase = nlm_get_sys_pcibase(n);
127 if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
133 /* read cores in reset from SYS */
134 nodep = nlm_get_node(n);
136 if (cpu_is_xlp9xx()) {
137 fusebase = nlm_get_fuse_regbase(n);
138 fusemask = nlm_read_reg(fusebase, FUSE_9XX_DEVCFG6);
141 fusemask = nlm_read_sys_reg(nodep->sysbase,
142 SYS_EFUSE_DEVICE_CFG_STATUS0);
143 switch (read_c0_prid() & 0xff00) {
144 case PRID_IMP_NETLOGIC_XLP3XX:
147 case PRID_IMP_NETLOGIC_XLP2XX:
150 case PRID_IMP_NETLOGIC_XLP8XX:
158 * Fused out cores are set in the fusemask, and the remaining
159 * cores are renumbered to range 0 .. nactive-1
161 syscoremask = (1 << hweight32(~fusemask & mask)) - 1;
167 pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask);
168 for (core = 0; core < nlm_cores_per_node(); core++) {
169 /* we will be on node 0 core 0 */
170 if (n == 0 && core == 0)
173 /* see if the core exists */
174 if ((syscoremask & (1 << core)) == 0)
177 /* see if at least the first hw thread is enabled */
178 cpu = (n * nlm_cores_per_node() + core)
179 * NLM_THREADS_PER_CORE;
180 if (!cpumask_test_cpu(cpu, wakeup_mask))
183 /* wake up the core */
184 if (!xlp_wakeup_core(nodep->sysbase, n, core))
188 nodep->coremask |= 1u << core;
190 /* spin until the hw threads sets their ready */
191 if (!wait_for_cpus(cpu, 0))
192 pr_err("Node %d : timeout core %d\n", n, core);
197 void xlp_wakeup_secondary_cpus()
200 * In case of u-boot, the secondaries are in reset
201 * first wakeup core 0 threads
203 xlp_boot_core0_siblings();
204 if (!wait_for_cpus(0, 0))
205 pr_err("Node 0 : timeout core 0\n");
207 /* now get other cores out of reset */
208 xlp_enable_secondary_cores(&nlm_cpumask);