2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
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35 #include <linux/kernel.h>
36 #include <linux/init.h>
37 #include <linux/linkage.h>
38 #include <linux/interrupt.h>
39 #include <linux/spinlock.h>
41 #include <linux/slab.h>
42 #include <linux/irq.h>
44 #include <asm/errno.h>
45 #include <asm/signal.h>
46 #include <asm/ptrace.h>
47 #include <asm/mipsregs.h>
48 #include <asm/thread_info.h>
50 #include <asm/netlogic/mips-extns.h>
51 #include <asm/netlogic/interrupt.h>
52 #include <asm/netlogic/haldefs.h>
53 #include <asm/netlogic/common.h>
55 #if defined(CONFIG_CPU_XLP)
56 #include <asm/netlogic/xlp-hal/iomap.h>
57 #include <asm/netlogic/xlp-hal/xlp.h>
58 #include <asm/netlogic/xlp-hal/pic.h>
59 #elif defined(CONFIG_CPU_XLR)
60 #include <asm/netlogic/xlr/iomap.h>
61 #include <asm/netlogic/xlr/pic.h>
66 * These are the routines that handle all the low level interrupt stuff.
67 * Actions handled here are: initialization of the interrupt map, requesting of
68 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
73 static uint64_t nlm_irq_mask;
74 static DEFINE_SPINLOCK(nlm_pic_lock);
76 static void xlp_pic_enable(struct irq_data *d)
81 irt = nlm_irq_to_irt(d->irq);
84 spin_lock_irqsave(&nlm_pic_lock, flags);
85 nlm_pic_enable_irt(nlm_pic_base, irt);
86 spin_unlock_irqrestore(&nlm_pic_lock, flags);
89 static void xlp_pic_disable(struct irq_data *d)
94 irt = nlm_irq_to_irt(d->irq);
97 spin_lock_irqsave(&nlm_pic_lock, flags);
98 nlm_pic_disable_irt(nlm_pic_base, irt);
99 spin_unlock_irqrestore(&nlm_pic_lock, flags);
102 static void xlp_pic_mask_ack(struct irq_data *d)
104 uint64_t mask = 1ull << d->irq;
106 write_c0_eirr(mask); /* ack by writing EIRR */
109 static void xlp_pic_unmask(struct irq_data *d)
111 void *hd = irq_data_get_irq_handler_data(d);
114 irt = nlm_irq_to_irt(d->irq);
119 void (*extra_ack)(void *) = hd;
122 /* Ack is a single write, no need to lock */
123 nlm_pic_ack(nlm_pic_base, irt);
126 static struct irq_chip xlp_pic = {
128 .irq_enable = xlp_pic_enable,
129 .irq_disable = xlp_pic_disable,
130 .irq_mask_ack = xlp_pic_mask_ack,
131 .irq_unmask = xlp_pic_unmask,
134 static void cpuintr_disable(struct irq_data *d)
137 uint64_t mask = 1ull << d->irq;
139 eimr = read_c0_eimr();
140 write_c0_eimr(eimr & ~mask);
143 static void cpuintr_enable(struct irq_data *d)
146 uint64_t mask = 1ull << d->irq;
148 eimr = read_c0_eimr();
149 write_c0_eimr(eimr | mask);
152 static void cpuintr_ack(struct irq_data *d)
154 uint64_t mask = 1ull << d->irq;
159 static void cpuintr_nop(struct irq_data *d)
161 WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
165 * Chip definition for CPU originated interrupts(timer, msg) and
168 struct irq_chip nlm_cpu_intr = {
169 .name = "XLP-CPU-INTR",
170 .irq_enable = cpuintr_enable,
171 .irq_disable = cpuintr_disable,
172 .irq_mask = cpuintr_nop,
173 .irq_ack = cpuintr_nop,
174 .irq_eoi = cpuintr_ack,
177 void __init init_nlm_common_irqs(void)
181 for (i = 0; i < PIC_IRT_FIRST_IRQ; i++)
182 irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq);
184 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ ; i++)
185 irq_set_chip_and_handler(i, &xlp_pic, handle_level_irq);
188 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
189 nlm_smp_function_ipi_handler);
190 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
191 nlm_smp_resched_ipi_handler);
193 ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
196 for (irq = PIC_IRT_FIRST_IRQ; irq <= PIC_IRT_LAST_IRQ; irq++) {
197 irt = nlm_irq_to_irt(irq);
200 nlm_irq_mask |= (1ULL << irq);
201 nlm_pic_init_irt(nlm_pic_base, irt, irq, 0);
204 nlm_irq_mask |= (1ULL << IRQ_TIMER);
207 void __init arch_init_irq(void)
209 /* Initialize the irq descriptors */
210 init_nlm_common_irqs();
212 write_c0_eimr(nlm_irq_mask);
215 void __cpuinit nlm_smp_irq_init(void)
217 /* set interrupt mask for non-zero cpus */
218 write_c0_eimr(nlm_irq_mask);
221 asmlinkage void plat_irq_dispatch(void)
226 eirr = read_c0_eirr() & read_c0_eimr();
227 if (eirr & (1 << IRQ_TIMER)) {
232 i = __ilog2_u64(eirr);