2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 * Setting up the clock on the MIPS boards.
21 #include <linux/types.h>
22 #include <linux/i8253.h>
23 #include <linux/init.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sched.h>
26 #include <linux/spinlock.h>
27 #include <linux/interrupt.h>
28 #include <linux/time.h>
29 #include <linux/timex.h>
30 #include <linux/mc146818rtc.h>
32 #include <asm/mipsregs.h>
33 #include <asm/mipsmtregs.h>
34 #include <asm/hardirq.h>
36 #include <asm/div64.h>
38 #include <asm/setup.h>
40 #include <asm/mc146818-time.h>
41 #include <asm/msc01_ic.h>
43 #include <asm/mips-boards/generic.h>
44 #include <asm/mips-boards/prom.h>
46 #include <asm/mips-boards/maltaint.h>
48 unsigned long cpu_khz;
50 static int mips_cpu_timer_irq;
51 static int mips_cpu_perf_irq;
52 extern int cp0_perfcount_irq;
54 static void mips_timer_dispatch(void)
56 do_IRQ(mips_cpu_timer_irq);
59 static void mips_perf_dispatch(void)
61 do_IRQ(mips_cpu_perf_irq);
65 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
67 static unsigned int __init estimate_cpu_frequency(void)
69 unsigned int prid = read_c0_prid() & 0xffff00;
75 local_irq_save(flags);
77 /* Start counter exactly on falling edge of update flag */
78 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
79 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
81 /* Start r4k counter. */
82 start = read_c0_count();
84 /* Read counter exactly on falling edge of update flag */
85 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
86 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
88 count = read_c0_count() - start;
90 /* restore interrupts */
91 local_irq_restore(flags);
93 mips_hpt_frequency = count;
94 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
95 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
98 count += 5000; /* round */
104 void read_persistent_clock(struct timespec *ts)
106 ts->tv_sec = mc146818_get_cmos_time();
110 static void __init plat_perf_setup(void)
112 #ifdef MSC01E_INT_BASE
114 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
115 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
118 if (cp0_perfcount_irq >= 0) {
120 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
121 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
123 irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
128 unsigned int __cpuinit get_c0_compare_int(void)
130 #ifdef MSC01E_INT_BASE
132 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
133 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
138 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
139 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
142 return mips_cpu_timer_irq;
145 void __init plat_time_init(void)
147 unsigned int est_freq;
149 /* Set Data mode - binary. */
150 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
152 est_freq = estimate_cpu_frequency();
154 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
155 (est_freq%1000000)*100/1000000);
157 cpu_khz = est_freq / 1000;
159 mips_scroll_message();
160 #ifdef CONFIG_I8253 /* Only Malta has a PIT */