2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Synthesize TLB refill handlers at runtime.
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
14 * ... and the days got worse and worse and now you see
15 * I've gone completly out of my mind.
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
21 * (Condolences to Napoleon XIV)
24 #include <linux/bug.h>
25 #include <linux/kernel.h>
26 #include <linux/types.h>
27 #include <linux/smp.h>
28 #include <linux/string.h>
29 #include <linux/cache.h>
31 #include <asm/cacheflush.h>
32 #include <asm/cpu-type.h>
33 #include <asm/pgtable.h>
36 #include <asm/setup.h>
39 * TLB load/store/modify handlers.
41 * Only the fastpath gets synthesized at runtime, the slowpath for
42 * do_page_fault remains normal asm.
44 extern void tlb_do_page_fault_0(void);
45 extern void tlb_do_page_fault_1(void);
47 struct work_registers {
56 } ____cacheline_aligned_in_smp;
58 static struct tlb_reg_save handler_reg_save[NR_CPUS];
60 static inline int r45k_bvahwbug(void)
62 /* XXX: We should probe for the presence of this bug, but we don't. */
66 static inline int r4k_250MHZhwbug(void)
68 /* XXX: We should probe for the presence of this bug, but we don't. */
72 static inline int __maybe_unused bcm1250_m3_war(void)
74 return BCM1250_M3_WAR;
77 static inline int __maybe_unused r10000_llsc_war(void)
79 return R10000_LLSC_WAR;
82 static int use_bbit_insns(void)
84 switch (current_cpu_type()) {
85 case CPU_CAVIUM_OCTEON:
86 case CPU_CAVIUM_OCTEON_PLUS:
87 case CPU_CAVIUM_OCTEON2:
88 case CPU_CAVIUM_OCTEON3:
95 static int use_lwx_insns(void)
97 switch (current_cpu_type()) {
98 case CPU_CAVIUM_OCTEON2:
99 case CPU_CAVIUM_OCTEON3:
105 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
106 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
107 static bool scratchpad_available(void)
111 static int scratchpad_offset(int i)
114 * CVMSEG starts at address -32768 and extends for
115 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
117 i += 1; /* Kernel use starts at the top and works down. */
118 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
121 static bool scratchpad_available(void)
125 static int scratchpad_offset(int i)
128 /* Really unreachable, but evidently some GCC want this. */
133 * Found by experiment: At least some revisions of the 4kc throw under
134 * some circumstances a machine check exception, triggered by invalid
135 * values in the index register. Delaying the tlbp instruction until
136 * after the next branch, plus adding an additional nop in front of
137 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
138 * why; it's not an issue caused by the core RTL.
141 static int m4kc_tlbp_war(void)
143 return (current_cpu_data.processor_id & 0xffff00) ==
144 (PRID_COMP_MIPS | PRID_IMP_4KC);
147 /* Handle labels (which must be positive integers). */
149 label_second_part = 1,
154 label_split = label_tlbw_hazard_0 + 8,
155 label_tlbl_goaround1,
156 label_tlbl_goaround2,
160 label_smp_pgtable_change,
161 label_r3000_write_probe_fail,
162 label_large_segbits_fault,
163 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
164 label_tlb_huge_update,
168 UASM_L_LA(_second_part)
171 UASM_L_LA(_vmalloc_done)
172 /* _tlbw_hazard_x is handled differently. */
174 UASM_L_LA(_tlbl_goaround1)
175 UASM_L_LA(_tlbl_goaround2)
176 UASM_L_LA(_nopage_tlbl)
177 UASM_L_LA(_nopage_tlbs)
178 UASM_L_LA(_nopage_tlbm)
179 UASM_L_LA(_smp_pgtable_change)
180 UASM_L_LA(_r3000_write_probe_fail)
181 UASM_L_LA(_large_segbits_fault)
182 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
183 UASM_L_LA(_tlb_huge_update)
186 static int hazard_instance;
188 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
192 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
199 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
203 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
211 * pgtable bits are assigned dynamically depending on processor feature
212 * and statically based on kernel configuration. This spits out the actual
213 * values the kernel is using. Required to make sense from disassembled
214 * TLB exception handlers.
216 static void output_pgtable_bits_defines(void)
218 #define pr_define(fmt, ...) \
219 pr_debug("#define " fmt, ##__VA_ARGS__)
221 pr_debug("#include <asm/asm.h>\n");
222 pr_debug("#include <asm/regdef.h>\n");
225 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
226 pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT);
227 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
228 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
229 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
230 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
231 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
232 pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT);
235 #ifdef _PAGE_NO_EXEC_SHIFT
236 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
238 #ifdef _PAGE_NO_READ_SHIFT
239 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
242 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
243 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
244 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
245 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
249 static inline void dump_handler(const char *symbol, const u32 *handler, int count)
253 pr_debug("LEAF(%s)\n", symbol);
255 pr_debug("\t.set push\n");
256 pr_debug("\t.set noreorder\n");
258 for (i = 0; i < count; i++)
259 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
261 pr_debug("\t.set\tpop\n");
263 pr_debug("\tEND(%s)\n", symbol);
266 /* The only general purpose registers allowed in TLB handlers. */
270 /* Some CP0 registers */
271 #define C0_INDEX 0, 0
272 #define C0_ENTRYLO0 2, 0
273 #define C0_TCBIND 2, 2
274 #define C0_ENTRYLO1 3, 0
275 #define C0_CONTEXT 4, 0
276 #define C0_PAGEMASK 5, 0
277 #define C0_BADVADDR 8, 0
278 #define C0_ENTRYHI 10, 0
280 #define C0_XCONTEXT 20, 0
283 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
285 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
288 /* The worst case length of the handler is around 18 instructions for
289 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
290 * Maximum space available is 32 instructions for R3000 and 64
291 * instructions for R4000.
293 * We deliberately chose a buffer size of 128, so we won't scribble
294 * over anything important on overflow before we panic.
296 static u32 tlb_handler[128];
298 /* simply assume worst case size for labels and relocs */
299 static struct uasm_label labels[128];
300 static struct uasm_reloc relocs[128];
302 static int check_for_high_segbits;
304 static unsigned int kscratch_used_mask;
306 static inline int __maybe_unused c0_kscratch(void)
308 switch (current_cpu_type()) {
317 static int allocate_kscratch(void)
320 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
327 r--; /* make it zero based */
329 kscratch_used_mask |= (1 << r);
334 static int scratch_reg;
336 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
338 static struct work_registers build_get_work_registers(u32 **p)
340 struct work_registers r;
342 if (scratch_reg >= 0) {
343 /* Save in CPU local C0_KScratch? */
344 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
351 if (num_possible_cpus() > 1) {
352 /* Get smp_processor_id */
353 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
354 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
356 /* handler_reg_save index in K0 */
357 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
359 UASM_i_LA(p, K1, (long)&handler_reg_save);
360 UASM_i_ADDU(p, K0, K0, K1);
362 UASM_i_LA(p, K0, (long)&handler_reg_save);
364 /* K0 now points to save area, save $1 and $2 */
365 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
366 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
374 static void build_restore_work_registers(u32 **p)
376 if (scratch_reg >= 0) {
377 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
380 /* K0 already points to save area, restore $1 and $2 */
381 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
382 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
385 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
388 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
389 * we cannot do r3000 under these circumstances.
391 * Declare pgd_current here instead of including mmu_context.h to avoid type
392 * conflicts for tlbmiss_handler_setup_pgd
394 extern unsigned long pgd_current[];
397 * The R3000 TLB handler is simple.
399 static void build_r3000_tlb_refill_handler(void)
401 long pgdc = (long)pgd_current;
404 memset(tlb_handler, 0, sizeof(tlb_handler));
407 uasm_i_mfc0(&p, K0, C0_BADVADDR);
408 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
409 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
410 uasm_i_srl(&p, K0, K0, 22); /* load delay */
411 uasm_i_sll(&p, K0, K0, 2);
412 uasm_i_addu(&p, K1, K1, K0);
413 uasm_i_mfc0(&p, K0, C0_CONTEXT);
414 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
415 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
416 uasm_i_addu(&p, K1, K1, K0);
417 uasm_i_lw(&p, K0, 0, K1);
418 uasm_i_nop(&p); /* load delay */
419 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
420 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
421 uasm_i_tlbwr(&p); /* cp0 delay */
423 uasm_i_rfe(&p); /* branch delay */
425 if (p > tlb_handler + 32)
426 panic("TLB refill handler space exceeded");
428 pr_debug("Wrote TLB refill handler (%u instructions).\n",
429 (unsigned int)(p - tlb_handler));
431 memcpy((void *)ebase, tlb_handler, 0x80);
432 local_flush_icache_range(ebase, ebase + 0x80);
434 dump_handler("r3000_tlb_refill", (u32 *)ebase, 32);
436 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
439 * The R4000 TLB handler is much more complicated. We have two
440 * consecutive handler areas with 32 instructions space each.
441 * Since they aren't used at the same time, we can overflow in the
442 * other one.To keep things simple, we first assume linear space,
443 * then we relocate it to the final handler layout as needed.
445 static u32 final_handler[64];
450 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
451 * 2. A timing hazard exists for the TLBP instruction.
453 * stalling_instruction
456 * The JTLB is being read for the TLBP throughout the stall generated by the
457 * previous instruction. This is not really correct as the stalling instruction
458 * can modify the address used to access the JTLB. The failure symptom is that
459 * the TLBP instruction will use an address created for the stalling instruction
460 * and not the address held in C0_ENHI and thus report the wrong results.
462 * The software work-around is to not allow the instruction preceding the TLBP
463 * to stall - make it an NOP or some other instruction guaranteed not to stall.
465 * Errata 2 will not be fixed. This errata is also on the R5000.
467 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
469 static void __maybe_unused build_tlb_probe_entry(u32 **p)
471 switch (current_cpu_type()) {
472 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
488 * Write random or indexed TLB entry, and care about the hazards from
489 * the preceding mtc0 and for the following eret.
491 enum tlb_write_entry { tlb_random, tlb_indexed };
493 static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
494 struct uasm_reloc **r,
495 enum tlb_write_entry wmode)
497 void(*tlbw)(u32 **) = NULL;
500 case tlb_random: tlbw = uasm_i_tlbwr; break;
501 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
504 if (cpu_has_mips_r2) {
506 * The architecture spec says an ehb is required here,
507 * but a number of cores do not have the hazard and
508 * using an ehb causes an expensive pipeline stall.
510 switch (current_cpu_type()) {
527 switch (current_cpu_type()) {
535 * This branch uses up a mtc0 hazard nop slot and saves
536 * two nops after the tlbw instruction.
538 uasm_bgezl_hazard(p, r, hazard_instance);
540 uasm_bgezl_label(l, p, hazard_instance);
554 uasm_i_nop(p); /* QED specifies 2 nops hazard */
555 uasm_i_nop(p); /* QED specifies 2 nops hazard */
628 panic("No TLB refill handler yet (CPU type: %d)",
634 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
638 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
640 #ifdef CONFIG_PHYS_ADDR_T_64BIT
641 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
643 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
648 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
650 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
651 unsigned int tmp, enum label_id lid,
654 if (restore_scratch) {
655 /* Reset default page size */
656 if (PM_DEFAULT_MASK >> 16) {
657 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
658 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
659 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
660 uasm_il_b(p, r, lid);
661 } else if (PM_DEFAULT_MASK) {
662 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
663 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
664 uasm_il_b(p, r, lid);
666 uasm_i_mtc0(p, 0, C0_PAGEMASK);
667 uasm_il_b(p, r, lid);
669 if (scratch_reg >= 0)
670 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
672 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
674 /* Reset default page size */
675 if (PM_DEFAULT_MASK >> 16) {
676 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
677 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
678 uasm_il_b(p, r, lid);
679 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
680 } else if (PM_DEFAULT_MASK) {
681 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
682 uasm_il_b(p, r, lid);
683 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
685 uasm_il_b(p, r, lid);
686 uasm_i_mtc0(p, 0, C0_PAGEMASK);
691 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l,
692 struct uasm_reloc **r,
694 enum tlb_write_entry wmode,
697 /* Set huge page tlb entry size */
698 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
699 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
700 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
702 build_tlb_write_entry(p, l, r, wmode);
704 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
708 * Check if Huge PTE is present, if so then jump to LABEL.
711 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
712 unsigned int pmd, int lid)
714 UASM_i_LW(p, tmp, 0, pmd);
715 if (use_bbit_insns()) {
716 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
718 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
719 uasm_il_bnez(p, r, tmp, lid);
723 static void build_huge_update_entries(u32 **p, unsigned int pte,
729 * A huge PTE describes an area the size of the
730 * configured huge page size. This is twice the
731 * of the large TLB entry size we intend to use.
732 * A TLB entry half the size of the configured
733 * huge page size is configured into entrylo0
734 * and entrylo1 to cover the contiguous huge PTE
737 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
739 /* We can clobber tmp. It isn't used after this.*/
741 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
743 build_convert_pte_to_entrylo(p, pte);
744 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
745 /* convert to entrylo1 */
747 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
749 UASM_i_ADDU(p, pte, pte, tmp);
751 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
754 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
755 struct uasm_label **l,
760 UASM_i_SC(p, pte, 0, ptr);
761 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
762 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
764 UASM_i_SW(p, pte, 0, ptr);
766 build_huge_update_entries(p, pte, ptr);
767 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
769 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
773 * TMP and PTR are scratch.
774 * TMP will be clobbered, PTR will hold the pmd entry.
777 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
778 unsigned int tmp, unsigned int ptr)
780 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
781 long pgdc = (long)pgd_current;
784 * The vmalloc handling is not in the hotpath.
786 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
788 if (check_for_high_segbits) {
790 * The kernel currently implicitely assumes that the
791 * MIPS SEGBITS parameter for the processor is
792 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
793 * allocate virtual addresses outside the maximum
794 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
795 * that doesn't prevent user code from accessing the
796 * higher xuseg addresses. Here, we make sure that
797 * everything but the lower xuseg addresses goes down
798 * the module_alloc/vmalloc path.
800 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
801 uasm_il_bnez(p, r, ptr, label_vmalloc);
803 uasm_il_bltz(p, r, tmp, label_vmalloc);
805 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
808 /* pgd is in pgd_reg */
809 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
811 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
813 * &pgd << 11 stored in CONTEXT [23..63].
815 UASM_i_MFC0(p, ptr, C0_CONTEXT);
817 /* Clear lower 23 bits of context. */
818 uasm_i_dins(p, ptr, 0, 0, 23);
820 /* 1 0 1 0 1 << 6 xkphys cached */
821 uasm_i_ori(p, ptr, ptr, 0x540);
822 uasm_i_drotr(p, ptr, ptr, 11);
823 #elif defined(CONFIG_SMP)
824 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
825 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
826 UASM_i_LA_mostly(p, tmp, pgdc);
827 uasm_i_daddu(p, ptr, ptr, tmp);
828 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
829 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
831 UASM_i_LA_mostly(p, ptr, pgdc);
832 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
836 uasm_l_vmalloc_done(l, *p);
838 /* get pgd offset in bytes */
839 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
841 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
842 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
843 #ifndef __PAGETABLE_PMD_FOLDED
844 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
845 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
846 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
847 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
848 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
853 * BVADDR is the faulting address, PTR is scratch.
854 * PTR will hold the pgd for vmalloc.
857 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
858 unsigned int bvaddr, unsigned int ptr,
859 enum vmalloc64_mode mode)
861 long swpd = (long)swapper_pg_dir;
862 int single_insn_swpd;
863 int did_vmalloc_branch = 0;
865 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
867 uasm_l_vmalloc(l, *p);
869 if (mode != not_refill && check_for_high_segbits) {
870 if (single_insn_swpd) {
871 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
872 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
873 did_vmalloc_branch = 1;
876 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
879 if (!did_vmalloc_branch) {
880 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) {
881 uasm_il_b(p, r, label_vmalloc_done);
882 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
884 UASM_i_LA_mostly(p, ptr, swpd);
885 uasm_il_b(p, r, label_vmalloc_done);
886 if (uasm_in_compat_space_p(swpd))
887 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
889 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
892 if (mode != not_refill && check_for_high_segbits) {
893 uasm_l_large_segbits_fault(l, *p);
895 * We get here if we are an xsseg address, or if we are
896 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
898 * Ignoring xsseg (assume disabled so would generate
899 * (address errors?), the only remaining possibility
900 * is the upper xuseg addresses. On processors with
901 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
902 * addresses would have taken an address error. We try
903 * to mimic that here by taking a load/istream page
906 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
909 if (mode == refill_scratch) {
910 if (scratch_reg >= 0)
911 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
913 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
920 #else /* !CONFIG_64BIT */
923 * TMP and PTR are scratch.
924 * TMP will be clobbered, PTR will hold the pgd entry.
926 static void __maybe_unused
927 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
930 /* pgd is in pgd_reg */
931 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
932 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
934 long pgdc = (long)pgd_current;
936 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
938 uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
939 UASM_i_LA_mostly(p, tmp, pgdc);
940 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
941 uasm_i_addu(p, ptr, tmp, ptr);
943 UASM_i_LA_mostly(p, ptr, pgdc);
945 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
946 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
948 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
949 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
950 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
953 #endif /* !CONFIG_64BIT */
955 static void build_adjust_context(u32 **p, unsigned int ctx)
957 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
958 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
960 switch (current_cpu_type()) {
977 UASM_i_SRL(p, ctx, ctx, shift);
978 uasm_i_andi(p, ctx, ctx, mask);
981 static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
984 * Bug workaround for the Nevada. It seems as if under certain
985 * circumstances the move from cp0_context might produce a
986 * bogus result when the mfc0 instruction and its consumer are
987 * in a different cacheline or a load instruction, probably any
988 * memory reference, is between them.
990 switch (current_cpu_type()) {
992 UASM_i_LW(p, ptr, 0, ptr);
993 GET_CONTEXT(p, tmp); /* get context reg */
997 GET_CONTEXT(p, tmp); /* get context reg */
998 UASM_i_LW(p, ptr, 0, ptr);
1002 build_adjust_context(p, tmp);
1003 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1006 static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1009 * 64bit address support (36bit on a 32bit CPU) in a 32bit
1010 * Kernel is a special case. Only a few CPUs use it.
1012 #ifdef CONFIG_PHYS_ADDR_T_64BIT
1013 if (cpu_has_64bits) {
1014 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
1015 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1017 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1018 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1019 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL));
1021 uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
1022 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1023 uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
1025 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1027 int pte_off_even = sizeof(pte_t) / 2;
1028 int pte_off_odd = pte_off_even + sizeof(pte_t);
1030 /* The pte entries are pre-shifted */
1031 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
1032 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1033 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
1034 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1037 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
1038 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1039 if (r45k_bvahwbug())
1040 build_tlb_probe_entry(p);
1042 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1043 if (r4k_250MHZhwbug())
1044 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1045 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1046 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL));
1048 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
1049 if (r4k_250MHZhwbug())
1050 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1051 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1052 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
1053 if (r45k_bvahwbug())
1054 uasm_i_mfc0(p, tmp, C0_INDEX);
1056 if (r4k_250MHZhwbug())
1057 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1058 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1062 struct mips_huge_tlb_info {
1064 int restore_scratch;
1065 bool need_reload_pte;
1068 static struct mips_huge_tlb_info
1069 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1070 struct uasm_reloc **r, unsigned int tmp,
1071 unsigned int ptr, int c0_scratch_reg)
1073 struct mips_huge_tlb_info rv;
1074 unsigned int even, odd;
1075 int vmalloc_branch_delay_filled = 0;
1076 const int scratch = 1; /* Our extra working register */
1078 rv.huge_pte = scratch;
1079 rv.restore_scratch = 0;
1080 rv.need_reload_pte = false;
1082 if (check_for_high_segbits) {
1083 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1086 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1088 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1090 if (c0_scratch_reg >= 0)
1091 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1093 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1095 uasm_i_dsrl_safe(p, scratch, tmp,
1096 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1097 uasm_il_bnez(p, r, scratch, label_vmalloc);
1099 if (pgd_reg == -1) {
1100 vmalloc_branch_delay_filled = 1;
1101 /* Clear lower 23 bits of context. */
1102 uasm_i_dins(p, ptr, 0, 0, 23);
1106 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1108 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1110 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1112 if (c0_scratch_reg >= 0)
1113 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1115 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1118 /* Clear lower 23 bits of context. */
1119 uasm_i_dins(p, ptr, 0, 0, 23);
1121 uasm_il_bltz(p, r, tmp, label_vmalloc);
1124 if (pgd_reg == -1) {
1125 vmalloc_branch_delay_filled = 1;
1126 /* 1 0 1 0 1 << 6 xkphys cached */
1127 uasm_i_ori(p, ptr, ptr, 0x540);
1128 uasm_i_drotr(p, ptr, ptr, 11);
1131 #ifdef __PAGETABLE_PMD_FOLDED
1132 #define LOC_PTEP scratch
1134 #define LOC_PTEP ptr
1137 if (!vmalloc_branch_delay_filled)
1138 /* get pgd offset in bytes */
1139 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1141 uasm_l_vmalloc_done(l, *p);
1145 * fall-through case = badvaddr *pgd_current
1146 * vmalloc case = badvaddr swapper_pg_dir
1149 if (vmalloc_branch_delay_filled)
1150 /* get pgd offset in bytes */
1151 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1153 #ifdef __PAGETABLE_PMD_FOLDED
1154 GET_CONTEXT(p, tmp); /* get context reg */
1156 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
1158 if (use_lwx_insns()) {
1159 UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
1161 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
1162 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1165 #ifndef __PAGETABLE_PMD_FOLDED
1166 /* get pmd offset in bytes */
1167 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
1168 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
1169 GET_CONTEXT(p, tmp); /* get context reg */
1171 if (use_lwx_insns()) {
1172 UASM_i_LWX(p, scratch, scratch, ptr);
1174 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1175 UASM_i_LW(p, scratch, 0, ptr);
1178 /* Adjust the context during the load latency. */
1179 build_adjust_context(p, tmp);
1181 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1182 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
1184 * The in the LWX case we don't want to do the load in the
1185 * delay slot. It cannot issue in the same cycle and may be
1186 * speculative and unneeded.
1188 if (use_lwx_insns())
1190 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1193 /* build_update_entries */
1194 if (use_lwx_insns()) {
1197 UASM_i_LWX(p, even, scratch, tmp);
1198 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
1199 UASM_i_LWX(p, odd, scratch, tmp);
1201 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
1204 UASM_i_LW(p, even, 0, ptr); /* get even pte */
1205 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
1208 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL));
1209 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1210 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL));
1212 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
1213 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1214 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
1216 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1218 if (c0_scratch_reg >= 0) {
1219 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1220 build_tlb_write_entry(p, l, r, tlb_random);
1221 uasm_l_leave(l, *p);
1222 rv.restore_scratch = 1;
1223 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
1224 build_tlb_write_entry(p, l, r, tlb_random);
1225 uasm_l_leave(l, *p);
1226 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1228 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1229 build_tlb_write_entry(p, l, r, tlb_random);
1230 uasm_l_leave(l, *p);
1231 rv.restore_scratch = 1;
1234 uasm_i_eret(p); /* return from trap */
1240 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1241 * because EXL == 0. If we wrap, we can also use the 32 instruction
1242 * slots before the XTLB refill exception handler which belong to the
1243 * unused TLB refill exception.
1245 #define MIPS64_REFILL_INSNS 32
1247 static void build_r4000_tlb_refill_handler(void)
1249 u32 *p = tlb_handler;
1250 struct uasm_label *l = labels;
1251 struct uasm_reloc *r = relocs;
1253 unsigned int final_len;
1254 struct mips_huge_tlb_info htlb_info __maybe_unused;
1255 enum vmalloc64_mode vmalloc_mode __maybe_unused;
1257 memset(tlb_handler, 0, sizeof(tlb_handler));
1258 memset(labels, 0, sizeof(labels));
1259 memset(relocs, 0, sizeof(relocs));
1260 memset(final_handler, 0, sizeof(final_handler));
1262 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
1263 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1265 vmalloc_mode = refill_scratch;
1267 htlb_info.huge_pte = K0;
1268 htlb_info.restore_scratch = 0;
1269 htlb_info.need_reload_pte = true;
1270 vmalloc_mode = refill_noscratch;
1272 * create the plain linear handler
1274 if (bcm1250_m3_war()) {
1275 unsigned int segbits = 44;
1277 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1278 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1279 uasm_i_xor(&p, K0, K0, K1);
1280 uasm_i_dsrl_safe(&p, K1, K0, 62);
1281 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1282 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1283 uasm_i_or(&p, K0, K0, K1);
1284 uasm_il_bnez(&p, &r, K0, label_leave);
1285 /* No need for uasm_i_nop */
1289 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1291 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1294 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1295 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
1298 build_get_ptep(&p, K0, K1);
1299 build_update_entries(&p, K0, K1);
1300 build_tlb_write_entry(&p, &l, &r, tlb_random);
1301 uasm_l_leave(&l, p);
1302 uasm_i_eret(&p); /* return from trap */
1304 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1305 uasm_l_tlb_huge_update(&l, p);
1306 if (htlb_info.need_reload_pte)
1307 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
1308 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1309 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1310 htlb_info.restore_scratch);
1314 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
1318 * Overflow check: For the 64bit handler, we need at least one
1319 * free instruction slot for the wrap-around branch. In worst
1320 * case, if the intended insertion point is a delay slot, we
1321 * need three, with the second nop'ed and the third being
1324 switch (boot_cpu_type()) {
1326 if (sizeof(long) == 4) {
1328 /* Loongson2 ebase is different than r4k, we have more space */
1329 if ((p - tlb_handler) > 64)
1330 panic("TLB refill handler space exceeded");
1332 * Now fold the handler in the TLB refill handler space.
1335 /* Simplest case, just copy the handler. */
1336 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1337 final_len = p - tlb_handler;
1340 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1341 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1342 && uasm_insn_has_bdelay(relocs,
1343 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1344 panic("TLB refill handler space exceeded");
1346 * Now fold the handler in the TLB refill handler space.
1348 f = final_handler + MIPS64_REFILL_INSNS;
1349 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1350 /* Just copy the handler. */
1351 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1352 final_len = p - tlb_handler;
1354 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1355 const enum label_id ls = label_tlb_huge_update;
1357 const enum label_id ls = label_vmalloc;
1363 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1365 BUG_ON(i == ARRAY_SIZE(labels));
1366 split = labels[i].addr;
1369 * See if we have overflown one way or the other.
1371 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1372 split < p - MIPS64_REFILL_INSNS)
1377 * Split two instructions before the end. One
1378 * for the branch and one for the instruction
1379 * in the delay slot.
1381 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1384 * If the branch would fall in a delay slot,
1385 * we must back up an additional instruction
1386 * so that it is no longer in a delay slot.
1388 if (uasm_insn_has_bdelay(relocs, split - 1))
1391 /* Copy first part of the handler. */
1392 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1393 f += split - tlb_handler;
1396 /* Insert branch. */
1397 uasm_l_split(&l, final_handler);
1398 uasm_il_b(&f, &r, label_split);
1399 if (uasm_insn_has_bdelay(relocs, split))
1402 uasm_copy_handler(relocs, labels,
1403 split, split + 1, f);
1404 uasm_move_labels(labels, f, f + 1, -1);
1410 /* Copy the rest of the handler. */
1411 uasm_copy_handler(relocs, labels, split, p, final_handler);
1412 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1419 uasm_resolve_relocs(relocs, labels);
1420 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1423 memcpy((void *)ebase, final_handler, 0x100);
1424 local_flush_icache_range(ebase, ebase + 0x100);
1426 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64);
1429 extern u32 handle_tlbl[], handle_tlbl_end[];
1430 extern u32 handle_tlbs[], handle_tlbs_end[];
1431 extern u32 handle_tlbm[], handle_tlbm_end[];
1432 extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[];
1433 extern u32 tlbmiss_handler_setup_pgd_end[];
1435 static void build_setup_pgd(void)
1438 const int __maybe_unused a1 = 5;
1439 const int __maybe_unused a2 = 6;
1440 u32 *p = tlbmiss_handler_setup_pgd_start;
1441 const int tlbmiss_handler_setup_pgd_size =
1442 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start;
1443 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1444 long pgdc = (long)pgd_current;
1447 memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size *
1448 sizeof(tlbmiss_handler_setup_pgd[0]));
1449 memset(labels, 0, sizeof(labels));
1450 memset(relocs, 0, sizeof(relocs));
1451 pgd_reg = allocate_kscratch();
1452 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1453 if (pgd_reg == -1) {
1454 struct uasm_label *l = labels;
1455 struct uasm_reloc *r = relocs;
1457 /* PGD << 11 in c0_Context */
1459 * If it is a ckseg0 address, convert to a physical
1460 * address. Shifting right by 29 and adding 4 will
1461 * result in zero for these addresses.
1464 UASM_i_SRA(&p, a1, a0, 29);
1465 UASM_i_ADDIU(&p, a1, a1, 4);
1466 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
1468 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
1469 uasm_l_tlbl_goaround1(&l, p);
1470 UASM_i_SLL(&p, a0, a0, 11);
1472 UASM_i_MTC0(&p, a0, C0_CONTEXT);
1474 /* PGD in c0_KScratch */
1476 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1480 /* Save PGD to pgd_current[smp_processor_id()] */
1481 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG);
1482 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT);
1483 UASM_i_LA_mostly(&p, a2, pgdc);
1484 UASM_i_ADDU(&p, a2, a2, a1);
1485 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1487 UASM_i_LA_mostly(&p, a2, pgdc);
1488 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1492 /* if pgd_reg is allocated, save PGD also to scratch register */
1494 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1498 if (p >= tlbmiss_handler_setup_pgd_end)
1499 panic("tlbmiss_handler_setup_pgd space exceeded");
1501 uasm_resolve_relocs(relocs, labels);
1502 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1503 (unsigned int)(p - tlbmiss_handler_setup_pgd));
1505 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
1506 tlbmiss_handler_setup_pgd_size);
1510 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1513 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1515 uasm_i_lld(p, pte, 0, ptr);
1518 UASM_i_LL(p, pte, 0, ptr);
1520 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1522 uasm_i_ld(p, pte, 0, ptr);
1525 UASM_i_LW(p, pte, 0, ptr);
1530 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1533 #ifdef CONFIG_PHYS_ADDR_T_64BIT
1534 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1537 uasm_i_ori(p, pte, pte, mode);
1539 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1541 uasm_i_scd(p, pte, 0, ptr);
1544 UASM_i_SC(p, pte, 0, ptr);
1546 if (r10000_llsc_war())
1547 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1549 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1551 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1552 if (!cpu_has_64bits) {
1553 /* no uasm_i_nop needed */
1554 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1555 uasm_i_ori(p, pte, pte, hwmode);
1556 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1557 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1558 /* no uasm_i_nop needed */
1559 uasm_i_lw(p, pte, 0, ptr);
1566 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1568 uasm_i_sd(p, pte, 0, ptr);
1571 UASM_i_SW(p, pte, 0, ptr);
1573 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1574 if (!cpu_has_64bits) {
1575 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1576 uasm_i_ori(p, pte, pte, hwmode);
1577 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1578 uasm_i_lw(p, pte, 0, ptr);
1585 * Check if PTE is present, if not then jump to LABEL. PTR points to
1586 * the page table where this PTE is located, PTE will be re-loaded
1587 * with it's original value.
1590 build_pte_present(u32 **p, struct uasm_reloc **r,
1591 int pte, int ptr, int scratch, enum label_id lid)
1593 int t = scratch >= 0 ? scratch : pte;
1596 if (use_bbit_insns()) {
1597 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1600 uasm_i_andi(p, t, pte, _PAGE_PRESENT);
1601 uasm_il_beqz(p, r, t, lid);
1603 /* You lose the SMP race :-(*/
1604 iPTE_LW(p, pte, ptr);
1607 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_READ);
1608 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_READ);
1609 uasm_il_bnez(p, r, t, lid);
1611 /* You lose the SMP race :-(*/
1612 iPTE_LW(p, pte, ptr);
1616 /* Make PTE valid, store result in PTR. */
1618 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1621 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1623 iPTE_SW(p, r, pte, ptr, mode);
1627 * Check if PTE can be written to, if not branch to LABEL. Regardless
1628 * restore PTE with value from PTR when done.
1631 build_pte_writable(u32 **p, struct uasm_reloc **r,
1632 unsigned int pte, unsigned int ptr, int scratch,
1635 int t = scratch >= 0 ? scratch : pte;
1637 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_WRITE);
1638 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_WRITE);
1639 uasm_il_bnez(p, r, t, lid);
1641 /* You lose the SMP race :-(*/
1642 iPTE_LW(p, pte, ptr);
1647 /* Make PTE writable, update software status bits as well, then store
1651 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1654 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1657 iPTE_SW(p, r, pte, ptr, mode);
1661 * Check if PTE can be modified, if not branch to LABEL. Regardless
1662 * restore PTE with value from PTR when done.
1665 build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1666 unsigned int pte, unsigned int ptr, int scratch,
1669 if (use_bbit_insns()) {
1670 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
1673 int t = scratch >= 0 ? scratch : pte;
1674 uasm_i_andi(p, t, pte, _PAGE_WRITE);
1675 uasm_il_beqz(p, r, t, lid);
1677 /* You lose the SMP race :-(*/
1678 iPTE_LW(p, pte, ptr);
1682 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1686 * R3000 style TLB load/store/modify handlers.
1690 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1694 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1696 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1697 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1700 uasm_i_rfe(p); /* branch delay */
1704 * This places the pte into ENTRYLO0 and writes it with tlbwi
1705 * or tlbwr as appropriate. This is because the index register
1706 * may have the probe fail bit set as a result of a trap on a
1707 * kseg2 access, i.e. without refill. Then it returns.
1710 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1711 struct uasm_reloc **r, unsigned int pte,
1714 uasm_i_mfc0(p, tmp, C0_INDEX);
1715 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1716 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1717 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1718 uasm_i_tlbwi(p); /* cp0 delay */
1720 uasm_i_rfe(p); /* branch delay */
1721 uasm_l_r3000_write_probe_fail(l, *p);
1722 uasm_i_tlbwr(p); /* cp0 delay */
1724 uasm_i_rfe(p); /* branch delay */
1728 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1731 long pgdc = (long)pgd_current;
1733 uasm_i_mfc0(p, pte, C0_BADVADDR);
1734 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1735 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1736 uasm_i_srl(p, pte, pte, 22); /* load delay */
1737 uasm_i_sll(p, pte, pte, 2);
1738 uasm_i_addu(p, ptr, ptr, pte);
1739 uasm_i_mfc0(p, pte, C0_CONTEXT);
1740 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1741 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1742 uasm_i_addu(p, ptr, ptr, pte);
1743 uasm_i_lw(p, pte, 0, ptr);
1744 uasm_i_tlbp(p); /* load delay */
1747 static void build_r3000_tlb_load_handler(void)
1749 u32 *p = handle_tlbl;
1750 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
1751 struct uasm_label *l = labels;
1752 struct uasm_reloc *r = relocs;
1754 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1755 memset(labels, 0, sizeof(labels));
1756 memset(relocs, 0, sizeof(relocs));
1758 build_r3000_tlbchange_handler_head(&p, K0, K1);
1759 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
1760 uasm_i_nop(&p); /* load delay */
1761 build_make_valid(&p, &r, K0, K1);
1762 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1764 uasm_l_nopage_tlbl(&l, p);
1765 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1768 if (p >= handle_tlbl_end)
1769 panic("TLB load handler fastpath space exceeded");
1771 uasm_resolve_relocs(relocs, labels);
1772 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1773 (unsigned int)(p - handle_tlbl));
1775 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size);
1778 static void build_r3000_tlb_store_handler(void)
1780 u32 *p = handle_tlbs;
1781 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
1782 struct uasm_label *l = labels;
1783 struct uasm_reloc *r = relocs;
1785 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
1786 memset(labels, 0, sizeof(labels));
1787 memset(relocs, 0, sizeof(relocs));
1789 build_r3000_tlbchange_handler_head(&p, K0, K1);
1790 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
1791 uasm_i_nop(&p); /* load delay */
1792 build_make_write(&p, &r, K0, K1);
1793 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1795 uasm_l_nopage_tlbs(&l, p);
1796 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1799 if (p >= handle_tlbs_end)
1800 panic("TLB store handler fastpath space exceeded");
1802 uasm_resolve_relocs(relocs, labels);
1803 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1804 (unsigned int)(p - handle_tlbs));
1806 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size);
1809 static void build_r3000_tlb_modify_handler(void)
1811 u32 *p = handle_tlbm;
1812 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
1813 struct uasm_label *l = labels;
1814 struct uasm_reloc *r = relocs;
1816 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
1817 memset(labels, 0, sizeof(labels));
1818 memset(relocs, 0, sizeof(relocs));
1820 build_r3000_tlbchange_handler_head(&p, K0, K1);
1821 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
1822 uasm_i_nop(&p); /* load delay */
1823 build_make_write(&p, &r, K0, K1);
1824 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1826 uasm_l_nopage_tlbm(&l, p);
1827 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1830 if (p >= handle_tlbm_end)
1831 panic("TLB modify handler fastpath space exceeded");
1833 uasm_resolve_relocs(relocs, labels);
1834 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1835 (unsigned int)(p - handle_tlbm));
1837 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size);
1839 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1842 * R4000 style TLB load/store/modify handlers.
1844 static struct work_registers
1845 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1846 struct uasm_reloc **r)
1848 struct work_registers wr = build_get_work_registers(p);
1851 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
1853 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
1856 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1858 * For huge tlb entries, pmd doesn't contain an address but
1859 * instead contains the tlb pte. Check the PAGE_HUGE bit and
1860 * see if we need to jump to huge tlb processing.
1862 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
1865 UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
1866 UASM_i_LW(p, wr.r2, 0, wr.r2);
1867 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1868 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1869 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
1872 uasm_l_smp_pgtable_change(l, *p);
1874 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
1875 if (!m4kc_tlbp_war()) {
1876 build_tlb_probe_entry(p);
1878 /* race condition happens, leaving */
1880 uasm_i_mfc0(p, wr.r3, C0_INDEX);
1881 uasm_il_bltz(p, r, wr.r3, label_leave);
1889 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1890 struct uasm_reloc **r, unsigned int tmp,
1893 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
1894 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
1895 build_update_entries(p, tmp, ptr);
1896 build_tlb_write_entry(p, l, r, tlb_indexed);
1897 uasm_l_leave(l, *p);
1898 build_restore_work_registers(p);
1899 uasm_i_eret(p); /* return from trap */
1902 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
1906 static void build_r4000_tlb_load_handler(void)
1908 u32 *p = handle_tlbl;
1909 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
1910 struct uasm_label *l = labels;
1911 struct uasm_reloc *r = relocs;
1912 struct work_registers wr;
1914 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1915 memset(labels, 0, sizeof(labels));
1916 memset(relocs, 0, sizeof(relocs));
1918 if (bcm1250_m3_war()) {
1919 unsigned int segbits = 44;
1921 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1922 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1923 uasm_i_xor(&p, K0, K0, K1);
1924 uasm_i_dsrl_safe(&p, K1, K0, 62);
1925 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1926 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1927 uasm_i_or(&p, K0, K0, K1);
1928 uasm_il_bnez(&p, &r, K0, label_leave);
1929 /* No need for uasm_i_nop */
1932 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
1933 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
1934 if (m4kc_tlbp_war())
1935 build_tlb_probe_entry(&p);
1937 if (cpu_has_rixi && !cpu_has_rixiex) {
1939 * If the page is not _PAGE_VALID, RI or XI could not
1940 * have triggered it. Skip the expensive test..
1942 if (use_bbit_insns()) {
1943 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
1944 label_tlbl_goaround1);
1946 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
1947 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
1953 switch (current_cpu_type()) {
1955 if (cpu_has_mips_r2) {
1958 case CPU_CAVIUM_OCTEON:
1959 case CPU_CAVIUM_OCTEON_PLUS:
1960 case CPU_CAVIUM_OCTEON2:
1965 /* Examine entrylo 0 or 1 based on ptr. */
1966 if (use_bbit_insns()) {
1967 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
1969 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
1970 uasm_i_beqz(&p, wr.r3, 8);
1972 /* load it in the delay slot*/
1973 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
1974 /* load it if ptr is odd */
1975 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
1977 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
1978 * XI must have triggered it.
1980 if (use_bbit_insns()) {
1981 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
1983 uasm_l_tlbl_goaround1(&l, p);
1985 uasm_i_andi(&p, wr.r3, wr.r3, 2);
1986 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
1989 uasm_l_tlbl_goaround1(&l, p);
1991 build_make_valid(&p, &r, wr.r1, wr.r2);
1992 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
1994 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1996 * This is the entry point when build_r4000_tlbchange_handler_head
1997 * spots a huge page.
1999 uasm_l_tlb_huge_update(&l, p);
2000 iPTE_LW(&p, wr.r1, wr.r2);
2001 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2002 build_tlb_probe_entry(&p);
2004 if (cpu_has_rixi && !cpu_has_rixiex) {
2006 * If the page is not _PAGE_VALID, RI or XI could not
2007 * have triggered it. Skip the expensive test..
2009 if (use_bbit_insns()) {
2010 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2011 label_tlbl_goaround2);
2013 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2014 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2020 switch (current_cpu_type()) {
2022 if (cpu_has_mips_r2) {
2025 case CPU_CAVIUM_OCTEON:
2026 case CPU_CAVIUM_OCTEON_PLUS:
2027 case CPU_CAVIUM_OCTEON2:
2032 /* Examine entrylo 0 or 1 based on ptr. */
2033 if (use_bbit_insns()) {
2034 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2036 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2037 uasm_i_beqz(&p, wr.r3, 8);
2039 /* load it in the delay slot*/
2040 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2041 /* load it if ptr is odd */
2042 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2044 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2045 * XI must have triggered it.
2047 if (use_bbit_insns()) {
2048 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
2050 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2051 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2053 if (PM_DEFAULT_MASK == 0)
2056 * We clobbered C0_PAGEMASK, restore it. On the other branch
2057 * it is restored in build_huge_tlb_write_entry.
2059 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
2061 uasm_l_tlbl_goaround2(&l, p);
2063 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
2064 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2067 uasm_l_nopage_tlbl(&l, p);
2068 build_restore_work_registers(&p);
2069 #ifdef CONFIG_CPU_MICROMIPS
2070 if ((unsigned long)tlb_do_page_fault_0 & 1) {
2071 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0));
2072 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0));
2076 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
2079 if (p >= handle_tlbl_end)
2080 panic("TLB load handler fastpath space exceeded");
2082 uasm_resolve_relocs(relocs, labels);
2083 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2084 (unsigned int)(p - handle_tlbl));
2086 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size);
2089 static void build_r4000_tlb_store_handler(void)
2091 u32 *p = handle_tlbs;
2092 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
2093 struct uasm_label *l = labels;
2094 struct uasm_reloc *r = relocs;
2095 struct work_registers wr;
2097 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
2098 memset(labels, 0, sizeof(labels));
2099 memset(relocs, 0, sizeof(relocs));
2101 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2102 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2103 if (m4kc_tlbp_war())
2104 build_tlb_probe_entry(&p);
2105 build_make_write(&p, &r, wr.r1, wr.r2);
2106 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2108 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2110 * This is the entry point when
2111 * build_r4000_tlbchange_handler_head spots a huge page.
2113 uasm_l_tlb_huge_update(&l, p);
2114 iPTE_LW(&p, wr.r1, wr.r2);
2115 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2116 build_tlb_probe_entry(&p);
2117 uasm_i_ori(&p, wr.r1, wr.r1,
2118 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2119 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2122 uasm_l_nopage_tlbs(&l, p);
2123 build_restore_work_registers(&p);
2124 #ifdef CONFIG_CPU_MICROMIPS
2125 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2126 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2127 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2131 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2134 if (p >= handle_tlbs_end)
2135 panic("TLB store handler fastpath space exceeded");
2137 uasm_resolve_relocs(relocs, labels);
2138 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2139 (unsigned int)(p - handle_tlbs));
2141 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size);
2144 static void build_r4000_tlb_modify_handler(void)
2146 u32 *p = handle_tlbm;
2147 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
2148 struct uasm_label *l = labels;
2149 struct uasm_reloc *r = relocs;
2150 struct work_registers wr;
2152 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
2153 memset(labels, 0, sizeof(labels));
2154 memset(relocs, 0, sizeof(relocs));
2156 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2157 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2158 if (m4kc_tlbp_war())
2159 build_tlb_probe_entry(&p);
2160 /* Present and writable bits set, set accessed and dirty bits. */
2161 build_make_write(&p, &r, wr.r1, wr.r2);
2162 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2164 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2166 * This is the entry point when
2167 * build_r4000_tlbchange_handler_head spots a huge page.
2169 uasm_l_tlb_huge_update(&l, p);
2170 iPTE_LW(&p, wr.r1, wr.r2);
2171 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2172 build_tlb_probe_entry(&p);
2173 uasm_i_ori(&p, wr.r1, wr.r1,
2174 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2175 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2178 uasm_l_nopage_tlbm(&l, p);
2179 build_restore_work_registers(&p);
2180 #ifdef CONFIG_CPU_MICROMIPS
2181 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2182 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2183 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2187 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2190 if (p >= handle_tlbm_end)
2191 panic("TLB modify handler fastpath space exceeded");
2193 uasm_resolve_relocs(relocs, labels);
2194 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2195 (unsigned int)(p - handle_tlbm));
2197 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size);
2200 static void flush_tlb_handlers(void)
2202 local_flush_icache_range((unsigned long)handle_tlbl,
2203 (unsigned long)handle_tlbl_end);
2204 local_flush_icache_range((unsigned long)handle_tlbs,
2205 (unsigned long)handle_tlbs_end);
2206 local_flush_icache_range((unsigned long)handle_tlbm,
2207 (unsigned long)handle_tlbm_end);
2208 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2209 (unsigned long)tlbmiss_handler_setup_pgd_end);
2212 static void print_htw_config(void)
2214 unsigned long config;
2216 const int field = 2 * sizeof(unsigned long);
2218 config = read_c0_pwfield();
2219 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n",
2221 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT,
2222 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT,
2223 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT,
2224 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT,
2225 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
2227 config = read_c0_pwsize();
2228 pr_debug("PWSize (0x%0*lx): GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
2230 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
2231 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
2232 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
2233 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT,
2234 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
2236 pwctl = read_c0_pwctl();
2237 pr_debug("PWCtl (0x%x): PWEn: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
2239 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
2240 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
2241 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
2242 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
2245 static void config_htw_params(void)
2247 unsigned long pwfield, pwsize, ptei;
2248 unsigned int config;
2251 * We are using 2-level page tables, so we only need to
2252 * setup GDW and PTW appropriately. UDW and MDW will remain 0.
2253 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
2254 * write values less than 0xc in these fields because the entire
2255 * write will be dropped. As a result of which, we must preserve
2256 * the original reset values and overwrite only what we really want.
2259 pwfield = read_c0_pwfield();
2260 /* re-initialize the GDI field */
2261 pwfield &= ~MIPS_PWFIELD_GDI_MASK;
2262 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT;
2263 /* re-initialize the PTI field including the even/odd bit */
2264 pwfield &= ~MIPS_PWFIELD_PTI_MASK;
2265 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
2266 /* Set the PTEI right shift */
2267 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
2269 write_c0_pwfield(pwfield);
2270 /* Check whether the PTEI value is supported */
2271 back_to_back_c0_hazard();
2272 pwfield = read_c0_pwfield();
2273 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT)
2275 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
2278 * Drop option to avoid HTW being enabled via another path
2281 current_cpu_data.options &= ~MIPS_CPU_HTW;
2285 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
2286 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
2287 write_c0_pwsize(pwsize);
2289 /* Make sure everything is set before we enable the HTW */
2290 back_to_back_c0_hazard();
2292 /* Enable HTW and disable the rest of the pwctl fields */
2293 config = 1 << MIPS_PWCTL_PWEN_SHIFT;
2294 write_c0_pwctl(config);
2295 pr_info("Hardware Page Table Walker enabled\n");
2300 void build_tlb_refill_handler(void)
2303 * The refill handler is generated per-CPU, multi-node systems
2304 * may have local storage for it. The other handlers are only
2307 static int run_once = 0;
2309 output_pgtable_bits_defines();
2312 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2315 switch (current_cpu_type()) {
2323 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2324 if (cpu_has_local_ebase)
2325 build_r3000_tlb_refill_handler();
2327 if (!cpu_has_local_ebase)
2328 build_r3000_tlb_refill_handler();
2330 build_r3000_tlb_load_handler();
2331 build_r3000_tlb_store_handler();
2332 build_r3000_tlb_modify_handler();
2333 flush_tlb_handlers();
2337 panic("No R3000 TLB refill handler");
2343 panic("No R6000 TLB refill handler yet");
2347 panic("No R8000 TLB refill handler yet");
2352 scratch_reg = allocate_kscratch();
2354 build_r4000_tlb_load_handler();
2355 build_r4000_tlb_store_handler();
2356 build_r4000_tlb_modify_handler();
2357 if (!cpu_has_local_ebase)
2358 build_r4000_tlb_refill_handler();
2359 flush_tlb_handlers();
2362 if (cpu_has_local_ebase)
2363 build_r4000_tlb_refill_handler();
2365 config_htw_params();