2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Synthesize TLB refill handlers at runtime.
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
14 * ... and the days got worse and worse and now you see
15 * I've gone completly out of my mind.
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
21 * (Condolences to Napoleon XIV)
24 #include <linux/bug.h>
25 #include <linux/kernel.h>
26 #include <linux/types.h>
27 #include <linux/smp.h>
28 #include <linux/string.h>
29 #include <linux/init.h>
30 #include <linux/cache.h>
32 #include <asm/cacheflush.h>
33 #include <asm/pgtable.h>
36 #include <asm/setup.h>
39 * TLB load/store/modify handlers.
41 * Only the fastpath gets synthesized at runtime, the slowpath for
42 * do_page_fault remains normal asm.
44 extern void tlb_do_page_fault_0(void);
45 extern void tlb_do_page_fault_1(void);
47 struct work_registers {
56 } ____cacheline_aligned_in_smp;
58 static struct tlb_reg_save handler_reg_save[NR_CPUS];
60 static inline int r45k_bvahwbug(void)
62 /* XXX: We should probe for the presence of this bug, but we don't. */
66 static inline int r4k_250MHZhwbug(void)
68 /* XXX: We should probe for the presence of this bug, but we don't. */
72 static inline int __maybe_unused bcm1250_m3_war(void)
74 return BCM1250_M3_WAR;
77 static inline int __maybe_unused r10000_llsc_war(void)
79 return R10000_LLSC_WAR;
82 static int use_bbit_insns(void)
84 switch (current_cpu_type()) {
85 case CPU_CAVIUM_OCTEON:
86 case CPU_CAVIUM_OCTEON_PLUS:
87 case CPU_CAVIUM_OCTEON2:
94 static int use_lwx_insns(void)
96 switch (current_cpu_type()) {
97 case CPU_CAVIUM_OCTEON2:
103 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
104 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
105 static bool scratchpad_available(void)
109 static int scratchpad_offset(int i)
112 * CVMSEG starts at address -32768 and extends for
113 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
115 i += 1; /* Kernel use starts at the top and works down. */
116 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
119 static bool scratchpad_available(void)
123 static int scratchpad_offset(int i)
126 /* Really unreachable, but evidently some GCC want this. */
131 * Found by experiment: At least some revisions of the 4kc throw under
132 * some circumstances a machine check exception, triggered by invalid
133 * values in the index register. Delaying the tlbp instruction until
134 * after the next branch, plus adding an additional nop in front of
135 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
136 * why; it's not an issue caused by the core RTL.
139 static int __cpuinit m4kc_tlbp_war(void)
141 return (current_cpu_data.processor_id & 0xffff00) ==
142 (PRID_COMP_MIPS | PRID_IMP_4KC);
145 /* Handle labels (which must be positive integers). */
147 label_second_part = 1,
153 label_tlbl_goaround1,
154 label_tlbl_goaround2,
158 label_smp_pgtable_change,
159 label_r3000_write_probe_fail,
160 label_large_segbits_fault,
161 #ifdef CONFIG_HUGETLB_PAGE
162 label_tlb_huge_update,
166 UASM_L_LA(_second_part)
169 UASM_L_LA(_vmalloc_done)
170 UASM_L_LA(_tlbw_hazard)
172 UASM_L_LA(_tlbl_goaround1)
173 UASM_L_LA(_tlbl_goaround2)
174 UASM_L_LA(_nopage_tlbl)
175 UASM_L_LA(_nopage_tlbs)
176 UASM_L_LA(_nopage_tlbm)
177 UASM_L_LA(_smp_pgtable_change)
178 UASM_L_LA(_r3000_write_probe_fail)
179 UASM_L_LA(_large_segbits_fault)
180 #ifdef CONFIG_HUGETLB_PAGE
181 UASM_L_LA(_tlb_huge_update)
185 * For debug purposes.
187 static inline void dump_handler(const u32 *handler, int count)
191 pr_debug("\t.set push\n");
192 pr_debug("\t.set noreorder\n");
194 for (i = 0; i < count; i++)
195 pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]);
197 pr_debug("\t.set pop\n");
200 /* The only general purpose registers allowed in TLB handlers. */
204 /* Some CP0 registers */
205 #define C0_INDEX 0, 0
206 #define C0_ENTRYLO0 2, 0
207 #define C0_TCBIND 2, 2
208 #define C0_ENTRYLO1 3, 0
209 #define C0_CONTEXT 4, 0
210 #define C0_PAGEMASK 5, 0
211 #define C0_BADVADDR 8, 0
212 #define C0_ENTRYHI 10, 0
214 #define C0_XCONTEXT 20, 0
217 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
219 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
222 /* The worst case length of the handler is around 18 instructions for
223 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
224 * Maximum space available is 32 instructions for R3000 and 64
225 * instructions for R4000.
227 * We deliberately chose a buffer size of 128, so we won't scribble
228 * over anything important on overflow before we panic.
230 static u32 tlb_handler[128] __cpuinitdata;
232 /* simply assume worst case size for labels and relocs */
233 static struct uasm_label labels[128] __cpuinitdata;
234 static struct uasm_reloc relocs[128] __cpuinitdata;
237 static int check_for_high_segbits __cpuinitdata;
240 static int check_for_high_segbits __cpuinitdata;
242 static unsigned int kscratch_used_mask __cpuinitdata;
244 static int __cpuinit allocate_kscratch(void)
247 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
254 r--; /* make it zero based */
256 kscratch_used_mask |= (1 << r);
261 static int scratch_reg __cpuinitdata;
262 static int pgd_reg __cpuinitdata;
263 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
265 static struct work_registers __cpuinit build_get_work_registers(u32 **p)
267 struct work_registers r;
269 int smp_processor_id_reg;
270 int smp_processor_id_sel;
271 int smp_processor_id_shift;
273 if (scratch_reg > 0) {
274 /* Save in CPU local C0_KScratch? */
275 UASM_i_MTC0(p, 1, 31, scratch_reg);
282 if (num_possible_cpus() > 1) {
283 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
284 smp_processor_id_shift = 51;
285 smp_processor_id_reg = 20; /* XContext */
286 smp_processor_id_sel = 0;
289 smp_processor_id_shift = 25;
290 smp_processor_id_reg = 4; /* Context */
291 smp_processor_id_sel = 0;
294 smp_processor_id_shift = 26;
295 smp_processor_id_reg = 4; /* Context */
296 smp_processor_id_sel = 0;
299 /* Get smp_processor_id */
300 UASM_i_MFC0(p, K0, smp_processor_id_reg, smp_processor_id_sel);
301 UASM_i_SRL_SAFE(p, K0, K0, smp_processor_id_shift);
303 /* handler_reg_save index in K0 */
304 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
306 UASM_i_LA(p, K1, (long)&handler_reg_save);
307 UASM_i_ADDU(p, K0, K0, K1);
309 UASM_i_LA(p, K0, (long)&handler_reg_save);
311 /* K0 now points to save area, save $1 and $2 */
312 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
313 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
321 static void __cpuinit build_restore_work_registers(u32 **p)
323 if (scratch_reg > 0) {
324 UASM_i_MFC0(p, 1, 31, scratch_reg);
327 /* K0 already points to save area, restore $1 and $2 */
328 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
329 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
332 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
335 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
336 * we cannot do r3000 under these circumstances.
338 * Declare pgd_current here instead of including mmu_context.h to avoid type
339 * conflicts for tlbmiss_handler_setup_pgd
341 extern unsigned long pgd_current[];
344 * The R3000 TLB handler is simple.
346 static void __cpuinit build_r3000_tlb_refill_handler(void)
348 long pgdc = (long)pgd_current;
351 memset(tlb_handler, 0, sizeof(tlb_handler));
354 uasm_i_mfc0(&p, K0, C0_BADVADDR);
355 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
356 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
357 uasm_i_srl(&p, K0, K0, 22); /* load delay */
358 uasm_i_sll(&p, K0, K0, 2);
359 uasm_i_addu(&p, K1, K1, K0);
360 uasm_i_mfc0(&p, K0, C0_CONTEXT);
361 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
362 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
363 uasm_i_addu(&p, K1, K1, K0);
364 uasm_i_lw(&p, K0, 0, K1);
365 uasm_i_nop(&p); /* load delay */
366 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
367 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
368 uasm_i_tlbwr(&p); /* cp0 delay */
370 uasm_i_rfe(&p); /* branch delay */
372 if (p > tlb_handler + 32)
373 panic("TLB refill handler space exceeded");
375 pr_debug("Wrote TLB refill handler (%u instructions).\n",
376 (unsigned int)(p - tlb_handler));
378 memcpy((void *)ebase, tlb_handler, 0x80);
380 dump_handler((u32 *)ebase, 32);
382 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
385 * The R4000 TLB handler is much more complicated. We have two
386 * consecutive handler areas with 32 instructions space each.
387 * Since they aren't used at the same time, we can overflow in the
388 * other one.To keep things simple, we first assume linear space,
389 * then we relocate it to the final handler layout as needed.
391 static u32 final_handler[64] __cpuinitdata;
396 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
397 * 2. A timing hazard exists for the TLBP instruction.
399 * stalling_instruction
402 * The JTLB is being read for the TLBP throughout the stall generated by the
403 * previous instruction. This is not really correct as the stalling instruction
404 * can modify the address used to access the JTLB. The failure symptom is that
405 * the TLBP instruction will use an address created for the stalling instruction
406 * and not the address held in C0_ENHI and thus report the wrong results.
408 * The software work-around is to not allow the instruction preceding the TLBP
409 * to stall - make it an NOP or some other instruction guaranteed not to stall.
411 * Errata 2 will not be fixed. This errata is also on the R5000.
413 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
415 static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
417 switch (current_cpu_type()) {
418 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
435 * Write random or indexed TLB entry, and care about the hazards from
436 * the preceding mtc0 and for the following eret.
438 enum tlb_write_entry { tlb_random, tlb_indexed };
440 static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
441 struct uasm_reloc **r,
442 enum tlb_write_entry wmode)
444 void(*tlbw)(u32 **) = NULL;
447 case tlb_random: tlbw = uasm_i_tlbwr; break;
448 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
451 if (cpu_has_mips_r2) {
452 if (cpu_has_mips_r2_exec_hazard)
458 switch (current_cpu_type()) {
466 * This branch uses up a mtc0 hazard nop slot and saves
467 * two nops after the tlbw instruction.
469 uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
471 uasm_l_tlbw_hazard(l, *p);
518 uasm_i_nop(p); /* QED specifies 2 nops hazard */
520 * This branch uses up a mtc0 hazard nop slot and saves
521 * a nop after the tlbw instruction.
523 uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
525 uasm_l_tlbw_hazard(l, *p);
538 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
539 * use of the JTLB for instructions should not occur for 4
540 * cpu cycles and use for data translations should not occur
580 panic("No TLB refill handler yet (CPU type: %d)",
581 current_cpu_data.cputype);
586 static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
589 if (kernel_uses_smartmips_rixi) {
590 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
591 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
593 #ifdef CONFIG_64BIT_PHYS_ADDR
594 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
596 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
601 #ifdef CONFIG_HUGETLB_PAGE
603 static __cpuinit void build_restore_pagemask(u32 **p,
604 struct uasm_reloc **r,
609 if (restore_scratch) {
610 /* Reset default page size */
611 if (PM_DEFAULT_MASK >> 16) {
612 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
613 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
614 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
615 uasm_il_b(p, r, lid);
616 } else if (PM_DEFAULT_MASK) {
617 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
618 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
619 uasm_il_b(p, r, lid);
621 uasm_i_mtc0(p, 0, C0_PAGEMASK);
622 uasm_il_b(p, r, lid);
625 UASM_i_MFC0(p, 1, 31, scratch_reg);
627 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
629 /* Reset default page size */
630 if (PM_DEFAULT_MASK >> 16) {
631 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
632 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
633 uasm_il_b(p, r, lid);
634 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
635 } else if (PM_DEFAULT_MASK) {
636 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
637 uasm_il_b(p, r, lid);
638 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
640 uasm_il_b(p, r, lid);
641 uasm_i_mtc0(p, 0, C0_PAGEMASK);
646 static __cpuinit void build_huge_tlb_write_entry(u32 **p,
647 struct uasm_label **l,
648 struct uasm_reloc **r,
650 enum tlb_write_entry wmode,
653 /* Set huge page tlb entry size */
654 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
655 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
656 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
658 build_tlb_write_entry(p, l, r, wmode);
660 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
664 * Check if Huge PTE is present, if so then jump to LABEL.
666 static void __cpuinit
667 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
668 unsigned int pmd, int lid)
670 UASM_i_LW(p, tmp, 0, pmd);
671 if (use_bbit_insns()) {
672 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
674 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
675 uasm_il_bnez(p, r, tmp, lid);
679 static __cpuinit void build_huge_update_entries(u32 **p,
686 * A huge PTE describes an area the size of the
687 * configured huge page size. This is twice the
688 * of the large TLB entry size we intend to use.
689 * A TLB entry half the size of the configured
690 * huge page size is configured into entrylo0
691 * and entrylo1 to cover the contiguous huge PTE
694 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
696 /* We can clobber tmp. It isn't used after this.*/
698 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
700 build_convert_pte_to_entrylo(p, pte);
701 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
702 /* convert to entrylo1 */
704 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
706 UASM_i_ADDU(p, pte, pte, tmp);
708 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
711 static __cpuinit void build_huge_handler_tail(u32 **p,
712 struct uasm_reloc **r,
713 struct uasm_label **l,
718 UASM_i_SC(p, pte, 0, ptr);
719 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
720 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
722 UASM_i_SW(p, pte, 0, ptr);
724 build_huge_update_entries(p, pte, ptr);
725 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
727 #endif /* CONFIG_HUGETLB_PAGE */
731 * TMP and PTR are scratch.
732 * TMP will be clobbered, PTR will hold the pmd entry.
734 static void __cpuinit
735 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
736 unsigned int tmp, unsigned int ptr)
738 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
739 long pgdc = (long)pgd_current;
742 * The vmalloc handling is not in the hotpath.
744 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
746 if (check_for_high_segbits) {
748 * The kernel currently implicitely assumes that the
749 * MIPS SEGBITS parameter for the processor is
750 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
751 * allocate virtual addresses outside the maximum
752 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
753 * that doesn't prevent user code from accessing the
754 * higher xuseg addresses. Here, we make sure that
755 * everything but the lower xuseg addresses goes down
756 * the module_alloc/vmalloc path.
758 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
759 uasm_il_bnez(p, r, ptr, label_vmalloc);
761 uasm_il_bltz(p, r, tmp, label_vmalloc);
763 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
765 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
767 /* pgd is in pgd_reg */
768 UASM_i_MFC0(p, ptr, 31, pgd_reg);
771 * &pgd << 11 stored in CONTEXT [23..63].
773 UASM_i_MFC0(p, ptr, C0_CONTEXT);
775 /* Clear lower 23 bits of context. */
776 uasm_i_dins(p, ptr, 0, 0, 23);
778 /* 1 0 1 0 1 << 6 xkphys cached */
779 uasm_i_ori(p, ptr, ptr, 0x540);
780 uasm_i_drotr(p, ptr, ptr, 11);
782 #elif defined(CONFIG_SMP)
783 # ifdef CONFIG_MIPS_MT_SMTC
785 * SMTC uses TCBind value as "CPU" index
787 uasm_i_mfc0(p, ptr, C0_TCBIND);
788 uasm_i_dsrl_safe(p, ptr, ptr, 19);
791 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
794 uasm_i_dmfc0(p, ptr, C0_CONTEXT);
795 uasm_i_dsrl_safe(p, ptr, ptr, 23);
797 UASM_i_LA_mostly(p, tmp, pgdc);
798 uasm_i_daddu(p, ptr, ptr, tmp);
799 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
800 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
802 UASM_i_LA_mostly(p, ptr, pgdc);
803 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
806 uasm_l_vmalloc_done(l, *p);
808 /* get pgd offset in bytes */
809 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
811 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
812 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
813 #ifndef __PAGETABLE_PMD_FOLDED
814 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
815 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
816 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
817 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
818 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
823 * BVADDR is the faulting address, PTR is scratch.
824 * PTR will hold the pgd for vmalloc.
826 static void __cpuinit
827 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
828 unsigned int bvaddr, unsigned int ptr,
829 enum vmalloc64_mode mode)
831 long swpd = (long)swapper_pg_dir;
832 int single_insn_swpd;
833 int did_vmalloc_branch = 0;
835 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
837 uasm_l_vmalloc(l, *p);
839 if (mode != not_refill && check_for_high_segbits) {
840 if (single_insn_swpd) {
841 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
842 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
843 did_vmalloc_branch = 1;
846 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
849 if (!did_vmalloc_branch) {
850 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) {
851 uasm_il_b(p, r, label_vmalloc_done);
852 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
854 UASM_i_LA_mostly(p, ptr, swpd);
855 uasm_il_b(p, r, label_vmalloc_done);
856 if (uasm_in_compat_space_p(swpd))
857 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
859 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
862 if (mode != not_refill && check_for_high_segbits) {
863 uasm_l_large_segbits_fault(l, *p);
865 * We get here if we are an xsseg address, or if we are
866 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
868 * Ignoring xsseg (assume disabled so would generate
869 * (address errors?), the only remaining possibility
870 * is the upper xuseg addresses. On processors with
871 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
872 * addresses would have taken an address error. We try
873 * to mimic that here by taking a load/istream page
876 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
879 if (mode == refill_scratch) {
881 UASM_i_MFC0(p, 1, 31, scratch_reg);
883 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
890 #else /* !CONFIG_64BIT */
893 * TMP and PTR are scratch.
894 * TMP will be clobbered, PTR will hold the pgd entry.
896 static void __cpuinit __maybe_unused
897 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
899 long pgdc = (long)pgd_current;
901 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
903 #ifdef CONFIG_MIPS_MT_SMTC
905 * SMTC uses TCBind value as "CPU" index
907 uasm_i_mfc0(p, ptr, C0_TCBIND);
908 UASM_i_LA_mostly(p, tmp, pgdc);
909 uasm_i_srl(p, ptr, ptr, 19);
912 * smp_processor_id() << 3 is stored in CONTEXT.
914 uasm_i_mfc0(p, ptr, C0_CONTEXT);
915 UASM_i_LA_mostly(p, tmp, pgdc);
916 uasm_i_srl(p, ptr, ptr, 23);
918 uasm_i_addu(p, ptr, tmp, ptr);
920 UASM_i_LA_mostly(p, ptr, pgdc);
922 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
923 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
924 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
925 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
926 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
929 #endif /* !CONFIG_64BIT */
931 static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx)
933 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
934 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
936 switch (current_cpu_type()) {
953 UASM_i_SRL(p, ctx, ctx, shift);
954 uasm_i_andi(p, ctx, ctx, mask);
957 static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
960 * Bug workaround for the Nevada. It seems as if under certain
961 * circumstances the move from cp0_context might produce a
962 * bogus result when the mfc0 instruction and its consumer are
963 * in a different cacheline or a load instruction, probably any
964 * memory reference, is between them.
966 switch (current_cpu_type()) {
968 UASM_i_LW(p, ptr, 0, ptr);
969 GET_CONTEXT(p, tmp); /* get context reg */
973 GET_CONTEXT(p, tmp); /* get context reg */
974 UASM_i_LW(p, ptr, 0, ptr);
978 build_adjust_context(p, tmp);
979 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
982 static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
986 * 64bit address support (36bit on a 32bit CPU) in a 32bit
987 * Kernel is a special case. Only a few CPUs use it.
989 #ifdef CONFIG_64BIT_PHYS_ADDR
990 if (cpu_has_64bits) {
991 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
992 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
993 if (kernel_uses_smartmips_rixi) {
994 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
995 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
996 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
997 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
998 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
1000 uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
1001 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1002 uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
1004 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1006 int pte_off_even = sizeof(pte_t) / 2;
1007 int pte_off_odd = pte_off_even + sizeof(pte_t);
1009 /* The pte entries are pre-shifted */
1010 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
1011 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1012 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
1013 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1016 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
1017 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1018 if (r45k_bvahwbug())
1019 build_tlb_probe_entry(p);
1020 if (kernel_uses_smartmips_rixi) {
1021 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
1022 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
1023 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
1024 if (r4k_250MHZhwbug())
1025 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1026 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1027 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
1029 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
1030 if (r4k_250MHZhwbug())
1031 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1032 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1033 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
1034 if (r45k_bvahwbug())
1035 uasm_i_mfc0(p, tmp, C0_INDEX);
1037 if (r4k_250MHZhwbug())
1038 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1039 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1043 struct mips_huge_tlb_info {
1045 int restore_scratch;
1048 static struct mips_huge_tlb_info __cpuinit
1049 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1050 struct uasm_reloc **r, unsigned int tmp,
1051 unsigned int ptr, int c0_scratch)
1053 struct mips_huge_tlb_info rv;
1054 unsigned int even, odd;
1055 int vmalloc_branch_delay_filled = 0;
1056 const int scratch = 1; /* Our extra working register */
1058 rv.huge_pte = scratch;
1059 rv.restore_scratch = 0;
1061 if (check_for_high_segbits) {
1062 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1065 UASM_i_MFC0(p, ptr, 31, pgd_reg);
1067 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1069 if (c0_scratch >= 0)
1070 UASM_i_MTC0(p, scratch, 31, c0_scratch);
1072 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1074 uasm_i_dsrl_safe(p, scratch, tmp,
1075 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1076 uasm_il_bnez(p, r, scratch, label_vmalloc);
1078 if (pgd_reg == -1) {
1079 vmalloc_branch_delay_filled = 1;
1080 /* Clear lower 23 bits of context. */
1081 uasm_i_dins(p, ptr, 0, 0, 23);
1085 UASM_i_MFC0(p, ptr, 31, pgd_reg);
1087 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1089 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1091 if (c0_scratch >= 0)
1092 UASM_i_MTC0(p, scratch, 31, c0_scratch);
1094 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1097 /* Clear lower 23 bits of context. */
1098 uasm_i_dins(p, ptr, 0, 0, 23);
1100 uasm_il_bltz(p, r, tmp, label_vmalloc);
1103 if (pgd_reg == -1) {
1104 vmalloc_branch_delay_filled = 1;
1105 /* 1 0 1 0 1 << 6 xkphys cached */
1106 uasm_i_ori(p, ptr, ptr, 0x540);
1107 uasm_i_drotr(p, ptr, ptr, 11);
1110 #ifdef __PAGETABLE_PMD_FOLDED
1111 #define LOC_PTEP scratch
1113 #define LOC_PTEP ptr
1116 if (!vmalloc_branch_delay_filled)
1117 /* get pgd offset in bytes */
1118 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1120 uasm_l_vmalloc_done(l, *p);
1124 * fall-through case = badvaddr *pgd_current
1125 * vmalloc case = badvaddr swapper_pg_dir
1128 if (vmalloc_branch_delay_filled)
1129 /* get pgd offset in bytes */
1130 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1132 #ifdef __PAGETABLE_PMD_FOLDED
1133 GET_CONTEXT(p, tmp); /* get context reg */
1135 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
1137 if (use_lwx_insns()) {
1138 UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
1140 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
1141 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1144 #ifndef __PAGETABLE_PMD_FOLDED
1145 /* get pmd offset in bytes */
1146 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
1147 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
1148 GET_CONTEXT(p, tmp); /* get context reg */
1150 if (use_lwx_insns()) {
1151 UASM_i_LWX(p, scratch, scratch, ptr);
1153 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1154 UASM_i_LW(p, scratch, 0, ptr);
1157 /* Adjust the context during the load latency. */
1158 build_adjust_context(p, tmp);
1160 #ifdef CONFIG_HUGETLB_PAGE
1161 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
1163 * The in the LWX case we don't want to do the load in the
1164 * delay slot. It cannot issue in the same cycle and may be
1165 * speculative and unneeded.
1167 if (use_lwx_insns())
1169 #endif /* CONFIG_HUGETLB_PAGE */
1172 /* build_update_entries */
1173 if (use_lwx_insns()) {
1176 UASM_i_LWX(p, even, scratch, tmp);
1177 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
1178 UASM_i_LWX(p, odd, scratch, tmp);
1180 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
1183 UASM_i_LW(p, even, 0, ptr); /* get even pte */
1184 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
1186 if (kernel_uses_smartmips_rixi) {
1187 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_NO_EXEC));
1188 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_NO_EXEC));
1189 uasm_i_drotr(p, even, even,
1190 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
1191 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1192 uasm_i_drotr(p, odd, odd,
1193 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
1195 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
1196 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1197 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
1199 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1201 if (c0_scratch >= 0) {
1202 UASM_i_MFC0(p, scratch, 31, c0_scratch);
1203 build_tlb_write_entry(p, l, r, tlb_random);
1204 uasm_l_leave(l, *p);
1205 rv.restore_scratch = 1;
1206 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
1207 build_tlb_write_entry(p, l, r, tlb_random);
1208 uasm_l_leave(l, *p);
1209 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1211 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1212 build_tlb_write_entry(p, l, r, tlb_random);
1213 uasm_l_leave(l, *p);
1214 rv.restore_scratch = 1;
1217 uasm_i_eret(p); /* return from trap */
1223 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1224 * because EXL == 0. If we wrap, we can also use the 32 instruction
1225 * slots before the XTLB refill exception handler which belong to the
1226 * unused TLB refill exception.
1228 #define MIPS64_REFILL_INSNS 32
1230 static void __cpuinit build_r4000_tlb_refill_handler(void)
1232 u32 *p = tlb_handler;
1233 struct uasm_label *l = labels;
1234 struct uasm_reloc *r = relocs;
1236 unsigned int final_len;
1237 struct mips_huge_tlb_info htlb_info __maybe_unused;
1238 enum vmalloc64_mode vmalloc_mode __maybe_unused;
1240 memset(tlb_handler, 0, sizeof(tlb_handler));
1241 memset(labels, 0, sizeof(labels));
1242 memset(relocs, 0, sizeof(relocs));
1243 memset(final_handler, 0, sizeof(final_handler));
1245 if ((scratch_reg > 0 || scratchpad_available()) && use_bbit_insns()) {
1246 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1248 vmalloc_mode = refill_scratch;
1250 htlb_info.huge_pte = K0;
1251 htlb_info.restore_scratch = 0;
1252 vmalloc_mode = refill_noscratch;
1254 * create the plain linear handler
1256 if (bcm1250_m3_war()) {
1257 unsigned int segbits = 44;
1259 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1260 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1261 uasm_i_xor(&p, K0, K0, K1);
1262 uasm_i_dsrl_safe(&p, K1, K0, 62);
1263 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1264 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1265 uasm_i_or(&p, K0, K0, K1);
1266 uasm_il_bnez(&p, &r, K0, label_leave);
1267 /* No need for uasm_i_nop */
1271 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1273 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1276 #ifdef CONFIG_HUGETLB_PAGE
1277 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
1280 build_get_ptep(&p, K0, K1);
1281 build_update_entries(&p, K0, K1);
1282 build_tlb_write_entry(&p, &l, &r, tlb_random);
1283 uasm_l_leave(&l, p);
1284 uasm_i_eret(&p); /* return from trap */
1286 #ifdef CONFIG_HUGETLB_PAGE
1287 uasm_l_tlb_huge_update(&l, p);
1288 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1289 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1290 htlb_info.restore_scratch);
1294 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
1298 * Overflow check: For the 64bit handler, we need at least one
1299 * free instruction slot for the wrap-around branch. In worst
1300 * case, if the intended insertion point is a delay slot, we
1301 * need three, with the second nop'ed and the third being
1304 /* Loongson2 ebase is different than r4k, we have more space */
1305 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
1306 if ((p - tlb_handler) > 64)
1307 panic("TLB refill handler space exceeded");
1309 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1310 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1311 && uasm_insn_has_bdelay(relocs,
1312 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1313 panic("TLB refill handler space exceeded");
1317 * Now fold the handler in the TLB refill handler space.
1319 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
1321 /* Simplest case, just copy the handler. */
1322 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1323 final_len = p - tlb_handler;
1324 #else /* CONFIG_64BIT */
1325 f = final_handler + MIPS64_REFILL_INSNS;
1326 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1327 /* Just copy the handler. */
1328 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1329 final_len = p - tlb_handler;
1331 #if defined(CONFIG_HUGETLB_PAGE)
1332 const enum label_id ls = label_tlb_huge_update;
1334 const enum label_id ls = label_vmalloc;
1340 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1342 BUG_ON(i == ARRAY_SIZE(labels));
1343 split = labels[i].addr;
1346 * See if we have overflown one way or the other.
1348 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1349 split < p - MIPS64_REFILL_INSNS)
1354 * Split two instructions before the end. One
1355 * for the branch and one for the instruction
1356 * in the delay slot.
1358 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1361 * If the branch would fall in a delay slot,
1362 * we must back up an additional instruction
1363 * so that it is no longer in a delay slot.
1365 if (uasm_insn_has_bdelay(relocs, split - 1))
1368 /* Copy first part of the handler. */
1369 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1370 f += split - tlb_handler;
1373 /* Insert branch. */
1374 uasm_l_split(&l, final_handler);
1375 uasm_il_b(&f, &r, label_split);
1376 if (uasm_insn_has_bdelay(relocs, split))
1379 uasm_copy_handler(relocs, labels,
1380 split, split + 1, f);
1381 uasm_move_labels(labels, f, f + 1, -1);
1387 /* Copy the rest of the handler. */
1388 uasm_copy_handler(relocs, labels, split, p, final_handler);
1389 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1392 #endif /* CONFIG_64BIT */
1394 uasm_resolve_relocs(relocs, labels);
1395 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1398 memcpy((void *)ebase, final_handler, 0x100);
1400 dump_handler((u32 *)ebase, 64);
1404 * 128 instructions for the fastpath handler is generous and should
1405 * never be exceeded.
1407 #define FASTPATH_SIZE 128
1409 u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned;
1410 u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
1411 u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
1412 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1413 u32 tlbmiss_handler_setup_pgd[16] __cacheline_aligned;
1415 static void __cpuinit build_r4000_setup_pgd(void)
1419 u32 *p = tlbmiss_handler_setup_pgd;
1420 struct uasm_label *l = labels;
1421 struct uasm_reloc *r = relocs;
1423 memset(tlbmiss_handler_setup_pgd, 0, sizeof(tlbmiss_handler_setup_pgd));
1424 memset(labels, 0, sizeof(labels));
1425 memset(relocs, 0, sizeof(relocs));
1427 pgd_reg = allocate_kscratch();
1429 if (pgd_reg == -1) {
1430 /* PGD << 11 in c0_Context */
1432 * If it is a ckseg0 address, convert to a physical
1433 * address. Shifting right by 29 and adding 4 will
1434 * result in zero for these addresses.
1437 UASM_i_SRA(&p, a1, a0, 29);
1438 UASM_i_ADDIU(&p, a1, a1, 4);
1439 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
1441 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
1442 uasm_l_tlbl_goaround1(&l, p);
1443 UASM_i_SLL(&p, a0, a0, 11);
1445 UASM_i_MTC0(&p, a0, C0_CONTEXT);
1447 /* PGD in c0_KScratch */
1449 UASM_i_MTC0(&p, a0, 31, pgd_reg);
1451 if (p - tlbmiss_handler_setup_pgd > ARRAY_SIZE(tlbmiss_handler_setup_pgd))
1452 panic("tlbmiss_handler_setup_pgd space exceeded");
1453 uasm_resolve_relocs(relocs, labels);
1454 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1455 (unsigned int)(p - tlbmiss_handler_setup_pgd));
1457 dump_handler(tlbmiss_handler_setup_pgd,
1458 ARRAY_SIZE(tlbmiss_handler_setup_pgd));
1462 static void __cpuinit
1463 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1466 # ifdef CONFIG_64BIT_PHYS_ADDR
1468 uasm_i_lld(p, pte, 0, ptr);
1471 UASM_i_LL(p, pte, 0, ptr);
1473 # ifdef CONFIG_64BIT_PHYS_ADDR
1475 uasm_i_ld(p, pte, 0, ptr);
1478 UASM_i_LW(p, pte, 0, ptr);
1482 static void __cpuinit
1483 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1486 #ifdef CONFIG_64BIT_PHYS_ADDR
1487 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1490 uasm_i_ori(p, pte, pte, mode);
1492 # ifdef CONFIG_64BIT_PHYS_ADDR
1494 uasm_i_scd(p, pte, 0, ptr);
1497 UASM_i_SC(p, pte, 0, ptr);
1499 if (r10000_llsc_war())
1500 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1502 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1504 # ifdef CONFIG_64BIT_PHYS_ADDR
1505 if (!cpu_has_64bits) {
1506 /* no uasm_i_nop needed */
1507 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1508 uasm_i_ori(p, pte, pte, hwmode);
1509 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1510 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1511 /* no uasm_i_nop needed */
1512 uasm_i_lw(p, pte, 0, ptr);
1519 # ifdef CONFIG_64BIT_PHYS_ADDR
1521 uasm_i_sd(p, pte, 0, ptr);
1524 UASM_i_SW(p, pte, 0, ptr);
1526 # ifdef CONFIG_64BIT_PHYS_ADDR
1527 if (!cpu_has_64bits) {
1528 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1529 uasm_i_ori(p, pte, pte, hwmode);
1530 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1531 uasm_i_lw(p, pte, 0, ptr);
1538 * Check if PTE is present, if not then jump to LABEL. PTR points to
1539 * the page table where this PTE is located, PTE will be re-loaded
1540 * with it's original value.
1542 static void __cpuinit
1543 build_pte_present(u32 **p, struct uasm_reloc **r,
1544 int pte, int ptr, int scratch, enum label_id lid)
1546 int t = scratch >= 0 ? scratch : pte;
1548 if (kernel_uses_smartmips_rixi) {
1549 if (use_bbit_insns()) {
1550 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1553 uasm_i_andi(p, t, pte, _PAGE_PRESENT);
1554 uasm_il_beqz(p, r, t, lid);
1556 /* You lose the SMP race :-(*/
1557 iPTE_LW(p, pte, ptr);
1560 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_READ);
1561 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_READ);
1562 uasm_il_bnez(p, r, t, lid);
1564 /* You lose the SMP race :-(*/
1565 iPTE_LW(p, pte, ptr);
1569 /* Make PTE valid, store result in PTR. */
1570 static void __cpuinit
1571 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1574 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1576 iPTE_SW(p, r, pte, ptr, mode);
1580 * Check if PTE can be written to, if not branch to LABEL. Regardless
1581 * restore PTE with value from PTR when done.
1583 static void __cpuinit
1584 build_pte_writable(u32 **p, struct uasm_reloc **r,
1585 unsigned int pte, unsigned int ptr, int scratch,
1588 int t = scratch >= 0 ? scratch : pte;
1590 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_WRITE);
1591 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_WRITE);
1592 uasm_il_bnez(p, r, t, lid);
1594 /* You lose the SMP race :-(*/
1595 iPTE_LW(p, pte, ptr);
1600 /* Make PTE writable, update software status bits as well, then store
1603 static void __cpuinit
1604 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1607 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1610 iPTE_SW(p, r, pte, ptr, mode);
1614 * Check if PTE can be modified, if not branch to LABEL. Regardless
1615 * restore PTE with value from PTR when done.
1617 static void __cpuinit
1618 build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1619 unsigned int pte, unsigned int ptr, int scratch,
1622 if (use_bbit_insns()) {
1623 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
1626 int t = scratch >= 0 ? scratch : pte;
1627 uasm_i_andi(p, t, pte, _PAGE_WRITE);
1628 uasm_il_beqz(p, r, t, lid);
1630 /* You lose the SMP race :-(*/
1631 iPTE_LW(p, pte, ptr);
1635 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1639 * R3000 style TLB load/store/modify handlers.
1643 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1646 static void __cpuinit
1647 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1649 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1650 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1653 uasm_i_rfe(p); /* branch delay */
1657 * This places the pte into ENTRYLO0 and writes it with tlbwi
1658 * or tlbwr as appropriate. This is because the index register
1659 * may have the probe fail bit set as a result of a trap on a
1660 * kseg2 access, i.e. without refill. Then it returns.
1662 static void __cpuinit
1663 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1664 struct uasm_reloc **r, unsigned int pte,
1667 uasm_i_mfc0(p, tmp, C0_INDEX);
1668 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1669 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1670 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1671 uasm_i_tlbwi(p); /* cp0 delay */
1673 uasm_i_rfe(p); /* branch delay */
1674 uasm_l_r3000_write_probe_fail(l, *p);
1675 uasm_i_tlbwr(p); /* cp0 delay */
1677 uasm_i_rfe(p); /* branch delay */
1680 static void __cpuinit
1681 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1684 long pgdc = (long)pgd_current;
1686 uasm_i_mfc0(p, pte, C0_BADVADDR);
1687 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1688 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1689 uasm_i_srl(p, pte, pte, 22); /* load delay */
1690 uasm_i_sll(p, pte, pte, 2);
1691 uasm_i_addu(p, ptr, ptr, pte);
1692 uasm_i_mfc0(p, pte, C0_CONTEXT);
1693 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1694 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1695 uasm_i_addu(p, ptr, ptr, pte);
1696 uasm_i_lw(p, pte, 0, ptr);
1697 uasm_i_tlbp(p); /* load delay */
1700 static void __cpuinit build_r3000_tlb_load_handler(void)
1702 u32 *p = handle_tlbl;
1703 struct uasm_label *l = labels;
1704 struct uasm_reloc *r = relocs;
1706 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1707 memset(labels, 0, sizeof(labels));
1708 memset(relocs, 0, sizeof(relocs));
1710 build_r3000_tlbchange_handler_head(&p, K0, K1);
1711 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
1712 uasm_i_nop(&p); /* load delay */
1713 build_make_valid(&p, &r, K0, K1);
1714 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1716 uasm_l_nopage_tlbl(&l, p);
1717 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1720 if ((p - handle_tlbl) > FASTPATH_SIZE)
1721 panic("TLB load handler fastpath space exceeded");
1723 uasm_resolve_relocs(relocs, labels);
1724 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1725 (unsigned int)(p - handle_tlbl));
1727 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
1730 static void __cpuinit build_r3000_tlb_store_handler(void)
1732 u32 *p = handle_tlbs;
1733 struct uasm_label *l = labels;
1734 struct uasm_reloc *r = relocs;
1736 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1737 memset(labels, 0, sizeof(labels));
1738 memset(relocs, 0, sizeof(relocs));
1740 build_r3000_tlbchange_handler_head(&p, K0, K1);
1741 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
1742 uasm_i_nop(&p); /* load delay */
1743 build_make_write(&p, &r, K0, K1);
1744 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1746 uasm_l_nopage_tlbs(&l, p);
1747 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1750 if ((p - handle_tlbs) > FASTPATH_SIZE)
1751 panic("TLB store handler fastpath space exceeded");
1753 uasm_resolve_relocs(relocs, labels);
1754 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1755 (unsigned int)(p - handle_tlbs));
1757 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
1760 static void __cpuinit build_r3000_tlb_modify_handler(void)
1762 u32 *p = handle_tlbm;
1763 struct uasm_label *l = labels;
1764 struct uasm_reloc *r = relocs;
1766 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1767 memset(labels, 0, sizeof(labels));
1768 memset(relocs, 0, sizeof(relocs));
1770 build_r3000_tlbchange_handler_head(&p, K0, K1);
1771 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
1772 uasm_i_nop(&p); /* load delay */
1773 build_make_write(&p, &r, K0, K1);
1774 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1776 uasm_l_nopage_tlbm(&l, p);
1777 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1780 if ((p - handle_tlbm) > FASTPATH_SIZE)
1781 panic("TLB modify handler fastpath space exceeded");
1783 uasm_resolve_relocs(relocs, labels);
1784 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1785 (unsigned int)(p - handle_tlbm));
1787 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
1789 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1792 * R4000 style TLB load/store/modify handlers.
1794 static struct work_registers __cpuinit
1795 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1796 struct uasm_reloc **r)
1798 struct work_registers wr = build_get_work_registers(p);
1801 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
1803 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
1806 #ifdef CONFIG_HUGETLB_PAGE
1808 * For huge tlb entries, pmd doesn't contain an address but
1809 * instead contains the tlb pte. Check the PAGE_HUGE bit and
1810 * see if we need to jump to huge tlb processing.
1812 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
1815 UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
1816 UASM_i_LW(p, wr.r2, 0, wr.r2);
1817 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1818 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1819 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
1822 uasm_l_smp_pgtable_change(l, *p);
1824 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
1825 if (!m4kc_tlbp_war())
1826 build_tlb_probe_entry(p);
1830 static void __cpuinit
1831 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1832 struct uasm_reloc **r, unsigned int tmp,
1835 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
1836 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
1837 build_update_entries(p, tmp, ptr);
1838 build_tlb_write_entry(p, l, r, tlb_indexed);
1839 uasm_l_leave(l, *p);
1840 build_restore_work_registers(p);
1841 uasm_i_eret(p); /* return from trap */
1844 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
1848 static void __cpuinit build_r4000_tlb_load_handler(void)
1850 u32 *p = handle_tlbl;
1851 struct uasm_label *l = labels;
1852 struct uasm_reloc *r = relocs;
1853 struct work_registers wr;
1855 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1856 memset(labels, 0, sizeof(labels));
1857 memset(relocs, 0, sizeof(relocs));
1859 if (bcm1250_m3_war()) {
1860 unsigned int segbits = 44;
1862 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1863 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1864 uasm_i_xor(&p, K0, K0, K1);
1865 uasm_i_dsrl_safe(&p, K1, K0, 62);
1866 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1867 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1868 uasm_i_or(&p, K0, K0, K1);
1869 uasm_il_bnez(&p, &r, K0, label_leave);
1870 /* No need for uasm_i_nop */
1873 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
1874 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
1875 if (m4kc_tlbp_war())
1876 build_tlb_probe_entry(&p);
1878 if (kernel_uses_smartmips_rixi) {
1880 * If the page is not _PAGE_VALID, RI or XI could not
1881 * have triggered it. Skip the expensive test..
1883 if (use_bbit_insns()) {
1884 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
1885 label_tlbl_goaround1);
1887 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
1888 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
1893 /* Examine entrylo 0 or 1 based on ptr. */
1894 if (use_bbit_insns()) {
1895 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
1897 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
1898 uasm_i_beqz(&p, wr.r3, 8);
1900 /* load it in the delay slot*/
1901 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
1902 /* load it if ptr is odd */
1903 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
1905 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
1906 * XI must have triggered it.
1908 if (use_bbit_insns()) {
1909 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
1911 uasm_l_tlbl_goaround1(&l, p);
1913 uasm_i_andi(&p, wr.r3, wr.r3, 2);
1914 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
1917 uasm_l_tlbl_goaround1(&l, p);
1919 build_make_valid(&p, &r, wr.r1, wr.r2);
1920 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
1922 #ifdef CONFIG_HUGETLB_PAGE
1924 * This is the entry point when build_r4000_tlbchange_handler_head
1925 * spots a huge page.
1927 uasm_l_tlb_huge_update(&l, p);
1928 iPTE_LW(&p, wr.r1, wr.r2);
1929 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
1930 build_tlb_probe_entry(&p);
1932 if (kernel_uses_smartmips_rixi) {
1934 * If the page is not _PAGE_VALID, RI or XI could not
1935 * have triggered it. Skip the expensive test..
1937 if (use_bbit_insns()) {
1938 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
1939 label_tlbl_goaround2);
1941 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
1942 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
1947 /* Examine entrylo 0 or 1 based on ptr. */
1948 if (use_bbit_insns()) {
1949 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
1951 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
1952 uasm_i_beqz(&p, wr.r3, 8);
1954 /* load it in the delay slot*/
1955 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
1956 /* load it if ptr is odd */
1957 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
1959 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
1960 * XI must have triggered it.
1962 if (use_bbit_insns()) {
1963 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
1965 uasm_i_andi(&p, wr.r3, wr.r3, 2);
1966 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
1968 if (PM_DEFAULT_MASK == 0)
1971 * We clobbered C0_PAGEMASK, restore it. On the other branch
1972 * it is restored in build_huge_tlb_write_entry.
1974 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
1976 uasm_l_tlbl_goaround2(&l, p);
1978 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
1979 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
1982 uasm_l_nopage_tlbl(&l, p);
1983 build_restore_work_registers(&p);
1984 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1987 if ((p - handle_tlbl) > FASTPATH_SIZE)
1988 panic("TLB load handler fastpath space exceeded");
1990 uasm_resolve_relocs(relocs, labels);
1991 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1992 (unsigned int)(p - handle_tlbl));
1994 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
1997 static void __cpuinit build_r4000_tlb_store_handler(void)
1999 u32 *p = handle_tlbs;
2000 struct uasm_label *l = labels;
2001 struct uasm_reloc *r = relocs;
2002 struct work_registers wr;
2004 memset(handle_tlbs, 0, sizeof(handle_tlbs));
2005 memset(labels, 0, sizeof(labels));
2006 memset(relocs, 0, sizeof(relocs));
2008 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2009 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2010 if (m4kc_tlbp_war())
2011 build_tlb_probe_entry(&p);
2012 build_make_write(&p, &r, wr.r1, wr.r2);
2013 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2015 #ifdef CONFIG_HUGETLB_PAGE
2017 * This is the entry point when
2018 * build_r4000_tlbchange_handler_head spots a huge page.
2020 uasm_l_tlb_huge_update(&l, p);
2021 iPTE_LW(&p, wr.r1, wr.r2);
2022 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2023 build_tlb_probe_entry(&p);
2024 uasm_i_ori(&p, wr.r1, wr.r1,
2025 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2026 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2029 uasm_l_nopage_tlbs(&l, p);
2030 build_restore_work_registers(&p);
2031 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2034 if ((p - handle_tlbs) > FASTPATH_SIZE)
2035 panic("TLB store handler fastpath space exceeded");
2037 uasm_resolve_relocs(relocs, labels);
2038 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2039 (unsigned int)(p - handle_tlbs));
2041 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
2044 static void __cpuinit build_r4000_tlb_modify_handler(void)
2046 u32 *p = handle_tlbm;
2047 struct uasm_label *l = labels;
2048 struct uasm_reloc *r = relocs;
2049 struct work_registers wr;
2051 memset(handle_tlbm, 0, sizeof(handle_tlbm));
2052 memset(labels, 0, sizeof(labels));
2053 memset(relocs, 0, sizeof(relocs));
2055 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2056 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2057 if (m4kc_tlbp_war())
2058 build_tlb_probe_entry(&p);
2059 /* Present and writable bits set, set accessed and dirty bits. */
2060 build_make_write(&p, &r, wr.r1, wr.r2);
2061 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2063 #ifdef CONFIG_HUGETLB_PAGE
2065 * This is the entry point when
2066 * build_r4000_tlbchange_handler_head spots a huge page.
2068 uasm_l_tlb_huge_update(&l, p);
2069 iPTE_LW(&p, wr.r1, wr.r2);
2070 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2071 build_tlb_probe_entry(&p);
2072 uasm_i_ori(&p, wr.r1, wr.r1,
2073 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2074 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2077 uasm_l_nopage_tlbm(&l, p);
2078 build_restore_work_registers(&p);
2079 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2082 if ((p - handle_tlbm) > FASTPATH_SIZE)
2083 panic("TLB modify handler fastpath space exceeded");
2085 uasm_resolve_relocs(relocs, labels);
2086 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2087 (unsigned int)(p - handle_tlbm));
2089 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
2092 void __cpuinit build_tlb_refill_handler(void)
2095 * The refill handler is generated per-CPU, multi-node systems
2096 * may have local storage for it. The other handlers are only
2099 static int run_once = 0;
2102 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2105 switch (current_cpu_type()) {
2113 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2114 build_r3000_tlb_refill_handler();
2116 build_r3000_tlb_load_handler();
2117 build_r3000_tlb_store_handler();
2118 build_r3000_tlb_modify_handler();
2122 panic("No R3000 TLB refill handler");
2128 panic("No R6000 TLB refill handler yet");
2132 panic("No R8000 TLB refill handler yet");
2137 scratch_reg = allocate_kscratch();
2138 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2139 build_r4000_setup_pgd();
2141 build_r4000_tlb_load_handler();
2142 build_r4000_tlb_store_handler();
2143 build_r4000_tlb_modify_handler();
2146 build_r4000_tlb_refill_handler();
2150 void __cpuinit flush_tlb_handlers(void)
2152 local_flush_icache_range((unsigned long)handle_tlbl,
2153 (unsigned long)handle_tlbl + sizeof(handle_tlbl));
2154 local_flush_icache_range((unsigned long)handle_tlbs,
2155 (unsigned long)handle_tlbs + sizeof(handle_tlbs));
2156 local_flush_icache_range((unsigned long)handle_tlbm,
2157 (unsigned long)handle_tlbm + sizeof(handle_tlbm));
2158 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2159 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2160 (unsigned long)tlbmiss_handler_setup_pgd + sizeof(handle_tlbm));