2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2005-2007 Cavium Networks
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/smp.h>
13 #include <linux/bitops.h>
14 #include <linux/cpu.h>
17 #include <asm/bcache.h>
18 #include <asm/bootinfo.h>
19 #include <asm/cacheops.h>
20 #include <asm/cpu-features.h>
22 #include <asm/pgtable.h>
23 #include <asm/r4kcache.h>
24 #include <asm/mmu_context.h>
27 #include <asm/octeon/octeon.h>
29 unsigned long long cache_err_dcache[NR_CPUS];
32 * Octeon automatically flushes the dcache on tlb changes, so
33 * from Linux's viewpoint it acts much like a physically
34 * tagged cache. No flushing is needed
37 static void octeon_flush_data_cache_page(unsigned long addr)
42 static inline void octeon_local_flush_icache(void)
44 asm volatile ("synci 0($0)");
48 * Flush local I-cache for the specified range.
50 static void local_octeon_flush_icache_range(unsigned long start,
53 octeon_local_flush_icache();
57 * Flush caches as necessary for all cores affected by a
58 * vma. If no vma is supplied, all cores are flushed.
60 * @vma: VMA to flush or NULL to flush all icaches.
62 static void octeon_flush_icache_all_cores(struct vm_area_struct *vma)
64 extern void octeon_send_ipi_single(int cpu, unsigned int action);
71 octeon_local_flush_icache();
74 cpu = smp_processor_id();
77 * If we have a vma structure, we only need to worry about
78 * cores it has been used on
81 mask = *mm_cpumask(vma->vm_mm);
83 mask = *cpu_online_mask;
84 cpumask_clear_cpu(cpu, &mask);
85 for_each_cpu(cpu, &mask)
86 octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH);
94 * Called to flush the icache on all cores
96 static void octeon_flush_icache_all(void)
98 octeon_flush_icache_all_cores(NULL);
103 * Called to flush all memory associated with a memory
106 * @mm: Memory context to flush
108 static void octeon_flush_cache_mm(struct mm_struct *mm)
111 * According to the R4K version of this file, CPUs without
112 * dcache aliases don't need to do anything here
118 * Flush a range of kernel addresses out of the icache
121 static void octeon_flush_icache_range(unsigned long start, unsigned long end)
123 octeon_flush_icache_all_cores(NULL);
128 * Flush the icache for a trampoline. These are used for interrupt
129 * and exception hooking.
131 * @addr: Address to flush
133 static void octeon_flush_cache_sigtramp(unsigned long addr)
135 struct vm_area_struct *vma;
137 vma = find_vma(current->mm, addr);
138 octeon_flush_icache_all_cores(vma);
143 * Flush a range out of a vma
149 static void octeon_flush_cache_range(struct vm_area_struct *vma,
150 unsigned long start, unsigned long end)
152 if (vma->vm_flags & VM_EXEC)
153 octeon_flush_icache_all_cores(vma);
158 * Flush a specific page of a vma
160 * @vma: VMA to flush page for
161 * @page: Page to flush
164 static void octeon_flush_cache_page(struct vm_area_struct *vma,
165 unsigned long page, unsigned long pfn)
167 if (vma->vm_flags & VM_EXEC)
168 octeon_flush_icache_all_cores(vma);
171 static void octeon_flush_kernel_vmap_range(unsigned long vaddr, int size)
177 * Probe Octeon's caches
180 static void __cpuinit probe_octeon(void)
182 unsigned long icache_size;
183 unsigned long dcache_size;
184 unsigned int config1;
185 struct cpuinfo_mips *c = ¤t_cpu_data;
187 config1 = read_c0_config1();
188 switch (c->cputype) {
189 case CPU_CAVIUM_OCTEON:
190 case CPU_CAVIUM_OCTEON_PLUS:
191 c->icache.linesz = 2 << ((config1 >> 19) & 7);
192 c->icache.sets = 64 << ((config1 >> 22) & 7);
193 c->icache.ways = 1 + ((config1 >> 16) & 7);
194 c->icache.flags |= MIPS_CACHE_VTAG;
196 c->icache.sets * c->icache.ways * c->icache.linesz;
197 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
198 c->dcache.linesz = 128;
199 if (c->cputype == CPU_CAVIUM_OCTEON_PLUS)
200 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
202 c->dcache.sets = 1; /* CN3XXX has one Dcache set */
205 c->dcache.sets * c->dcache.ways * c->dcache.linesz;
206 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
207 c->options |= MIPS_CPU_PREFETCH;
210 case CPU_CAVIUM_OCTEON2:
211 c->icache.linesz = 2 << ((config1 >> 19) & 7);
214 c->icache.flags |= MIPS_CACHE_VTAG;
215 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
217 c->dcache.linesz = 128;
220 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
221 c->options |= MIPS_CPU_PREFETCH;
225 panic("Unsupported Cavium Networks CPU type");
229 /* compute a couple of other cache variables */
230 c->icache.waysize = icache_size / c->icache.ways;
231 c->dcache.waysize = dcache_size / c->dcache.ways;
233 c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
234 c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
236 if (smp_processor_id() == 0) {
237 pr_notice("Primary instruction cache %ldkB, %s, %d way, "
238 "%d sets, linesize %d bytes.\n",
240 cpu_has_vtag_icache ?
241 "virtually tagged" : "physically tagged",
242 c->icache.ways, c->icache.sets, c->icache.linesz);
244 pr_notice("Primary data cache %ldkB, %d-way, %d sets, "
245 "linesize %d bytes.\n",
246 dcache_size >> 10, c->dcache.ways,
247 c->dcache.sets, c->dcache.linesz);
253 * Setup the Octeon cache flush routines
256 void __cpuinit octeon_cache_init(void)
258 extern unsigned long ebase;
259 extern char except_vec2_octeon;
261 memcpy((void *)(ebase + 0x100), &except_vec2_octeon, 0x80);
262 octeon_flush_cache_sigtramp(ebase + 0x100);
266 shm_align_mask = PAGE_SIZE - 1;
268 flush_cache_all = octeon_flush_icache_all;
269 __flush_cache_all = octeon_flush_icache_all;
270 flush_cache_mm = octeon_flush_cache_mm;
271 flush_cache_page = octeon_flush_cache_page;
272 flush_cache_range = octeon_flush_cache_range;
273 flush_cache_sigtramp = octeon_flush_cache_sigtramp;
274 flush_icache_all = octeon_flush_icache_all;
275 flush_data_cache_page = octeon_flush_data_cache_page;
276 flush_icache_range = octeon_flush_icache_range;
277 local_flush_icache_range = local_octeon_flush_icache_range;
279 __flush_kernel_vmap_range = octeon_flush_kernel_vmap_range;
286 * Handle a cache error exception
289 static void cache_parity_error_octeon(int non_recoverable)
291 unsigned long coreid = cvmx_get_core_num();
292 uint64_t icache_err = read_octeon_c0_icacheerr();
294 pr_err("Cache error exception:\n");
295 pr_err("cp0_errorepc == %lx\n", read_c0_errorepc());
296 if (icache_err & 1) {
297 pr_err("CacheErr (Icache) == %llx\n",
298 (unsigned long long)icache_err);
299 write_octeon_c0_icacheerr(0);
301 if (cache_err_dcache[coreid] & 1) {
302 pr_err("CacheErr (Dcache) == %llx\n",
303 (unsigned long long)cache_err_dcache[coreid]);
304 cache_err_dcache[coreid] = 0;
308 panic("Can't handle cache error: nested exception");
312 * Called when the the exception is recoverable
315 asmlinkage void cache_parity_error_octeon_recoverable(void)
317 cache_parity_error_octeon(0);
321 * Called when the the exception is not recoverable
324 asmlinkage void cache_parity_error_octeon_non_recoverable(void)
326 cache_parity_error_octeon(1);