2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
42 #include <asm/branch.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
48 #include <asm/processor.h>
49 #include <asm/fpu_emulator.h>
54 /* Function which emulates a floating point instruction. */
56 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
59 static int fpux_emu(struct pt_regs *,
60 struct mips_fpu_struct *, mips_instruction, void *__user *);
62 /* Control registers */
64 #define FPCREG_RID 0 /* $0 = revision id */
65 #define FPCREG_CSR 31 /* $31 = csr */
67 /* Determine rounding mode from the RM bits of the FCSR */
68 #define modeindex(v) ((v) & FPU_CSR_RM)
70 /* convert condition code register number to csr bit */
71 static const unsigned int fpucondbit[8] = {
82 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
83 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
84 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
85 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
86 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
89 * This functions translates a 32-bit microMIPS instruction
90 * into a 32-bit MIPS32 instruction. Returns 0 on success
91 * and SIGILL otherwise.
93 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
95 union mips_instruction insn = *insn_ptr;
96 union mips_instruction mips32_insn = insn;
99 switch (insn.mm_i_format.opcode) {
101 mips32_insn.mm_i_format.opcode = ldc1_op;
102 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
103 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
106 mips32_insn.mm_i_format.opcode = lwc1_op;
107 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
108 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
111 mips32_insn.mm_i_format.opcode = sdc1_op;
112 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
113 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
116 mips32_insn.mm_i_format.opcode = swc1_op;
117 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
118 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
121 /* NOTE: offset is << by 1 if in microMIPS mode. */
122 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
123 (insn.mm_i_format.rt == mm_bc1t_op)) {
124 mips32_insn.fb_format.opcode = cop1_op;
125 mips32_insn.fb_format.bc = bc_op;
126 mips32_insn.fb_format.flag =
127 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
132 switch (insn.mm_fp0_format.func) {
141 op = insn.mm_fp0_format.func;
142 if (op == mm_32f_01_op)
144 else if (op == mm_32f_11_op)
146 else if (op == mm_32f_02_op)
148 else if (op == mm_32f_12_op)
150 else if (op == mm_32f_41_op)
152 else if (op == mm_32f_51_op)
154 else if (op == mm_32f_42_op)
158 mips32_insn.fp6_format.opcode = cop1x_op;
159 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
160 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
161 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
162 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
163 mips32_insn.fp6_format.func = func;
166 func = -1; /* Invalid */
167 op = insn.mm_fp5_format.op & 0x7;
168 if (op == mm_ldxc1_op)
170 else if (op == mm_sdxc1_op)
172 else if (op == mm_lwxc1_op)
174 else if (op == mm_swxc1_op)
178 mips32_insn.r_format.opcode = cop1x_op;
179 mips32_insn.r_format.rs =
180 insn.mm_fp5_format.base;
181 mips32_insn.r_format.rt =
182 insn.mm_fp5_format.index;
183 mips32_insn.r_format.rd = 0;
184 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
185 mips32_insn.r_format.func = func;
190 op = -1; /* Invalid */
191 if (insn.mm_fp2_format.op == mm_fmovt_op)
193 else if (insn.mm_fp2_format.op == mm_fmovf_op)
196 mips32_insn.fp0_format.opcode = cop1_op;
197 mips32_insn.fp0_format.fmt =
198 sdps_format[insn.mm_fp2_format.fmt];
199 mips32_insn.fp0_format.ft =
200 (insn.mm_fp2_format.cc<<2) + op;
201 mips32_insn.fp0_format.fs =
202 insn.mm_fp2_format.fs;
203 mips32_insn.fp0_format.fd =
204 insn.mm_fp2_format.fd;
205 mips32_insn.fp0_format.func = fmovc_op;
210 func = -1; /* Invalid */
211 if (insn.mm_fp0_format.op == mm_fadd_op)
213 else if (insn.mm_fp0_format.op == mm_fsub_op)
215 else if (insn.mm_fp0_format.op == mm_fmul_op)
217 else if (insn.mm_fp0_format.op == mm_fdiv_op)
220 mips32_insn.fp0_format.opcode = cop1_op;
221 mips32_insn.fp0_format.fmt =
222 sdps_format[insn.mm_fp0_format.fmt];
223 mips32_insn.fp0_format.ft =
224 insn.mm_fp0_format.ft;
225 mips32_insn.fp0_format.fs =
226 insn.mm_fp0_format.fs;
227 mips32_insn.fp0_format.fd =
228 insn.mm_fp0_format.fd;
229 mips32_insn.fp0_format.func = func;
234 func = -1; /* Invalid */
235 if (insn.mm_fp0_format.op == mm_fmovn_op)
237 else if (insn.mm_fp0_format.op == mm_fmovz_op)
240 mips32_insn.fp0_format.opcode = cop1_op;
241 mips32_insn.fp0_format.fmt =
242 sdps_format[insn.mm_fp0_format.fmt];
243 mips32_insn.fp0_format.ft =
244 insn.mm_fp0_format.ft;
245 mips32_insn.fp0_format.fs =
246 insn.mm_fp0_format.fs;
247 mips32_insn.fp0_format.fd =
248 insn.mm_fp0_format.fd;
249 mips32_insn.fp0_format.func = func;
253 case mm_32f_73_op: /* POOL32FXF */
254 switch (insn.mm_fp1_format.op) {
259 if ((insn.mm_fp1_format.op & 0x7f) ==
264 mips32_insn.r_format.opcode = spec_op;
265 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
266 mips32_insn.r_format.rt =
267 (insn.mm_fp4_format.cc << 2) + op;
268 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
269 mips32_insn.r_format.re = 0;
270 mips32_insn.r_format.func = movc_op;
276 if ((insn.mm_fp1_format.op & 0x7f) ==
279 fmt = swl_format[insn.mm_fp3_format.fmt];
282 fmt = dwl_format[insn.mm_fp3_format.fmt];
284 mips32_insn.fp0_format.opcode = cop1_op;
285 mips32_insn.fp0_format.fmt = fmt;
286 mips32_insn.fp0_format.ft = 0;
287 mips32_insn.fp0_format.fs =
288 insn.mm_fp3_format.fs;
289 mips32_insn.fp0_format.fd =
290 insn.mm_fp3_format.rt;
291 mips32_insn.fp0_format.func = func;
299 if ((insn.mm_fp1_format.op & 0x7f) ==
302 else if ((insn.mm_fp1_format.op & 0x7f) ==
307 mips32_insn.fp0_format.opcode = cop1_op;
308 mips32_insn.fp0_format.fmt =
309 sdps_format[insn.mm_fp3_format.fmt];
310 mips32_insn.fp0_format.ft = 0;
311 mips32_insn.fp0_format.fs =
312 insn.mm_fp3_format.fs;
313 mips32_insn.fp0_format.fd =
314 insn.mm_fp3_format.rt;
315 mips32_insn.fp0_format.func = func;
327 if (insn.mm_fp1_format.op == mm_ffloorl_op)
329 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
331 else if (insn.mm_fp1_format.op == mm_fceill_op)
333 else if (insn.mm_fp1_format.op == mm_fceilw_op)
335 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
337 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
339 else if (insn.mm_fp1_format.op == mm_froundl_op)
341 else if (insn.mm_fp1_format.op == mm_froundw_op)
343 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
347 mips32_insn.fp0_format.opcode = cop1_op;
348 mips32_insn.fp0_format.fmt =
349 sd_format[insn.mm_fp1_format.fmt];
350 mips32_insn.fp0_format.ft = 0;
351 mips32_insn.fp0_format.fs =
352 insn.mm_fp1_format.fs;
353 mips32_insn.fp0_format.fd =
354 insn.mm_fp1_format.rt;
355 mips32_insn.fp0_format.func = func;
360 if (insn.mm_fp1_format.op == mm_frsqrt_op)
362 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
366 mips32_insn.fp0_format.opcode = cop1_op;
367 mips32_insn.fp0_format.fmt =
368 sdps_format[insn.mm_fp1_format.fmt];
369 mips32_insn.fp0_format.ft = 0;
370 mips32_insn.fp0_format.fs =
371 insn.mm_fp1_format.fs;
372 mips32_insn.fp0_format.fd =
373 insn.mm_fp1_format.rt;
374 mips32_insn.fp0_format.func = func;
382 if (insn.mm_fp1_format.op == mm_mfc1_op)
384 else if (insn.mm_fp1_format.op == mm_mtc1_op)
386 else if (insn.mm_fp1_format.op == mm_cfc1_op)
388 else if (insn.mm_fp1_format.op == mm_ctc1_op)
390 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
394 mips32_insn.fp1_format.opcode = cop1_op;
395 mips32_insn.fp1_format.op = op;
396 mips32_insn.fp1_format.rt =
397 insn.mm_fp1_format.rt;
398 mips32_insn.fp1_format.fs =
399 insn.mm_fp1_format.fs;
400 mips32_insn.fp1_format.fd = 0;
401 mips32_insn.fp1_format.func = 0;
407 case mm_32f_74_op: /* c.cond.fmt */
408 mips32_insn.fp0_format.opcode = cop1_op;
409 mips32_insn.fp0_format.fmt =
410 sdps_format[insn.mm_fp4_format.fmt];
411 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
412 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
413 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
414 mips32_insn.fp0_format.func =
415 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
425 *insn_ptr = mips32_insn;
430 * Redundant with logic already in kernel/branch.c,
431 * embedded in compute_return_epc. At some point,
432 * a single subroutine should be used across both
435 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
436 unsigned long *contpc)
438 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
440 unsigned int bit = 0;
442 switch (insn.i_format.opcode) {
444 switch (insn.r_format.func) {
446 regs->regs[insn.r_format.rd] =
447 regs->cp0_epc + dec_insn.pc_inc +
448 dec_insn.next_pc_inc;
451 /* For R6, JR already emulated in jalr_op */
452 if (NO_R6EMU && insn.r_format.opcode == jr_op)
454 *contpc = regs->regs[insn.r_format.rs];
459 switch (insn.i_format.rt) {
462 if (NO_R6EMU && (insn.i_format.rs ||
463 insn.i_format.rt == bltzall_op))
466 regs->regs[31] = regs->cp0_epc +
468 dec_insn.next_pc_inc;
474 if ((long)regs->regs[insn.i_format.rs] < 0)
475 *contpc = regs->cp0_epc +
477 (insn.i_format.simmediate << 2);
479 *contpc = regs->cp0_epc +
481 dec_insn.next_pc_inc;
485 if (NO_R6EMU && (insn.i_format.rs ||
486 insn.i_format.rt == bgezall_op))
489 regs->regs[31] = regs->cp0_epc +
491 dec_insn.next_pc_inc;
497 if ((long)regs->regs[insn.i_format.rs] >= 0)
498 *contpc = regs->cp0_epc +
500 (insn.i_format.simmediate << 2);
502 *contpc = regs->cp0_epc +
504 dec_insn.next_pc_inc;
511 regs->regs[31] = regs->cp0_epc +
513 dec_insn.next_pc_inc;
516 *contpc = regs->cp0_epc + dec_insn.pc_inc;
519 *contpc |= (insn.j_format.target << 2);
520 /* Set microMIPS mode bit: XOR for jalx. */
527 if (regs->regs[insn.i_format.rs] ==
528 regs->regs[insn.i_format.rt])
529 *contpc = regs->cp0_epc +
531 (insn.i_format.simmediate << 2);
533 *contpc = regs->cp0_epc +
535 dec_insn.next_pc_inc;
541 if (regs->regs[insn.i_format.rs] !=
542 regs->regs[insn.i_format.rt])
543 *contpc = regs->cp0_epc +
545 (insn.i_format.simmediate << 2);
547 *contpc = regs->cp0_epc +
549 dec_insn.next_pc_inc;
555 if ((long)regs->regs[insn.i_format.rs] <= 0)
556 *contpc = regs->cp0_epc +
558 (insn.i_format.simmediate << 2);
560 *contpc = regs->cp0_epc +
562 dec_insn.next_pc_inc;
568 if ((long)regs->regs[insn.i_format.rs] > 0)
569 *contpc = regs->cp0_epc +
571 (insn.i_format.simmediate << 2);
573 *contpc = regs->cp0_epc +
575 dec_insn.next_pc_inc;
577 #ifdef CONFIG_CPU_CAVIUM_OCTEON
578 case lwc2_op: /* This is bbit0 on Octeon */
579 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
580 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
582 *contpc = regs->cp0_epc + 8;
584 case ldc2_op: /* This is bbit032 on Octeon */
585 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
586 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
588 *contpc = regs->cp0_epc + 8;
590 case swc2_op: /* This is bbit1 on Octeon */
591 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
592 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
594 *contpc = regs->cp0_epc + 8;
596 case sdc2_op: /* This is bbit132 on Octeon */
597 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
598 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
600 *contpc = regs->cp0_epc + 8;
607 if (insn.i_format.rs == bc_op) {
610 fcr31 = read_32bit_cp1_register(CP1_STATUS);
612 fcr31 = current->thread.fpu.fcr31;
615 bit = (insn.i_format.rt >> 2);
618 switch (insn.i_format.rt & 3) {
621 if (~fcr31 & (1 << bit))
622 *contpc = regs->cp0_epc +
624 (insn.i_format.simmediate << 2);
626 *contpc = regs->cp0_epc +
628 dec_insn.next_pc_inc;
632 if (fcr31 & (1 << bit))
633 *contpc = regs->cp0_epc +
635 (insn.i_format.simmediate << 2);
637 *contpc = regs->cp0_epc +
639 dec_insn.next_pc_inc;
649 * In the Linux kernel, we support selection of FPR format on the
650 * basis of the Status.FR bit. If an FPU is not present, the FR bit
651 * is hardwired to zero, which would imply a 32-bit FPU even for
652 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
653 * FPU emu is slow and bulky and optimizing this function offers fairly
654 * sizeable benefits so we try to be clever and make this function return
655 * a constant whenever possible, that is on 64-bit kernels without O32
656 * compatibility enabled and on 32-bit without 64-bit FPU support.
658 static inline int cop1_64bit(struct pt_regs *xcp)
660 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
662 else if (config_enabled(CONFIG_32BIT) &&
663 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
666 return !test_thread_flag(TIF_32BIT_FPREGS);
669 static inline bool hybrid_fprs(void)
671 return test_thread_flag(TIF_HYBRID_FPREGS);
674 #define SIFROMREG(si, x) \
676 if (cop1_64bit(xcp) && !hybrid_fprs()) \
677 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
679 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
682 #define SITOREG(si, x) \
684 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
686 set_fpr32(&ctx->fpr[x], 0, si); \
687 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
688 set_fpr32(&ctx->fpr[x], i, 0); \
690 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
694 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
696 #define SITOHREG(si, x) \
699 set_fpr32(&ctx->fpr[x], 1, si); \
700 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
701 set_fpr32(&ctx->fpr[x], i, 0); \
704 #define DIFROMREG(di, x) \
705 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
707 #define DITOREG(di, x) \
710 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
711 set_fpr64(&ctx->fpr[fpr], 0, di); \
712 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
713 set_fpr64(&ctx->fpr[fpr], i, 0); \
716 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
717 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
718 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
719 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
722 * Emulate the single floating point instruction pointed at by EPC.
723 * Two instructions if the instruction is in a branch delay slot.
726 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
727 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
729 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
730 unsigned int cond, cbit;
741 * These are giving gcc a gentle hint about what to expect in
742 * dec_inst in order to do better optimization.
744 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
747 /* XXX NEC Vr54xx bug workaround */
748 if (delay_slot(xcp)) {
749 if (dec_insn.micro_mips_mode) {
750 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
751 clear_delay_slot(xcp);
753 if (!isBranchInstr(xcp, dec_insn, &contpc))
754 clear_delay_slot(xcp);
758 if (delay_slot(xcp)) {
760 * The instruction to be emulated is in a branch delay slot
761 * which means that we have to emulate the branch instruction
762 * BEFORE we do the cop1 instruction.
764 * This branch could be a COP1 branch, but in that case we
765 * would have had a trap for that instruction, and would not
766 * come through this route.
768 * Linux MIPS branch emulator operates on context, updating the
771 ir = dec_insn.next_insn; /* process delay slot instr */
772 pc_inc = dec_insn.next_pc_inc;
774 ir = dec_insn.insn; /* process current instr */
775 pc_inc = dec_insn.pc_inc;
779 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
780 * instructions, we want to convert microMIPS FPU instructions
781 * into MIPS32 instructions so that we could reuse all of the
782 * FPU emulation code.
784 * NOTE: We cannot do this for branch instructions since they
785 * are not a subset. Example: Cannot emulate a 16-bit
786 * aligned target address with a MIPS32 instruction.
788 if (dec_insn.micro_mips_mode) {
790 * If next instruction is a 16-bit instruction, then it
791 * it cannot be a FPU instruction. This could happen
792 * since we can be called for non-FPU instructions.
795 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
801 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
802 MIPS_FPU_EMU_INC_STATS(emulated);
803 switch (MIPSInst_OPCODE(ir)) {
805 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
807 MIPS_FPU_EMU_INC_STATS(loads);
809 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
810 MIPS_FPU_EMU_INC_STATS(errors);
814 if (__get_user(dval, dva)) {
815 MIPS_FPU_EMU_INC_STATS(errors);
819 DITOREG(dval, MIPSInst_RT(ir));
823 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
825 MIPS_FPU_EMU_INC_STATS(stores);
826 DIFROMREG(dval, MIPSInst_RT(ir));
827 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
828 MIPS_FPU_EMU_INC_STATS(errors);
832 if (__put_user(dval, dva)) {
833 MIPS_FPU_EMU_INC_STATS(errors);
840 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
842 MIPS_FPU_EMU_INC_STATS(loads);
843 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
844 MIPS_FPU_EMU_INC_STATS(errors);
848 if (__get_user(wval, wva)) {
849 MIPS_FPU_EMU_INC_STATS(errors);
853 SITOREG(wval, MIPSInst_RT(ir));
857 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
859 MIPS_FPU_EMU_INC_STATS(stores);
860 SIFROMREG(wval, MIPSInst_RT(ir));
861 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
862 MIPS_FPU_EMU_INC_STATS(errors);
866 if (__put_user(wval, wva)) {
867 MIPS_FPU_EMU_INC_STATS(errors);
874 switch (MIPSInst_RS(ir)) {
876 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
879 /* copregister fs -> gpr[rt] */
880 if (MIPSInst_RT(ir) != 0) {
881 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
887 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
890 /* copregister fs <- rt */
891 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
895 if (!cpu_has_mips_r2)
898 /* copregister rd -> gpr[rt] */
899 if (MIPSInst_RT(ir) != 0) {
900 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
906 if (!cpu_has_mips_r2)
909 /* copregister rd <- gpr[rt] */
910 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
914 /* copregister rd -> gpr[rt] */
915 if (MIPSInst_RT(ir) != 0) {
916 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
922 /* copregister rd <- rt */
923 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
927 /* cop control register rd -> gpr[rt] */
928 if (MIPSInst_RD(ir) == FPCREG_CSR) {
930 value = (value & ~FPU_CSR_RM) | modeindex(value);
931 pr_debug("%p gpr[%d]<-csr=%08x\n",
932 (void *) (xcp->cp0_epc),
933 MIPSInst_RT(ir), value);
935 else if (MIPSInst_RD(ir) == FPCREG_RID)
940 xcp->regs[MIPSInst_RT(ir)] = value;
944 /* copregister rd <- rt */
945 if (MIPSInst_RT(ir) == 0)
948 value = xcp->regs[MIPSInst_RT(ir)];
950 /* we only have one writable control reg
952 if (MIPSInst_RD(ir) == FPCREG_CSR) {
953 pr_debug("%p gpr[%d]->csr=%08x\n",
954 (void *) (xcp->cp0_epc),
955 MIPSInst_RT(ir), value);
958 * Don't write reserved bits,
959 * and convert to ieee library modes
961 ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
964 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
973 if (cpu_has_mips_4_5_r)
974 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
977 cond = ctx->fcr31 & cbit;
980 switch (MIPSInst_RT(ir) & 3) {
991 /* thats an illegal instruction */
998 * Branch taken: emulate dslot instruction
1000 xcp->cp0_epc += dec_insn.pc_inc;
1002 contpc = MIPSInst_SIMM(ir);
1003 ir = dec_insn.next_insn;
1004 if (dec_insn.micro_mips_mode) {
1005 contpc = (xcp->cp0_epc + (contpc << 1));
1007 /* If 16-bit instruction, not FPU. */
1008 if ((dec_insn.next_pc_inc == 2) ||
1009 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1012 * Since this instruction will
1013 * be put on the stack with
1014 * 32-bit words, get around
1015 * this problem by putting a
1016 * NOP16 as the second one.
1018 if (dec_insn.next_pc_inc == 2)
1019 ir = (ir & (~0xffff)) | MM_NOP16;
1022 * Single step the non-CP1
1023 * instruction in the dslot.
1025 return mips_dsemul(xcp, ir, contpc);
1028 contpc = (xcp->cp0_epc + (contpc << 2));
1030 switch (MIPSInst_OPCODE(ir)) {
1039 if (cpu_has_mips_2_3_4_5 ||
1050 if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2)
1051 /* its one of ours */
1057 if (!cpu_has_mips_4_5_r)
1060 if (MIPSInst_FUNC(ir) == movc_op)
1066 * Single step the non-cp1
1067 * instruction in the dslot
1069 return mips_dsemul(xcp, ir, contpc);
1070 } else if (likely) { /* branch not taken */
1072 * branch likely nullifies
1073 * dslot if not taken
1075 xcp->cp0_epc += dec_insn.pc_inc;
1076 contpc += dec_insn.pc_inc;
1078 * else continue & execute
1079 * dslot as normal insn
1085 if (!(MIPSInst_RS(ir) & 0x10))
1088 /* a real fpu computation instruction */
1089 if ((sig = fpu_emu(xcp, ctx, ir)))
1095 if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2)
1098 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1104 if (!cpu_has_mips_4_5_r)
1107 if (MIPSInst_FUNC(ir) != movc_op)
1109 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1110 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1111 xcp->regs[MIPSInst_RD(ir)] =
1112 xcp->regs[MIPSInst_RS(ir)];
1120 xcp->cp0_epc = contpc;
1121 clear_delay_slot(xcp);
1127 * Conversion table from MIPS compare ops 48-63
1128 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1130 static const unsigned char cmptab[8] = {
1131 0, /* cmp_0 (sig) cmp_sf */
1132 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1133 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1134 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1135 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1136 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1137 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1138 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1143 * Additional MIPS4 instructions
1146 #define DEF3OP(name, p, f1, f2, f3) \
1147 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1148 union ieee754##p s, union ieee754##p t) \
1150 struct _ieee754_csr ieee754_csr_save; \
1152 ieee754_csr_save = ieee754_csr; \
1154 ieee754_csr_save.cx |= ieee754_csr.cx; \
1155 ieee754_csr_save.sx |= ieee754_csr.sx; \
1157 ieee754_csr.cx |= ieee754_csr_save.cx; \
1158 ieee754_csr.sx |= ieee754_csr_save.sx; \
1162 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1164 return ieee754dp_div(ieee754dp_one(0), d);
1167 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1169 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1172 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1174 return ieee754sp_div(ieee754sp_one(0), s);
1177 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1179 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1182 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1183 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1184 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1185 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1186 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1187 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1188 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1189 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1191 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1192 mips_instruction ir, void *__user *fault_addr)
1194 unsigned rcsr = 0; /* resulting csr */
1196 MIPS_FPU_EMU_INC_STATS(cp1xops);
1198 switch (MIPSInst_FMA_FFMT(ir)) {
1199 case s_fmt:{ /* 0 */
1201 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1202 union ieee754sp fd, fr, fs, ft;
1206 switch (MIPSInst_FUNC(ir)) {
1208 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1209 xcp->regs[MIPSInst_FT(ir)]);
1211 MIPS_FPU_EMU_INC_STATS(loads);
1212 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1213 MIPS_FPU_EMU_INC_STATS(errors);
1217 if (__get_user(val, va)) {
1218 MIPS_FPU_EMU_INC_STATS(errors);
1222 SITOREG(val, MIPSInst_FD(ir));
1226 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1227 xcp->regs[MIPSInst_FT(ir)]);
1229 MIPS_FPU_EMU_INC_STATS(stores);
1231 SIFROMREG(val, MIPSInst_FS(ir));
1232 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1233 MIPS_FPU_EMU_INC_STATS(errors);
1237 if (put_user(val, va)) {
1238 MIPS_FPU_EMU_INC_STATS(errors);
1245 handler = fpemu_sp_madd;
1248 handler = fpemu_sp_msub;
1251 handler = fpemu_sp_nmadd;
1254 handler = fpemu_sp_nmsub;
1258 SPFROMREG(fr, MIPSInst_FR(ir));
1259 SPFROMREG(fs, MIPSInst_FS(ir));
1260 SPFROMREG(ft, MIPSInst_FT(ir));
1261 fd = (*handler) (fr, fs, ft);
1262 SPTOREG(fd, MIPSInst_FD(ir));
1265 if (ieee754_cxtest(IEEE754_INEXACT)) {
1266 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1267 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1269 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1270 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1271 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1273 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1274 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1275 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1277 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1278 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1279 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1282 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1283 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1284 /*printk ("SIGFPE: FPU csr = %08x\n",
1297 case d_fmt:{ /* 1 */
1298 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1299 union ieee754dp fd, fr, fs, ft;
1303 switch (MIPSInst_FUNC(ir)) {
1305 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1306 xcp->regs[MIPSInst_FT(ir)]);
1308 MIPS_FPU_EMU_INC_STATS(loads);
1309 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1310 MIPS_FPU_EMU_INC_STATS(errors);
1314 if (__get_user(val, va)) {
1315 MIPS_FPU_EMU_INC_STATS(errors);
1319 DITOREG(val, MIPSInst_FD(ir));
1323 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1324 xcp->regs[MIPSInst_FT(ir)]);
1326 MIPS_FPU_EMU_INC_STATS(stores);
1327 DIFROMREG(val, MIPSInst_FS(ir));
1328 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1329 MIPS_FPU_EMU_INC_STATS(errors);
1333 if (__put_user(val, va)) {
1334 MIPS_FPU_EMU_INC_STATS(errors);
1341 handler = fpemu_dp_madd;
1344 handler = fpemu_dp_msub;
1347 handler = fpemu_dp_nmadd;
1350 handler = fpemu_dp_nmsub;
1354 DPFROMREG(fr, MIPSInst_FR(ir));
1355 DPFROMREG(fs, MIPSInst_FS(ir));
1356 DPFROMREG(ft, MIPSInst_FT(ir));
1357 fd = (*handler) (fr, fs, ft);
1358 DPTOREG(fd, MIPSInst_FD(ir));
1368 if (MIPSInst_FUNC(ir) != pfetch_op)
1371 /* ignore prefx operation */
1384 * Emulate a single COP1 arithmetic instruction.
1386 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1387 mips_instruction ir)
1389 int rfmt; /* resulting format */
1390 unsigned rcsr = 0; /* resulting csr */
1399 } rv; /* resulting value */
1402 MIPS_FPU_EMU_INC_STATS(cp1ops);
1403 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1404 case s_fmt: { /* 0 */
1406 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1407 union ieee754sp(*u) (union ieee754sp);
1409 union ieee754sp fs, ft;
1411 switch (MIPSInst_FUNC(ir)) {
1414 handler.b = ieee754sp_add;
1417 handler.b = ieee754sp_sub;
1420 handler.b = ieee754sp_mul;
1423 handler.b = ieee754sp_div;
1428 if (!cpu_has_mips_4_5_r)
1431 handler.u = ieee754sp_sqrt;
1435 * Note that on some MIPS IV implementations such as the
1436 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1437 * achieve full IEEE-754 accuracy - however this emulator does.
1440 if (!cpu_has_mips_4_5_r2)
1443 handler.u = fpemu_sp_rsqrt;
1447 if (!cpu_has_mips_4_5_r2)
1450 handler.u = fpemu_sp_recip;
1454 if (!cpu_has_mips_4_5_r)
1457 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1458 if (((ctx->fcr31 & cond) != 0) !=
1459 ((MIPSInst_FT(ir) & 1) != 0))
1461 SPFROMREG(rv.s, MIPSInst_FS(ir));
1465 if (!cpu_has_mips_4_5_r)
1468 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1470 SPFROMREG(rv.s, MIPSInst_FS(ir));
1474 if (!cpu_has_mips_4_5_r)
1477 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1479 SPFROMREG(rv.s, MIPSInst_FS(ir));
1483 handler.u = ieee754sp_abs;
1487 handler.u = ieee754sp_neg;
1492 SPFROMREG(rv.s, MIPSInst_FS(ir));
1495 /* binary op on handler */
1497 SPFROMREG(fs, MIPSInst_FS(ir));
1498 SPFROMREG(ft, MIPSInst_FT(ir));
1500 rv.s = (*handler.b) (fs, ft);
1503 SPFROMREG(fs, MIPSInst_FS(ir));
1504 rv.s = (*handler.u) (fs);
1507 if (ieee754_cxtest(IEEE754_INEXACT)) {
1508 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1509 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1511 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1512 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1513 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1515 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1516 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1517 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1519 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1520 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1521 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1523 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1524 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1525 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1529 /* unary conv ops */
1531 return SIGILL; /* not defined */
1534 SPFROMREG(fs, MIPSInst_FS(ir));
1535 rv.d = ieee754dp_fsp(fs);
1540 SPFROMREG(fs, MIPSInst_FS(ir));
1541 rv.w = ieee754sp_tint(fs);
1549 if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64)
1552 oldrm = ieee754_csr.rm;
1553 SPFROMREG(fs, MIPSInst_FS(ir));
1554 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1555 rv.w = ieee754sp_tint(fs);
1556 ieee754_csr.rm = oldrm;
1561 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1564 SPFROMREG(fs, MIPSInst_FS(ir));
1565 rv.l = ieee754sp_tlong(fs);
1573 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1576 oldrm = ieee754_csr.rm;
1577 SPFROMREG(fs, MIPSInst_FS(ir));
1578 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1579 rv.l = ieee754sp_tlong(fs);
1580 ieee754_csr.rm = oldrm;
1585 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1586 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1587 union ieee754sp fs, ft;
1589 SPFROMREG(fs, MIPSInst_FS(ir));
1590 SPFROMREG(ft, MIPSInst_FT(ir));
1591 rv.w = ieee754sp_cmp(fs, ft,
1592 cmptab[cmpop & 0x7], cmpop & 0x8);
1594 if ((cmpop & 0x8) && ieee754_cxtest
1595 (IEEE754_INVALID_OPERATION))
1596 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1608 union ieee754dp fs, ft;
1610 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1611 union ieee754dp(*u) (union ieee754dp);
1614 switch (MIPSInst_FUNC(ir)) {
1617 handler.b = ieee754dp_add;
1620 handler.b = ieee754dp_sub;
1623 handler.b = ieee754dp_mul;
1626 handler.b = ieee754dp_div;
1631 if (!cpu_has_mips_2_3_4_5_r)
1634 handler.u = ieee754dp_sqrt;
1637 * Note that on some MIPS IV implementations such as the
1638 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1639 * achieve full IEEE-754 accuracy - however this emulator does.
1642 if (!cpu_has_mips_4_5_r2)
1645 handler.u = fpemu_dp_rsqrt;
1648 if (!cpu_has_mips_4_5_r2)
1651 handler.u = fpemu_dp_recip;
1654 if (!cpu_has_mips_4_5_r)
1657 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1658 if (((ctx->fcr31 & cond) != 0) !=
1659 ((MIPSInst_FT(ir) & 1) != 0))
1661 DPFROMREG(rv.d, MIPSInst_FS(ir));
1664 if (!cpu_has_mips_4_5_r)
1667 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1669 DPFROMREG(rv.d, MIPSInst_FS(ir));
1672 if (!cpu_has_mips_4_5_r)
1675 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1677 DPFROMREG(rv.d, MIPSInst_FS(ir));
1680 handler.u = ieee754dp_abs;
1684 handler.u = ieee754dp_neg;
1689 DPFROMREG(rv.d, MIPSInst_FS(ir));
1692 /* binary op on handler */
1694 DPFROMREG(fs, MIPSInst_FS(ir));
1695 DPFROMREG(ft, MIPSInst_FT(ir));
1697 rv.d = (*handler.b) (fs, ft);
1700 DPFROMREG(fs, MIPSInst_FS(ir));
1701 rv.d = (*handler.u) (fs);
1708 DPFROMREG(fs, MIPSInst_FS(ir));
1709 rv.s = ieee754sp_fdp(fs);
1714 return SIGILL; /* not defined */
1717 DPFROMREG(fs, MIPSInst_FS(ir));
1718 rv.w = ieee754dp_tint(fs); /* wrong */
1726 if (!cpu_has_mips_2_3_4_5_r)
1729 oldrm = ieee754_csr.rm;
1730 DPFROMREG(fs, MIPSInst_FS(ir));
1731 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1732 rv.w = ieee754dp_tint(fs);
1733 ieee754_csr.rm = oldrm;
1738 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1741 DPFROMREG(fs, MIPSInst_FS(ir));
1742 rv.l = ieee754dp_tlong(fs);
1750 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1753 oldrm = ieee754_csr.rm;
1754 DPFROMREG(fs, MIPSInst_FS(ir));
1755 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1756 rv.l = ieee754dp_tlong(fs);
1757 ieee754_csr.rm = oldrm;
1762 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1763 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1764 union ieee754dp fs, ft;
1766 DPFROMREG(fs, MIPSInst_FS(ir));
1767 DPFROMREG(ft, MIPSInst_FT(ir));
1768 rv.w = ieee754dp_cmp(fs, ft,
1769 cmptab[cmpop & 0x7], cmpop & 0x8);
1774 (IEEE754_INVALID_OPERATION))
1775 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1788 switch (MIPSInst_FUNC(ir)) {
1790 /* convert word to single precision real */
1791 SPFROMREG(fs, MIPSInst_FS(ir));
1792 rv.s = ieee754sp_fint(fs.bits);
1796 /* convert word to double precision real */
1797 SPFROMREG(fs, MIPSInst_FS(ir));
1798 rv.d = ieee754dp_fint(fs.bits);
1809 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1812 DIFROMREG(bits, MIPSInst_FS(ir));
1814 switch (MIPSInst_FUNC(ir)) {
1816 /* convert long to single precision real */
1817 rv.s = ieee754sp_flong(bits);
1821 /* convert long to double precision real */
1822 rv.d = ieee754dp_flong(bits);
1835 * Update the fpu CSR register for this operation.
1836 * If an exception is required, generate a tidy SIGFPE exception,
1837 * without updating the result register.
1838 * Note: cause exception bits do not accumulate, they are rewritten
1839 * for each op; only the flag/sticky bits accumulate.
1841 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1842 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1843 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
1848 * Now we can safely write the result back to the register file.
1853 if (cpu_has_mips_4_5_r)
1854 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
1856 cbit = FPU_CSR_COND;
1860 ctx->fcr31 &= ~cbit;
1864 DPTOREG(rv.d, MIPSInst_FD(ir));
1867 SPTOREG(rv.s, MIPSInst_FD(ir));
1870 SITOREG(rv.w, MIPSInst_FD(ir));
1873 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1876 DITOREG(rv.l, MIPSInst_FD(ir));
1885 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1886 int has_fpu, void *__user *fault_addr)
1888 unsigned long oldepc, prevepc;
1889 struct mm_decoded_insn dec_insn;
1894 oldepc = xcp->cp0_epc;
1896 prevepc = xcp->cp0_epc;
1898 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
1900 * Get next 2 microMIPS instructions and convert them
1901 * into 32-bit instructions.
1903 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
1904 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
1905 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
1906 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
1907 MIPS_FPU_EMU_INC_STATS(errors);
1912 /* Get first instruction. */
1913 if (mm_insn_16bit(*instr_ptr)) {
1914 /* Duplicate the half-word. */
1915 dec_insn.insn = (*instr_ptr << 16) |
1917 /* 16-bit instruction. */
1918 dec_insn.pc_inc = 2;
1921 dec_insn.insn = (*instr_ptr << 16) |
1923 /* 32-bit instruction. */
1924 dec_insn.pc_inc = 4;
1927 /* Get second instruction. */
1928 if (mm_insn_16bit(*instr_ptr)) {
1929 /* Duplicate the half-word. */
1930 dec_insn.next_insn = (*instr_ptr << 16) |
1932 /* 16-bit instruction. */
1933 dec_insn.next_pc_inc = 2;
1935 dec_insn.next_insn = (*instr_ptr << 16) |
1937 /* 32-bit instruction. */
1938 dec_insn.next_pc_inc = 4;
1940 dec_insn.micro_mips_mode = 1;
1942 if ((get_user(dec_insn.insn,
1943 (mips_instruction __user *) xcp->cp0_epc)) ||
1944 (get_user(dec_insn.next_insn,
1945 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
1946 MIPS_FPU_EMU_INC_STATS(errors);
1949 dec_insn.pc_inc = 4;
1950 dec_insn.next_pc_inc = 4;
1951 dec_insn.micro_mips_mode = 0;
1954 if ((dec_insn.insn == 0) ||
1955 ((dec_insn.pc_inc == 2) &&
1956 ((dec_insn.insn & 0xffff) == MM_NOP16)))
1957 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
1960 * The 'ieee754_csr' is an alias of
1961 * ctx->fcr31. No need to copy ctx->fcr31 to
1962 * ieee754_csr. But ieee754_csr.rm is ieee
1963 * library modes. (not mips rounding mode)
1965 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
1974 } while (xcp->cp0_epc > prevepc);
1976 /* SIGILL indicates a non-fpu instruction */
1977 if (sig == SIGILL && xcp->cp0_epc != oldepc)
1978 /* but if EPC has advanced, then ignore it */