2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/stddef.h>
21 #include <asm/mipsregs.h>
22 #include <asm/system.h>
25 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
26 * the implementation of the "wait" feature differs between CPU families. This
27 * points to the function that implements CPU specific wait.
28 * The wait instruction stops the pipeline and reduces the power consumption of
31 void (*cpu_wait)(void) = NULL;
33 static void r3081_wait(void)
35 unsigned long cfg = read_c0_conf();
36 write_c0_conf(cfg | R30XX_CONF_HALT);
39 static void r39xx_wait(void)
43 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
48 * There is a race when WAIT instruction executed with interrupt
50 * But it is implementation-dependent wheter the pipelie restarts when
51 * a non-enabled interrupt is requested.
53 static void r4k_wait(void)
55 __asm__(" .set mips3 \n"
61 * This variant is preferable as it allows testing need_resched and going to
62 * sleep depending on the outcome atomically. Unfortunately the "It is
63 * implementation-dependent whether the pipeline restarts when a non-enabled
64 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
65 * using this version a gamble.
67 static void r4k_wait_irqoff(void)
71 __asm__(" .set mips3 \n"
77 /* The Au1xxx wait is available only if using 32khz counter or
78 * external timer source, but specifically not CP0 Counter. */
81 static void au1k_wait(void)
83 /* using the wait instruction makes CP0 counter unusable */
84 __asm__(" .set mips3 \n"
85 " cache 0x14, 0(%0) \n"
86 " cache 0x14, 32(%0) \n"
98 static int __initdata nowait = 0;
100 int __init wait_disable(char *s)
107 __setup("nowait", wait_disable);
109 static inline void check_wait(void)
111 struct cpuinfo_mips *c = ¤t_cpu_data;
113 printk("Checking for 'wait' instruction... ");
115 printk (" disabled.\n");
119 switch (c->cputype) {
122 cpu_wait = r3081_wait;
123 printk(" available.\n");
126 cpu_wait = r39xx_wait;
127 printk(" available.\n");
130 /* case CPU_R4300: */
149 printk(" available.\n");
152 cpu_wait = r4k_wait_irqoff;
153 printk(" available.\n");
160 if (allow_au1k_wait) {
161 cpu_wait = au1k_wait;
162 printk(" available.\n");
164 printk(" unavailable.\n");
167 if ((c->processor_id & 0x00ff) >= 0x40) {
169 printk(" available.\n");
171 printk(" unavailable.\n");
175 printk(" unavailable.\n");
180 void __init check_bugs32(void)
186 * Probe whether cpu has config register by trying to play with
187 * alternate cache bit and see whether it matters.
188 * It's used by cpu_probe to distinguish between R3000A and R3081.
190 static inline int cpu_has_confreg(void)
192 #ifdef CONFIG_CPU_R3000
193 extern unsigned long r3k_cache_size(unsigned long);
194 unsigned long size1, size2;
195 unsigned long cfg = read_c0_conf();
197 size1 = r3k_cache_size(ST0_ISC);
198 write_c0_conf(cfg ^ R30XX_CONF_AC);
199 size2 = r3k_cache_size(ST0_ISC);
201 return size1 != size2;
208 * Get the FPU Implementation/Revision.
210 static inline unsigned long cpu_get_fpu_id(void)
212 unsigned long tmp, fpu_id;
214 tmp = read_c0_status();
216 fpu_id = read_32bit_cp1_register(CP1_REVISION);
217 write_c0_status(tmp);
222 * Check the CPU has an FPU the official way.
224 static inline int __cpu_has_fpu(void)
226 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
229 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
232 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
234 switch (c->processor_id & 0xff00) {
236 c->cputype = CPU_R2000;
237 c->isa_level = MIPS_CPU_ISA_I;
238 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
241 c->options |= MIPS_CPU_FPU;
245 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
246 if (cpu_has_confreg())
247 c->cputype = CPU_R3081E;
249 c->cputype = CPU_R3000A;
251 c->cputype = CPU_R3000;
252 c->isa_level = MIPS_CPU_ISA_I;
253 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
256 c->options |= MIPS_CPU_FPU;
260 if (read_c0_config() & CONF_SC) {
261 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
262 c->cputype = CPU_R4400PC;
264 c->cputype = CPU_R4000PC;
266 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
267 c->cputype = CPU_R4400SC;
269 c->cputype = CPU_R4000SC;
272 c->isa_level = MIPS_CPU_ISA_III;
273 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
274 MIPS_CPU_WATCH | MIPS_CPU_VCE |
278 case PRID_IMP_VR41XX:
279 switch (c->processor_id & 0xf0) {
280 case PRID_REV_VR4111:
281 c->cputype = CPU_VR4111;
283 case PRID_REV_VR4121:
284 c->cputype = CPU_VR4121;
286 case PRID_REV_VR4122:
287 if ((c->processor_id & 0xf) < 0x3)
288 c->cputype = CPU_VR4122;
290 c->cputype = CPU_VR4181A;
292 case PRID_REV_VR4130:
293 if ((c->processor_id & 0xf) < 0x4)
294 c->cputype = CPU_VR4131;
296 c->cputype = CPU_VR4133;
299 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
300 c->cputype = CPU_VR41XX;
303 c->isa_level = MIPS_CPU_ISA_III;
304 c->options = R4K_OPTS;
308 c->cputype = CPU_R4300;
309 c->isa_level = MIPS_CPU_ISA_III;
310 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
315 c->cputype = CPU_R4600;
316 c->isa_level = MIPS_CPU_ISA_III;
317 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
324 * This processor doesn't have an MMU, so it's not
325 * "real easy" to run Linux on it. It is left purely
326 * for documentation. Commented out because it shares
327 * it's c0_prid id number with the TX3900.
329 c->cputype = CPU_R4650;
330 c->isa_level = MIPS_CPU_ISA_III;
331 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
336 c->isa_level = MIPS_CPU_ISA_I;
337 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
339 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
340 c->cputype = CPU_TX3927;
343 switch (c->processor_id & 0xff) {
344 case PRID_REV_TX3912:
345 c->cputype = CPU_TX3912;
348 case PRID_REV_TX3922:
349 c->cputype = CPU_TX3922;
353 c->cputype = CPU_UNKNOWN;
359 c->cputype = CPU_R4700;
360 c->isa_level = MIPS_CPU_ISA_III;
361 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
366 c->cputype = CPU_TX49XX;
367 c->isa_level = MIPS_CPU_ISA_III;
368 c->options = R4K_OPTS | MIPS_CPU_LLSC;
369 if (!(c->processor_id & 0x08))
370 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
374 c->cputype = CPU_R5000;
375 c->isa_level = MIPS_CPU_ISA_IV;
376 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
381 c->cputype = CPU_R5432;
382 c->isa_level = MIPS_CPU_ISA_IV;
383 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
384 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
388 c->cputype = CPU_R5500;
389 c->isa_level = MIPS_CPU_ISA_IV;
390 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
391 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
394 case PRID_IMP_NEVADA:
395 c->cputype = CPU_NEVADA;
396 c->isa_level = MIPS_CPU_ISA_IV;
397 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
398 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
402 c->cputype = CPU_R6000;
403 c->isa_level = MIPS_CPU_ISA_II;
404 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
408 case PRID_IMP_R6000A:
409 c->cputype = CPU_R6000A;
410 c->isa_level = MIPS_CPU_ISA_II;
411 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
415 case PRID_IMP_RM7000:
416 c->cputype = CPU_RM7000;
417 c->isa_level = MIPS_CPU_ISA_IV;
418 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
421 * Undocumented RM7000: Bit 29 in the info register of
422 * the RM7000 v2.0 indicates if the TLB has 48 or 64
425 * 29 1 => 64 entry JTLB
428 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
430 case PRID_IMP_RM9000:
431 c->cputype = CPU_RM9000;
432 c->isa_level = MIPS_CPU_ISA_IV;
433 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
436 * Bit 29 in the info register of the RM9000
437 * indicates if the TLB has 48 or 64 entries.
439 * 29 1 => 64 entry JTLB
442 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
445 c->cputype = CPU_R8000;
446 c->isa_level = MIPS_CPU_ISA_IV;
447 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
448 MIPS_CPU_FPU | MIPS_CPU_32FPR |
450 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
452 case PRID_IMP_R10000:
453 c->cputype = CPU_R10000;
454 c->isa_level = MIPS_CPU_ISA_IV;
455 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
456 MIPS_CPU_FPU | MIPS_CPU_32FPR |
457 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
461 case PRID_IMP_R12000:
462 c->cputype = CPU_R12000;
463 c->isa_level = MIPS_CPU_ISA_IV;
464 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
465 MIPS_CPU_FPU | MIPS_CPU_32FPR |
466 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
470 case PRID_IMP_R14000:
471 c->cputype = CPU_R14000;
472 c->isa_level = MIPS_CPU_ISA_IV;
473 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
474 MIPS_CPU_FPU | MIPS_CPU_32FPR |
475 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
482 static char unknown_isa[] __initdata = KERN_ERR \
483 "Unsupported ISA type, c0.config0: %d.";
485 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
487 unsigned int config0;
490 config0 = read_c0_config();
492 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
493 c->options |= MIPS_CPU_TLB;
494 isa = (config0 & MIPS_CONF_AT) >> 13;
497 switch ((config0 & MIPS_CONF_AR) >> 10) {
499 c->isa_level = MIPS_CPU_ISA_M32R1;
502 c->isa_level = MIPS_CPU_ISA_M32R2;
509 switch ((config0 & MIPS_CONF_AR) >> 10) {
511 c->isa_level = MIPS_CPU_ISA_M64R1;
514 c->isa_level = MIPS_CPU_ISA_M64R2;
524 return config0 & MIPS_CONF_M;
527 panic(unknown_isa, config0);
530 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
532 unsigned int config1;
534 config1 = read_c0_config1();
536 if (config1 & MIPS_CONF1_MD)
537 c->ases |= MIPS_ASE_MDMX;
538 if (config1 & MIPS_CONF1_WR)
539 c->options |= MIPS_CPU_WATCH;
540 if (config1 & MIPS_CONF1_CA)
541 c->ases |= MIPS_ASE_MIPS16;
542 if (config1 & MIPS_CONF1_EP)
543 c->options |= MIPS_CPU_EJTAG;
544 if (config1 & MIPS_CONF1_FP) {
545 c->options |= MIPS_CPU_FPU;
546 c->options |= MIPS_CPU_32FPR;
549 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
551 return config1 & MIPS_CONF_M;
554 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
556 unsigned int config2;
558 config2 = read_c0_config2();
560 if (config2 & MIPS_CONF2_SL)
561 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
563 return config2 & MIPS_CONF_M;
566 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
568 unsigned int config3;
570 config3 = read_c0_config3();
572 if (config3 & MIPS_CONF3_SM)
573 c->ases |= MIPS_ASE_SMARTMIPS;
574 if (config3 & MIPS_CONF3_DSP)
575 c->ases |= MIPS_ASE_DSP;
576 if (config3 & MIPS_CONF3_VINT)
577 c->options |= MIPS_CPU_VINT;
578 if (config3 & MIPS_CONF3_VEIC)
579 c->options |= MIPS_CPU_VEIC;
580 if (config3 & MIPS_CONF3_MT)
581 c->ases |= MIPS_ASE_MIPSMT;
583 return config3 & MIPS_CONF_M;
586 static void __init decode_configs(struct cpuinfo_mips *c)
588 /* MIPS32 or MIPS64 compliant CPU. */
589 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
590 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
592 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
594 /* Read Config registers. */
595 if (!decode_config0(c))
596 return; /* actually worth a panic() */
597 if (!decode_config1(c))
599 if (!decode_config2(c))
601 if (!decode_config3(c))
605 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
608 switch (c->processor_id & 0xff00) {
610 c->cputype = CPU_4KC;
613 c->cputype = CPU_4KEC;
615 case PRID_IMP_4KECR2:
616 c->cputype = CPU_4KEC;
620 c->cputype = CPU_4KSC;
623 c->cputype = CPU_5KC;
626 c->cputype = CPU_20KC;
630 c->cputype = CPU_24K;
633 c->cputype = CPU_25KF;
636 c->cputype = CPU_34K;
639 c->cputype = CPU_74K;
644 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
647 switch (c->processor_id & 0xff00) {
648 case PRID_IMP_AU1_REV1:
649 case PRID_IMP_AU1_REV2:
650 switch ((c->processor_id >> 24) & 0xff) {
652 c->cputype = CPU_AU1000;
655 c->cputype = CPU_AU1500;
658 c->cputype = CPU_AU1100;
661 c->cputype = CPU_AU1550;
664 c->cputype = CPU_AU1200;
667 panic("Unknown Au Core!");
674 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
679 * For historical reasons the SB1 comes with it's own variant of
680 * cache code which eventually will be folded into c-r4k.c. Until
681 * then we pretend it's got it's own cache architecture.
683 c->options &= ~MIPS_CPU_4K_CACHE;
684 c->options |= MIPS_CPU_SB1_CACHE;
686 switch (c->processor_id & 0xff00) {
688 c->cputype = CPU_SB1;
689 /* FPU in pass1 is known to have issues. */
690 if ((c->processor_id & 0xff) < 0x02)
691 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
694 c->cputype = CPU_SB1A;
699 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
702 switch (c->processor_id & 0xff00) {
703 case PRID_IMP_SR71000:
704 c->cputype = CPU_SR71000;
711 static inline void cpu_probe_philips(struct cpuinfo_mips *c)
714 switch (c->processor_id & 0xff00) {
715 case PRID_IMP_PR4450:
716 c->cputype = CPU_PR4450;
717 c->isa_level = MIPS_CPU_ISA_M32R1;
720 panic("Unknown Philips Core!"); /* REVISIT: die? */
726 __init void cpu_probe(void)
728 struct cpuinfo_mips *c = ¤t_cpu_data;
730 c->processor_id = PRID_IMP_UNKNOWN;
731 c->fpu_id = FPIR_IMP_NONE;
732 c->cputype = CPU_UNKNOWN;
734 c->processor_id = read_c0_prid();
735 switch (c->processor_id & 0xff0000) {
736 case PRID_COMP_LEGACY:
742 case PRID_COMP_ALCHEMY:
743 cpu_probe_alchemy(c);
745 case PRID_COMP_SIBYTE:
748 case PRID_COMP_SANDCRAFT:
749 cpu_probe_sandcraft(c);
751 case PRID_COMP_PHILIPS:
752 cpu_probe_philips(c);
755 c->cputype = CPU_UNKNOWN;
757 if (c->options & MIPS_CPU_FPU) {
758 c->fpu_id = cpu_get_fpu_id();
760 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
761 c->isa_level == MIPS_CPU_ISA_M32R2 ||
762 c->isa_level == MIPS_CPU_ISA_M64R1 ||
763 c->isa_level == MIPS_CPU_ISA_M64R2) {
764 if (c->fpu_id & MIPS_FPIR_3D)
765 c->ases |= MIPS_ASE_MIPS3D;
770 __init void cpu_report(void)
772 struct cpuinfo_mips *c = ¤t_cpu_data;
774 printk("CPU revision is: %08x\n", c->processor_id);
775 if (c->options & MIPS_CPU_FPU)
776 printk("FPU revision is: %08x\n", c->fpu_id);