2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
23 #include <asm/cpu-type.h>
25 #include <asm/mipsregs.h>
26 #include <asm/mipsmtregs.h>
28 #include <asm/watch.h>
30 #include <asm/pgtable-bits.h>
31 #include <asm/spram.h>
32 #include <asm/uaccess.h>
34 static int mips_fpu_disabled;
36 static int __init fpu_disable(char *s)
38 cpu_data[0].options &= ~MIPS_CPU_FPU;
39 mips_fpu_disabled = 1;
44 __setup("nofpu", fpu_disable);
46 int mips_dsp_disabled;
48 static int __init dsp_disable(char *s)
50 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
51 mips_dsp_disabled = 1;
56 __setup("nodsp", dsp_disable);
58 static int mips_htw_disabled;
60 static int __init htw_disable(char *s)
62 mips_htw_disabled = 1;
63 cpu_data[0].options &= ~MIPS_CPU_HTW;
64 write_c0_pwctl(read_c0_pwctl() &
65 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
70 __setup("nohtw", htw_disable);
72 static inline void check_errata(void)
74 struct cpuinfo_mips *c = ¤t_cpu_data;
76 switch (current_cpu_type()) {
79 * Erratum "RPS May Cause Incorrect Instruction Execution"
80 * This code only handles VPE0, any SMP/RTOS code
81 * making use of VPE1 will be responsable for that VPE.
83 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
84 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
91 void __init check_bugs32(void)
97 * Probe whether cpu has config register by trying to play with
98 * alternate cache bit and see whether it matters.
99 * It's used by cpu_probe to distinguish between R3000A and R3081.
101 static inline int cpu_has_confreg(void)
103 #ifdef CONFIG_CPU_R3000
104 extern unsigned long r3k_cache_size(unsigned long);
105 unsigned long size1, size2;
106 unsigned long cfg = read_c0_conf();
108 size1 = r3k_cache_size(ST0_ISC);
109 write_c0_conf(cfg ^ R30XX_CONF_AC);
110 size2 = r3k_cache_size(ST0_ISC);
112 return size1 != size2;
118 static inline void set_elf_platform(int cpu, const char *plat)
121 __elf_platform = plat;
125 * Get the FPU Implementation/Revision.
127 static inline unsigned long cpu_get_fpu_id(void)
129 unsigned long tmp, fpu_id;
131 tmp = read_c0_status();
132 __enable_fpu(FPU_AS_IS);
133 fpu_id = read_32bit_cp1_register(CP1_REVISION);
134 write_c0_status(tmp);
139 * Check the CPU has an FPU the official way.
141 static inline int __cpu_has_fpu(void)
143 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
146 static inline unsigned long cpu_get_msa_id(void)
148 unsigned long status, msa_id;
150 status = read_c0_status();
151 __enable_fpu(FPU_64BIT);
153 msa_id = read_msa_ir();
155 write_c0_status(status);
159 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
161 #ifdef __NEED_VMBITS_PROBE
162 write_c0_entryhi(0x3fffffffffffe000ULL);
163 back_to_back_c0_hazard();
164 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
168 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
171 case MIPS_CPU_ISA_M64R2:
172 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
173 case MIPS_CPU_ISA_M64R1:
174 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
176 c->isa_level |= MIPS_CPU_ISA_V;
177 case MIPS_CPU_ISA_IV:
178 c->isa_level |= MIPS_CPU_ISA_IV;
179 case MIPS_CPU_ISA_III:
180 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
183 case MIPS_CPU_ISA_M32R2:
184 c->isa_level |= MIPS_CPU_ISA_M32R2;
185 case MIPS_CPU_ISA_M32R1:
186 c->isa_level |= MIPS_CPU_ISA_M32R1;
187 case MIPS_CPU_ISA_II:
188 c->isa_level |= MIPS_CPU_ISA_II;
193 static char unknown_isa[] = KERN_ERR \
194 "Unsupported ISA type, c0.config0: %d.";
196 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
198 unsigned int config6;
200 /* It's implementation dependent how the FTLB can be enabled */
201 switch (c->cputype) {
204 /* proAptiv & related cores use Config6 to enable the FTLB */
205 config6 = read_c0_config6();
208 write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
211 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
212 back_to_back_c0_hazard();
217 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
219 unsigned int config0;
222 config0 = read_c0_config();
225 * Look for Standard TLB or Dual VTLB and FTLB
227 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
228 (((config0 & MIPS_CONF_MT) >> 7) == 4))
229 c->options |= MIPS_CPU_TLB;
231 isa = (config0 & MIPS_CONF_AT) >> 13;
234 switch ((config0 & MIPS_CONF_AR) >> 10) {
236 set_isa(c, MIPS_CPU_ISA_M32R1);
239 set_isa(c, MIPS_CPU_ISA_M32R2);
246 switch ((config0 & MIPS_CONF_AR) >> 10) {
248 set_isa(c, MIPS_CPU_ISA_M64R1);
251 set_isa(c, MIPS_CPU_ISA_M64R2);
261 return config0 & MIPS_CONF_M;
264 panic(unknown_isa, config0);
267 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
269 unsigned int config1;
271 config1 = read_c0_config1();
273 if (config1 & MIPS_CONF1_MD)
274 c->ases |= MIPS_ASE_MDMX;
275 if (config1 & MIPS_CONF1_WR)
276 c->options |= MIPS_CPU_WATCH;
277 if (config1 & MIPS_CONF1_CA)
278 c->ases |= MIPS_ASE_MIPS16;
279 if (config1 & MIPS_CONF1_EP)
280 c->options |= MIPS_CPU_EJTAG;
281 if (config1 & MIPS_CONF1_FP) {
282 c->options |= MIPS_CPU_FPU;
283 c->options |= MIPS_CPU_32FPR;
286 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
287 c->tlbsizevtlb = c->tlbsize;
288 c->tlbsizeftlbsets = 0;
291 return config1 & MIPS_CONF_M;
294 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
296 unsigned int config2;
298 config2 = read_c0_config2();
300 if (config2 & MIPS_CONF2_SL)
301 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
303 return config2 & MIPS_CONF_M;
306 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
308 unsigned int config3;
310 config3 = read_c0_config3();
312 if (config3 & MIPS_CONF3_SM) {
313 c->ases |= MIPS_ASE_SMARTMIPS;
314 c->options |= MIPS_CPU_RIXI;
316 if (config3 & MIPS_CONF3_RXI)
317 c->options |= MIPS_CPU_RIXI;
318 if (config3 & MIPS_CONF3_DSP)
319 c->ases |= MIPS_ASE_DSP;
320 if (config3 & MIPS_CONF3_DSP2P)
321 c->ases |= MIPS_ASE_DSP2P;
322 if (config3 & MIPS_CONF3_VINT)
323 c->options |= MIPS_CPU_VINT;
324 if (config3 & MIPS_CONF3_VEIC)
325 c->options |= MIPS_CPU_VEIC;
326 if (config3 & MIPS_CONF3_MT)
327 c->ases |= MIPS_ASE_MIPSMT;
328 if (config3 & MIPS_CONF3_ULRI)
329 c->options |= MIPS_CPU_ULRI;
330 if (config3 & MIPS_CONF3_ISA)
331 c->options |= MIPS_CPU_MICROMIPS;
332 if (config3 & MIPS_CONF3_VZ)
333 c->ases |= MIPS_ASE_VZ;
334 if (config3 & MIPS_CONF3_SC)
335 c->options |= MIPS_CPU_SEGMENTS;
336 if (config3 & MIPS_CONF3_MSA)
337 c->ases |= MIPS_ASE_MSA;
338 /* Only tested on 32-bit cores */
339 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT))
340 c->options |= MIPS_CPU_HTW;
342 return config3 & MIPS_CONF_M;
345 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
347 unsigned int config4;
349 unsigned int mmuextdef;
350 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
352 config4 = read_c0_config4();
355 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
356 c->options |= MIPS_CPU_TLBINV;
357 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
359 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
360 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
361 c->tlbsizevtlb = c->tlbsize;
363 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
365 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
366 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
367 c->tlbsize = c->tlbsizevtlb;
368 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
370 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
371 newcf4 = (config4 & ~ftlb_page) |
372 (page_size_ftlb(mmuextdef) <<
373 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
374 write_c0_config4(newcf4);
375 back_to_back_c0_hazard();
376 config4 = read_c0_config4();
377 if (config4 != newcf4) {
378 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
380 /* Switch FTLB off */
381 set_ftlb_enable(c, 0);
384 c->tlbsizeftlbsets = 1 <<
385 ((config4 & MIPS_CONF4_FTLBSETS) >>
386 MIPS_CONF4_FTLBSETS_SHIFT);
387 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
388 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
389 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
394 c->kscratch_mask = (config4 >> 16) & 0xff;
396 return config4 & MIPS_CONF_M;
399 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
401 unsigned int config5;
403 config5 = read_c0_config5();
404 config5 &= ~MIPS_CONF5_UFR;
405 write_c0_config5(config5);
407 if (config5 & MIPS_CONF5_EVA)
408 c->options |= MIPS_CPU_EVA;
409 if (config5 & MIPS_CONF5_MRP)
410 c->options |= MIPS_CPU_MAAR;
412 return config5 & MIPS_CONF_M;
415 static void decode_configs(struct cpuinfo_mips *c)
419 /* MIPS32 or MIPS64 compliant CPU. */
420 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
421 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
423 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
425 /* Enable FTLB if present */
426 set_ftlb_enable(c, 1);
428 ok = decode_config0(c); /* Read Config registers. */
429 BUG_ON(!ok); /* Arch spec violation! */
431 ok = decode_config1(c);
433 ok = decode_config2(c);
435 ok = decode_config3(c);
437 ok = decode_config4(c);
439 ok = decode_config5(c);
441 mips_probe_watch_registers(c);
444 /* Enable the RIXI exceptions */
445 write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
446 back_to_back_c0_hazard();
447 /* Verify the IEC bit is set */
448 if (read_c0_pagegrain() & PG_IEC)
449 c->options |= MIPS_CPU_RIXIEX;
452 #ifndef CONFIG_MIPS_CPS
453 if (cpu_has_mips_r2) {
454 c->core = get_ebase_cpunum();
456 c->core >>= fls(core_nvpes()) - 1;
461 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
464 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
466 switch (c->processor_id & PRID_IMP_MASK) {
468 c->cputype = CPU_R2000;
469 __cpu_name[cpu] = "R2000";
470 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
473 c->options |= MIPS_CPU_FPU;
477 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
478 if (cpu_has_confreg()) {
479 c->cputype = CPU_R3081E;
480 __cpu_name[cpu] = "R3081";
482 c->cputype = CPU_R3000A;
483 __cpu_name[cpu] = "R3000A";
486 c->cputype = CPU_R3000;
487 __cpu_name[cpu] = "R3000";
489 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
492 c->options |= MIPS_CPU_FPU;
496 if (read_c0_config() & CONF_SC) {
497 if ((c->processor_id & PRID_REV_MASK) >=
499 c->cputype = CPU_R4400PC;
500 __cpu_name[cpu] = "R4400PC";
502 c->cputype = CPU_R4000PC;
503 __cpu_name[cpu] = "R4000PC";
506 int cca = read_c0_config() & CONF_CM_CMASK;
510 * SC and MC versions can't be reliably told apart,
511 * but only the latter support coherent caching
512 * modes so assume the firmware has set the KSEG0
513 * coherency attribute reasonably (if uncached, we
517 case CONF_CM_CACHABLE_CE:
518 case CONF_CM_CACHABLE_COW:
519 case CONF_CM_CACHABLE_CUW:
526 if ((c->processor_id & PRID_REV_MASK) >=
528 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
529 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
531 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
532 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
536 set_isa(c, MIPS_CPU_ISA_III);
537 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
538 MIPS_CPU_WATCH | MIPS_CPU_VCE |
542 case PRID_IMP_VR41XX:
543 set_isa(c, MIPS_CPU_ISA_III);
544 c->options = R4K_OPTS;
546 switch (c->processor_id & 0xf0) {
547 case PRID_REV_VR4111:
548 c->cputype = CPU_VR4111;
549 __cpu_name[cpu] = "NEC VR4111";
551 case PRID_REV_VR4121:
552 c->cputype = CPU_VR4121;
553 __cpu_name[cpu] = "NEC VR4121";
555 case PRID_REV_VR4122:
556 if ((c->processor_id & 0xf) < 0x3) {
557 c->cputype = CPU_VR4122;
558 __cpu_name[cpu] = "NEC VR4122";
560 c->cputype = CPU_VR4181A;
561 __cpu_name[cpu] = "NEC VR4181A";
564 case PRID_REV_VR4130:
565 if ((c->processor_id & 0xf) < 0x4) {
566 c->cputype = CPU_VR4131;
567 __cpu_name[cpu] = "NEC VR4131";
569 c->cputype = CPU_VR4133;
570 c->options |= MIPS_CPU_LLSC;
571 __cpu_name[cpu] = "NEC VR4133";
575 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
576 c->cputype = CPU_VR41XX;
577 __cpu_name[cpu] = "NEC Vr41xx";
582 c->cputype = CPU_R4300;
583 __cpu_name[cpu] = "R4300";
584 set_isa(c, MIPS_CPU_ISA_III);
585 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
590 c->cputype = CPU_R4600;
591 __cpu_name[cpu] = "R4600";
592 set_isa(c, MIPS_CPU_ISA_III);
593 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
600 * This processor doesn't have an MMU, so it's not
601 * "real easy" to run Linux on it. It is left purely
602 * for documentation. Commented out because it shares
603 * it's c0_prid id number with the TX3900.
605 c->cputype = CPU_R4650;
606 __cpu_name[cpu] = "R4650";
607 set_isa(c, MIPS_CPU_ISA_III);
608 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
613 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
615 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
616 c->cputype = CPU_TX3927;
617 __cpu_name[cpu] = "TX3927";
620 switch (c->processor_id & PRID_REV_MASK) {
621 case PRID_REV_TX3912:
622 c->cputype = CPU_TX3912;
623 __cpu_name[cpu] = "TX3912";
626 case PRID_REV_TX3922:
627 c->cputype = CPU_TX3922;
628 __cpu_name[cpu] = "TX3922";
635 c->cputype = CPU_R4700;
636 __cpu_name[cpu] = "R4700";
637 set_isa(c, MIPS_CPU_ISA_III);
638 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
643 c->cputype = CPU_TX49XX;
644 __cpu_name[cpu] = "R49XX";
645 set_isa(c, MIPS_CPU_ISA_III);
646 c->options = R4K_OPTS | MIPS_CPU_LLSC;
647 if (!(c->processor_id & 0x08))
648 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
652 c->cputype = CPU_R5000;
653 __cpu_name[cpu] = "R5000";
654 set_isa(c, MIPS_CPU_ISA_IV);
655 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
660 c->cputype = CPU_R5432;
661 __cpu_name[cpu] = "R5432";
662 set_isa(c, MIPS_CPU_ISA_IV);
663 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
664 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
668 c->cputype = CPU_R5500;
669 __cpu_name[cpu] = "R5500";
670 set_isa(c, MIPS_CPU_ISA_IV);
671 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
672 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
675 case PRID_IMP_NEVADA:
676 c->cputype = CPU_NEVADA;
677 __cpu_name[cpu] = "Nevada";
678 set_isa(c, MIPS_CPU_ISA_IV);
679 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
680 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
684 c->cputype = CPU_R6000;
685 __cpu_name[cpu] = "R6000";
686 set_isa(c, MIPS_CPU_ISA_II);
687 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
691 case PRID_IMP_R6000A:
692 c->cputype = CPU_R6000A;
693 __cpu_name[cpu] = "R6000A";
694 set_isa(c, MIPS_CPU_ISA_II);
695 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
699 case PRID_IMP_RM7000:
700 c->cputype = CPU_RM7000;
701 __cpu_name[cpu] = "RM7000";
702 set_isa(c, MIPS_CPU_ISA_IV);
703 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
706 * Undocumented RM7000: Bit 29 in the info register of
707 * the RM7000 v2.0 indicates if the TLB has 48 or 64
710 * 29 1 => 64 entry JTLB
713 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
716 c->cputype = CPU_R8000;
717 __cpu_name[cpu] = "RM8000";
718 set_isa(c, MIPS_CPU_ISA_IV);
719 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
720 MIPS_CPU_FPU | MIPS_CPU_32FPR |
722 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
724 case PRID_IMP_R10000:
725 c->cputype = CPU_R10000;
726 __cpu_name[cpu] = "R10000";
727 set_isa(c, MIPS_CPU_ISA_IV);
728 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
729 MIPS_CPU_FPU | MIPS_CPU_32FPR |
730 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
734 case PRID_IMP_R12000:
735 c->cputype = CPU_R12000;
736 __cpu_name[cpu] = "R12000";
737 set_isa(c, MIPS_CPU_ISA_IV);
738 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
739 MIPS_CPU_FPU | MIPS_CPU_32FPR |
740 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
744 case PRID_IMP_R14000:
745 c->cputype = CPU_R14000;
746 __cpu_name[cpu] = "R14000";
747 set_isa(c, MIPS_CPU_ISA_IV);
748 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
749 MIPS_CPU_FPU | MIPS_CPU_32FPR |
750 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
754 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
755 switch (c->processor_id & PRID_REV_MASK) {
756 case PRID_REV_LOONGSON2E:
757 c->cputype = CPU_LOONGSON2;
758 __cpu_name[cpu] = "ICT Loongson-2";
759 set_elf_platform(cpu, "loongson2e");
761 case PRID_REV_LOONGSON2F:
762 c->cputype = CPU_LOONGSON2;
763 __cpu_name[cpu] = "ICT Loongson-2";
764 set_elf_platform(cpu, "loongson2f");
766 case PRID_REV_LOONGSON3A:
767 c->cputype = CPU_LOONGSON3;
768 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
769 __cpu_name[cpu] = "ICT Loongson-3";
770 set_elf_platform(cpu, "loongson3a");
772 case PRID_REV_LOONGSON3B_R1:
773 case PRID_REV_LOONGSON3B_R2:
774 c->cputype = CPU_LOONGSON3;
775 __cpu_name[cpu] = "ICT Loongson-3";
776 set_elf_platform(cpu, "loongson3b");
780 set_isa(c, MIPS_CPU_ISA_III);
781 c->options = R4K_OPTS |
782 MIPS_CPU_FPU | MIPS_CPU_LLSC |
786 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
789 c->cputype = CPU_LOONGSON1;
791 switch (c->processor_id & PRID_REV_MASK) {
792 case PRID_REV_LOONGSON1B:
793 __cpu_name[cpu] = "Loongson 1B";
801 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
803 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
804 switch (c->processor_id & PRID_IMP_MASK) {
806 c->cputype = CPU_4KC;
807 c->writecombine = _CACHE_UNCACHED;
808 __cpu_name[cpu] = "MIPS 4Kc";
811 case PRID_IMP_4KECR2:
812 c->cputype = CPU_4KEC;
813 c->writecombine = _CACHE_UNCACHED;
814 __cpu_name[cpu] = "MIPS 4KEc";
818 c->cputype = CPU_4KSC;
819 c->writecombine = _CACHE_UNCACHED;
820 __cpu_name[cpu] = "MIPS 4KSc";
823 c->cputype = CPU_5KC;
824 c->writecombine = _CACHE_UNCACHED;
825 __cpu_name[cpu] = "MIPS 5Kc";
828 c->cputype = CPU_5KE;
829 c->writecombine = _CACHE_UNCACHED;
830 __cpu_name[cpu] = "MIPS 5KE";
833 c->cputype = CPU_20KC;
834 c->writecombine = _CACHE_UNCACHED;
835 __cpu_name[cpu] = "MIPS 20Kc";
838 c->cputype = CPU_24K;
839 c->writecombine = _CACHE_UNCACHED;
840 __cpu_name[cpu] = "MIPS 24Kc";
843 c->cputype = CPU_24K;
844 c->writecombine = _CACHE_UNCACHED;
845 __cpu_name[cpu] = "MIPS 24KEc";
848 c->cputype = CPU_25KF;
849 c->writecombine = _CACHE_UNCACHED;
850 __cpu_name[cpu] = "MIPS 25Kc";
853 c->cputype = CPU_34K;
854 c->writecombine = _CACHE_UNCACHED;
855 __cpu_name[cpu] = "MIPS 34Kc";
858 c->cputype = CPU_74K;
859 c->writecombine = _CACHE_UNCACHED;
860 __cpu_name[cpu] = "MIPS 74Kc";
863 c->cputype = CPU_M14KC;
864 c->writecombine = _CACHE_UNCACHED;
865 __cpu_name[cpu] = "MIPS M14Kc";
867 case PRID_IMP_M14KEC:
868 c->cputype = CPU_M14KEC;
869 c->writecombine = _CACHE_UNCACHED;
870 __cpu_name[cpu] = "MIPS M14KEc";
873 c->cputype = CPU_1004K;
874 c->writecombine = _CACHE_UNCACHED;
875 __cpu_name[cpu] = "MIPS 1004Kc";
878 c->cputype = CPU_1074K;
879 c->writecombine = _CACHE_UNCACHED;
880 __cpu_name[cpu] = "MIPS 1074Kc";
882 case PRID_IMP_INTERAPTIV_UP:
883 c->cputype = CPU_INTERAPTIV;
884 __cpu_name[cpu] = "MIPS interAptiv";
886 case PRID_IMP_INTERAPTIV_MP:
887 c->cputype = CPU_INTERAPTIV;
888 __cpu_name[cpu] = "MIPS interAptiv (multi)";
890 case PRID_IMP_PROAPTIV_UP:
891 c->cputype = CPU_PROAPTIV;
892 __cpu_name[cpu] = "MIPS proAptiv";
894 case PRID_IMP_PROAPTIV_MP:
895 c->cputype = CPU_PROAPTIV;
896 __cpu_name[cpu] = "MIPS proAptiv (multi)";
899 c->cputype = CPU_P5600;
900 __cpu_name[cpu] = "MIPS P5600";
903 c->cputype = CPU_M5150;
904 __cpu_name[cpu] = "MIPS M5150";
913 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
916 switch (c->processor_id & PRID_IMP_MASK) {
917 case PRID_IMP_AU1_REV1:
918 case PRID_IMP_AU1_REV2:
919 c->cputype = CPU_ALCHEMY;
920 switch ((c->processor_id >> 24) & 0xff) {
922 __cpu_name[cpu] = "Au1000";
925 __cpu_name[cpu] = "Au1500";
928 __cpu_name[cpu] = "Au1100";
931 __cpu_name[cpu] = "Au1550";
934 __cpu_name[cpu] = "Au1200";
935 if ((c->processor_id & PRID_REV_MASK) == 2)
936 __cpu_name[cpu] = "Au1250";
939 __cpu_name[cpu] = "Au1210";
942 __cpu_name[cpu] = "Au1xxx";
949 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
953 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
954 switch (c->processor_id & PRID_IMP_MASK) {
956 c->cputype = CPU_SB1;
957 __cpu_name[cpu] = "SiByte SB1";
958 /* FPU in pass1 is known to have issues. */
959 if ((c->processor_id & PRID_REV_MASK) < 0x02)
960 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
963 c->cputype = CPU_SB1A;
964 __cpu_name[cpu] = "SiByte SB1A";
969 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
972 switch (c->processor_id & PRID_IMP_MASK) {
973 case PRID_IMP_SR71000:
974 c->cputype = CPU_SR71000;
975 __cpu_name[cpu] = "Sandcraft SR71000";
982 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
985 switch (c->processor_id & PRID_IMP_MASK) {
986 case PRID_IMP_PR4450:
987 c->cputype = CPU_PR4450;
988 __cpu_name[cpu] = "Philips PR4450";
989 set_isa(c, MIPS_CPU_ISA_M32R1);
994 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
997 switch (c->processor_id & PRID_IMP_MASK) {
998 case PRID_IMP_BMIPS32_REV4:
999 case PRID_IMP_BMIPS32_REV8:
1000 c->cputype = CPU_BMIPS32;
1001 __cpu_name[cpu] = "Broadcom BMIPS32";
1002 set_elf_platform(cpu, "bmips32");
1004 case PRID_IMP_BMIPS3300:
1005 case PRID_IMP_BMIPS3300_ALT:
1006 case PRID_IMP_BMIPS3300_BUG:
1007 c->cputype = CPU_BMIPS3300;
1008 __cpu_name[cpu] = "Broadcom BMIPS3300";
1009 set_elf_platform(cpu, "bmips3300");
1011 case PRID_IMP_BMIPS43XX: {
1012 int rev = c->processor_id & PRID_REV_MASK;
1014 if (rev >= PRID_REV_BMIPS4380_LO &&
1015 rev <= PRID_REV_BMIPS4380_HI) {
1016 c->cputype = CPU_BMIPS4380;
1017 __cpu_name[cpu] = "Broadcom BMIPS4380";
1018 set_elf_platform(cpu, "bmips4380");
1020 c->cputype = CPU_BMIPS4350;
1021 __cpu_name[cpu] = "Broadcom BMIPS4350";
1022 set_elf_platform(cpu, "bmips4350");
1026 case PRID_IMP_BMIPS5000:
1027 c->cputype = CPU_BMIPS5000;
1028 __cpu_name[cpu] = "Broadcom BMIPS5000";
1029 set_elf_platform(cpu, "bmips5000");
1030 c->options |= MIPS_CPU_ULRI;
1035 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1038 switch (c->processor_id & PRID_IMP_MASK) {
1039 case PRID_IMP_CAVIUM_CN38XX:
1040 case PRID_IMP_CAVIUM_CN31XX:
1041 case PRID_IMP_CAVIUM_CN30XX:
1042 c->cputype = CPU_CAVIUM_OCTEON;
1043 __cpu_name[cpu] = "Cavium Octeon";
1045 case PRID_IMP_CAVIUM_CN58XX:
1046 case PRID_IMP_CAVIUM_CN56XX:
1047 case PRID_IMP_CAVIUM_CN50XX:
1048 case PRID_IMP_CAVIUM_CN52XX:
1049 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1050 __cpu_name[cpu] = "Cavium Octeon+";
1052 set_elf_platform(cpu, "octeon");
1054 case PRID_IMP_CAVIUM_CN61XX:
1055 case PRID_IMP_CAVIUM_CN63XX:
1056 case PRID_IMP_CAVIUM_CN66XX:
1057 case PRID_IMP_CAVIUM_CN68XX:
1058 case PRID_IMP_CAVIUM_CNF71XX:
1059 c->cputype = CPU_CAVIUM_OCTEON2;
1060 __cpu_name[cpu] = "Cavium Octeon II";
1061 set_elf_platform(cpu, "octeon2");
1063 case PRID_IMP_CAVIUM_CN70XX:
1064 case PRID_IMP_CAVIUM_CN78XX:
1065 c->cputype = CPU_CAVIUM_OCTEON3;
1066 __cpu_name[cpu] = "Cavium Octeon III";
1067 set_elf_platform(cpu, "octeon3");
1070 printk(KERN_INFO "Unknown Octeon chip!\n");
1071 c->cputype = CPU_UNKNOWN;
1076 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1079 /* JZRISC does not implement the CP0 counter. */
1080 c->options &= ~MIPS_CPU_COUNTER;
1081 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1082 switch (c->processor_id & PRID_IMP_MASK) {
1083 case PRID_IMP_JZRISC:
1084 c->cputype = CPU_JZRISC;
1085 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1086 __cpu_name[cpu] = "Ingenic JZRISC";
1089 panic("Unknown Ingenic Processor ID!");
1094 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1098 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1099 c->cputype = CPU_ALCHEMY;
1100 __cpu_name[cpu] = "Au1300";
1101 /* following stuff is not for Alchemy */
1105 c->options = (MIPS_CPU_TLB |
1113 switch (c->processor_id & PRID_IMP_MASK) {
1114 case PRID_IMP_NETLOGIC_XLP2XX:
1115 case PRID_IMP_NETLOGIC_XLP9XX:
1116 case PRID_IMP_NETLOGIC_XLP5XX:
1117 c->cputype = CPU_XLP;
1118 __cpu_name[cpu] = "Broadcom XLPII";
1121 case PRID_IMP_NETLOGIC_XLP8XX:
1122 case PRID_IMP_NETLOGIC_XLP3XX:
1123 c->cputype = CPU_XLP;
1124 __cpu_name[cpu] = "Netlogic XLP";
1127 case PRID_IMP_NETLOGIC_XLR732:
1128 case PRID_IMP_NETLOGIC_XLR716:
1129 case PRID_IMP_NETLOGIC_XLR532:
1130 case PRID_IMP_NETLOGIC_XLR308:
1131 case PRID_IMP_NETLOGIC_XLR532C:
1132 case PRID_IMP_NETLOGIC_XLR516C:
1133 case PRID_IMP_NETLOGIC_XLR508C:
1134 case PRID_IMP_NETLOGIC_XLR308C:
1135 c->cputype = CPU_XLR;
1136 __cpu_name[cpu] = "Netlogic XLR";
1139 case PRID_IMP_NETLOGIC_XLS608:
1140 case PRID_IMP_NETLOGIC_XLS408:
1141 case PRID_IMP_NETLOGIC_XLS404:
1142 case PRID_IMP_NETLOGIC_XLS208:
1143 case PRID_IMP_NETLOGIC_XLS204:
1144 case PRID_IMP_NETLOGIC_XLS108:
1145 case PRID_IMP_NETLOGIC_XLS104:
1146 case PRID_IMP_NETLOGIC_XLS616B:
1147 case PRID_IMP_NETLOGIC_XLS608B:
1148 case PRID_IMP_NETLOGIC_XLS416B:
1149 case PRID_IMP_NETLOGIC_XLS412B:
1150 case PRID_IMP_NETLOGIC_XLS408B:
1151 case PRID_IMP_NETLOGIC_XLS404B:
1152 c->cputype = CPU_XLR;
1153 __cpu_name[cpu] = "Netlogic XLS";
1157 pr_info("Unknown Netlogic chip id [%02x]!\n",
1159 c->cputype = CPU_XLR;
1163 if (c->cputype == CPU_XLP) {
1164 set_isa(c, MIPS_CPU_ISA_M64R2);
1165 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1166 /* This will be updated again after all threads are woken up */
1167 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1169 set_isa(c, MIPS_CPU_ISA_M64R1);
1170 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1172 c->kscratch_mask = 0xf;
1176 /* For use by uaccess.h */
1178 EXPORT_SYMBOL(__ua_limit);
1181 const char *__cpu_name[NR_CPUS];
1182 const char *__elf_platform;
1184 void cpu_probe(void)
1186 struct cpuinfo_mips *c = ¤t_cpu_data;
1187 unsigned int cpu = smp_processor_id();
1189 c->processor_id = PRID_IMP_UNKNOWN;
1190 c->fpu_id = FPIR_IMP_NONE;
1191 c->cputype = CPU_UNKNOWN;
1192 c->writecombine = _CACHE_UNCACHED;
1194 c->processor_id = read_c0_prid();
1195 switch (c->processor_id & PRID_COMP_MASK) {
1196 case PRID_COMP_LEGACY:
1197 cpu_probe_legacy(c, cpu);
1199 case PRID_COMP_MIPS:
1200 cpu_probe_mips(c, cpu);
1202 case PRID_COMP_ALCHEMY:
1203 cpu_probe_alchemy(c, cpu);
1205 case PRID_COMP_SIBYTE:
1206 cpu_probe_sibyte(c, cpu);
1208 case PRID_COMP_BROADCOM:
1209 cpu_probe_broadcom(c, cpu);
1211 case PRID_COMP_SANDCRAFT:
1212 cpu_probe_sandcraft(c, cpu);
1215 cpu_probe_nxp(c, cpu);
1217 case PRID_COMP_CAVIUM:
1218 cpu_probe_cavium(c, cpu);
1220 case PRID_COMP_INGENIC:
1221 cpu_probe_ingenic(c, cpu);
1223 case PRID_COMP_NETLOGIC:
1224 cpu_probe_netlogic(c, cpu);
1228 BUG_ON(!__cpu_name[cpu]);
1229 BUG_ON(c->cputype == CPU_UNKNOWN);
1232 * Platform code can force the cpu type to optimize code
1233 * generation. In that case be sure the cpu type is correctly
1234 * manually setup otherwise it could trigger some nasty bugs.
1236 BUG_ON(current_cpu_type() != c->cputype);
1238 if (mips_fpu_disabled)
1239 c->options &= ~MIPS_CPU_FPU;
1241 if (mips_dsp_disabled)
1242 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1244 if (mips_htw_disabled) {
1245 c->options &= ~MIPS_CPU_HTW;
1246 write_c0_pwctl(read_c0_pwctl() &
1247 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1250 if (c->options & MIPS_CPU_FPU) {
1251 c->fpu_id = cpu_get_fpu_id();
1253 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1254 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1255 if (c->fpu_id & MIPS_FPIR_3D)
1256 c->ases |= MIPS_ASE_MIPS3D;
1260 if (cpu_has_mips_r2) {
1261 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1262 /* R2 has Performance Counter Interrupt indicator */
1263 c->options |= MIPS_CPU_PCI;
1269 c->msa_id = cpu_get_msa_id();
1270 WARN(c->msa_id & MSA_IR_WRPF,
1271 "Vector register partitioning unimplemented!");
1274 cpu_probe_vmbits(c);
1278 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1282 void cpu_report(void)
1284 struct cpuinfo_mips *c = ¤t_cpu_data;
1286 pr_info("CPU%d revision is: %08x (%s)\n",
1287 smp_processor_id(), c->processor_id, cpu_name_string());
1288 if (c->options & MIPS_CPU_FPU)
1289 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1291 pr_info("MSA revision is: %08x\n", c->msa_id);