2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
29 #include <asm/watch.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <asm/uaccess.h>
35 /* Hardware capabilities */
36 unsigned int elf_hwcap __read_mostly;
39 * Get the FPU Implementation/Revision.
41 static inline unsigned long cpu_get_fpu_id(void)
43 unsigned long tmp, fpu_id;
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
53 * Check if the CPU has an external FPU.
55 static inline int __cpu_has_fpu(void)
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
60 static inline unsigned long cpu_get_msa_id(void)
62 unsigned long status, msa_id;
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
67 msa_id = read_msa_ir();
69 write_c0_status(status);
74 * Determine the FCSR mask for FPU hardware.
76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
102 * Set the FIR feature flags for the FPU emulator.
104 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
109 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
110 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
111 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
112 value |= MIPS_FPIR_D | MIPS_FPIR_S;
113 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
114 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
115 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
119 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
120 static unsigned int mips_nofpu_msk31;
123 * Set options for FPU hardware.
125 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
127 c->fpu_id = cpu_get_fpu_id();
128 mips_nofpu_msk31 = c->fpu_msk31;
130 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
131 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
132 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
133 if (c->fpu_id & MIPS_FPIR_3D)
134 c->ases |= MIPS_ASE_MIPS3D;
135 if (c->fpu_id & MIPS_FPIR_FREP)
136 c->options |= MIPS_CPU_FRE;
139 cpu_set_fpu_fcsr_mask(c);
143 * Set options for the FPU emulator.
145 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
147 c->options &= ~MIPS_CPU_FPU;
148 c->fpu_msk31 = mips_nofpu_msk31;
153 static int mips_fpu_disabled;
155 static int __init fpu_disable(char *s)
157 cpu_set_nofpu_opts(&boot_cpu_data);
158 mips_fpu_disabled = 1;
163 __setup("nofpu", fpu_disable);
165 int mips_dsp_disabled;
167 static int __init dsp_disable(char *s)
169 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
170 mips_dsp_disabled = 1;
175 __setup("nodsp", dsp_disable);
177 static int mips_htw_disabled;
179 static int __init htw_disable(char *s)
181 mips_htw_disabled = 1;
182 cpu_data[0].options &= ~MIPS_CPU_HTW;
183 write_c0_pwctl(read_c0_pwctl() &
184 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
189 __setup("nohtw", htw_disable);
191 static int mips_ftlb_disabled;
192 static int mips_has_ftlb_configured;
194 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
196 static int __init ftlb_disable(char *s)
198 unsigned int config4, mmuextdef;
201 * If the core hasn't done any FTLB configuration, there is nothing
204 if (!mips_has_ftlb_configured)
207 /* Disable it in the boot cpu */
208 if (set_ftlb_enable(&cpu_data[0], 0)) {
209 pr_warn("Can't turn FTLB off\n");
213 back_to_back_c0_hazard();
215 config4 = read_c0_config4();
217 /* Check that FTLB has been disabled */
218 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
219 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
220 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
221 /* This should never happen */
222 pr_warn("FTLB could not be disabled!\n");
226 mips_ftlb_disabled = 1;
227 mips_has_ftlb_configured = 0;
230 * noftlb is mainly used for debug purposes so print
231 * an informative message instead of using pr_debug()
233 pr_info("FTLB has been disabled\n");
236 * Some of these bits are duplicated in the decode_config4.
237 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
238 * once FTLB has been disabled so undo what decode_config4 did.
240 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
241 cpu_data[0].tlbsizeftlbsets;
242 cpu_data[0].tlbsizeftlbsets = 0;
243 cpu_data[0].tlbsizeftlbways = 0;
248 __setup("noftlb", ftlb_disable);
251 static inline void check_errata(void)
253 struct cpuinfo_mips *c = ¤t_cpu_data;
255 switch (current_cpu_type()) {
258 * Erratum "RPS May Cause Incorrect Instruction Execution"
259 * This code only handles VPE0, any SMP/RTOS code
260 * making use of VPE1 will be responsable for that VPE.
262 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
263 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
270 void __init check_bugs32(void)
276 * Probe whether cpu has config register by trying to play with
277 * alternate cache bit and see whether it matters.
278 * It's used by cpu_probe to distinguish between R3000A and R3081.
280 static inline int cpu_has_confreg(void)
282 #ifdef CONFIG_CPU_R3000
283 extern unsigned long r3k_cache_size(unsigned long);
284 unsigned long size1, size2;
285 unsigned long cfg = read_c0_conf();
287 size1 = r3k_cache_size(ST0_ISC);
288 write_c0_conf(cfg ^ R30XX_CONF_AC);
289 size2 = r3k_cache_size(ST0_ISC);
291 return size1 != size2;
297 static inline void set_elf_platform(int cpu, const char *plat)
300 __elf_platform = plat;
303 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
305 #ifdef __NEED_VMBITS_PROBE
306 write_c0_entryhi(0x3fffffffffffe000ULL);
307 back_to_back_c0_hazard();
308 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
312 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
315 case MIPS_CPU_ISA_M64R2:
316 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
317 case MIPS_CPU_ISA_M64R1:
318 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
320 c->isa_level |= MIPS_CPU_ISA_V;
321 case MIPS_CPU_ISA_IV:
322 c->isa_level |= MIPS_CPU_ISA_IV;
323 case MIPS_CPU_ISA_III:
324 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
327 /* R6 incompatible with everything else */
328 case MIPS_CPU_ISA_M64R6:
329 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
330 case MIPS_CPU_ISA_M32R6:
331 c->isa_level |= MIPS_CPU_ISA_M32R6;
332 /* Break here so we don't add incompatible ISAs */
334 case MIPS_CPU_ISA_M32R2:
335 c->isa_level |= MIPS_CPU_ISA_M32R2;
336 case MIPS_CPU_ISA_M32R1:
337 c->isa_level |= MIPS_CPU_ISA_M32R1;
338 case MIPS_CPU_ISA_II:
339 c->isa_level |= MIPS_CPU_ISA_II;
344 static char unknown_isa[] = KERN_ERR \
345 "Unsupported ISA type, c0.config0: %d.";
347 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
350 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
353 * 0 = All TLBWR instructions go to FTLB
354 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
355 * FTLB and 1 goes to the VTLB.
356 * 2 = 7:1: As above with 7:1 ratio.
357 * 3 = 3:1: As above with 3:1 ratio.
359 * Use the linear midpoint as the probability threshold.
361 if (probability >= 12)
363 else if (probability >= 6)
367 * So FTLB is less than 4 times bigger than VTLB.
368 * A 3:1 ratio can still be useful though.
373 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
377 /* It's implementation dependent how the FTLB can be enabled */
378 switch (c->cputype) {
381 /* proAptiv & related cores use Config6 to enable the FTLB */
382 config = read_c0_config6();
383 /* Clear the old probability value */
384 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
387 write_c0_config6(config |
388 (calculate_ftlb_probability(c)
389 << MIPS_CONF6_FTLBP_SHIFT)
390 | MIPS_CONF6_FTLBEN);
393 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
396 /* I6400 & related cores use Config7 to configure FTLB */
397 config = read_c0_config7();
398 /* Clear the old probability value */
399 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
400 write_c0_config7(config | (calculate_ftlb_probability(c)
401 << MIPS_CONF7_FTLBP_SHIFT));
410 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
412 unsigned int config0;
415 config0 = read_c0_config();
418 * Look for Standard TLB or Dual VTLB and FTLB
420 mt = config0 & MIPS_CONF_MT;
421 if (mt == MIPS_CONF_MT_TLB)
422 c->options |= MIPS_CPU_TLB;
423 else if (mt == MIPS_CONF_MT_FTLB)
424 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
426 isa = (config0 & MIPS_CONF_AT) >> 13;
429 switch ((config0 & MIPS_CONF_AR) >> 10) {
431 set_isa(c, MIPS_CPU_ISA_M32R1);
434 set_isa(c, MIPS_CPU_ISA_M32R2);
437 set_isa(c, MIPS_CPU_ISA_M32R6);
444 switch ((config0 & MIPS_CONF_AR) >> 10) {
446 set_isa(c, MIPS_CPU_ISA_M64R1);
449 set_isa(c, MIPS_CPU_ISA_M64R2);
452 set_isa(c, MIPS_CPU_ISA_M64R6);
462 return config0 & MIPS_CONF_M;
465 panic(unknown_isa, config0);
468 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
470 unsigned int config1;
472 config1 = read_c0_config1();
474 if (config1 & MIPS_CONF1_MD)
475 c->ases |= MIPS_ASE_MDMX;
476 if (config1 & MIPS_CONF1_WR)
477 c->options |= MIPS_CPU_WATCH;
478 if (config1 & MIPS_CONF1_CA)
479 c->ases |= MIPS_ASE_MIPS16;
480 if (config1 & MIPS_CONF1_EP)
481 c->options |= MIPS_CPU_EJTAG;
482 if (config1 & MIPS_CONF1_FP) {
483 c->options |= MIPS_CPU_FPU;
484 c->options |= MIPS_CPU_32FPR;
487 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
488 c->tlbsizevtlb = c->tlbsize;
489 c->tlbsizeftlbsets = 0;
492 return config1 & MIPS_CONF_M;
495 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
497 unsigned int config2;
499 config2 = read_c0_config2();
501 if (config2 & MIPS_CONF2_SL)
502 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
504 return config2 & MIPS_CONF_M;
507 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
509 unsigned int config3;
511 config3 = read_c0_config3();
513 if (config3 & MIPS_CONF3_SM) {
514 c->ases |= MIPS_ASE_SMARTMIPS;
515 c->options |= MIPS_CPU_RIXI;
517 if (config3 & MIPS_CONF3_RXI)
518 c->options |= MIPS_CPU_RIXI;
519 if (config3 & MIPS_CONF3_DSP)
520 c->ases |= MIPS_ASE_DSP;
521 if (config3 & MIPS_CONF3_DSP2P)
522 c->ases |= MIPS_ASE_DSP2P;
523 if (config3 & MIPS_CONF3_VINT)
524 c->options |= MIPS_CPU_VINT;
525 if (config3 & MIPS_CONF3_VEIC)
526 c->options |= MIPS_CPU_VEIC;
527 if (config3 & MIPS_CONF3_MT)
528 c->ases |= MIPS_ASE_MIPSMT;
529 if (config3 & MIPS_CONF3_ULRI)
530 c->options |= MIPS_CPU_ULRI;
531 if (config3 & MIPS_CONF3_ISA)
532 c->options |= MIPS_CPU_MICROMIPS;
533 if (config3 & MIPS_CONF3_VZ)
534 c->ases |= MIPS_ASE_VZ;
535 if (config3 & MIPS_CONF3_SC)
536 c->options |= MIPS_CPU_SEGMENTS;
537 if (config3 & MIPS_CONF3_MSA)
538 c->ases |= MIPS_ASE_MSA;
539 /* Only tested on 32-bit cores */
540 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
542 c->options |= MIPS_CPU_HTW;
544 if (config3 & MIPS_CONF3_CDMM)
545 c->options |= MIPS_CPU_CDMM;
546 if (config3 & MIPS_CONF3_SP)
547 c->options |= MIPS_CPU_SP;
549 return config3 & MIPS_CONF_M;
552 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
554 unsigned int config4;
556 unsigned int mmuextdef;
557 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
559 config4 = read_c0_config4();
562 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
563 c->options |= MIPS_CPU_TLBINV;
565 * This is a bit ugly. R6 has dropped that field from
566 * config4 and the only valid configuration is VTLB+FTLB so
567 * set a good value for mmuextdef for that case.
570 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
572 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
575 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
576 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
577 c->tlbsizevtlb = c->tlbsize;
579 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
581 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
582 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
583 c->tlbsize = c->tlbsizevtlb;
584 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
586 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
587 if (mips_ftlb_disabled)
589 newcf4 = (config4 & ~ftlb_page) |
590 (page_size_ftlb(mmuextdef) <<
591 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
592 write_c0_config4(newcf4);
593 back_to_back_c0_hazard();
594 config4 = read_c0_config4();
595 if (config4 != newcf4) {
596 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
598 /* Switch FTLB off */
599 set_ftlb_enable(c, 0);
602 c->tlbsizeftlbsets = 1 <<
603 ((config4 & MIPS_CONF4_FTLBSETS) >>
604 MIPS_CONF4_FTLBSETS_SHIFT);
605 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
606 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
607 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
608 mips_has_ftlb_configured = 1;
613 c->kscratch_mask = (config4 >> 16) & 0xff;
615 return config4 & MIPS_CONF_M;
618 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
620 unsigned int config5;
622 config5 = read_c0_config5();
623 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
624 write_c0_config5(config5);
626 if (config5 & MIPS_CONF5_EVA)
627 c->options |= MIPS_CPU_EVA;
628 if (config5 & MIPS_CONF5_MRP)
629 c->options |= MIPS_CPU_MAAR;
630 if (config5 & MIPS_CONF5_LLB)
631 c->options |= MIPS_CPU_RW_LLB;
633 if (config5 & MIPS_CONF5_MVH)
634 c->options |= MIPS_CPU_XPA;
637 return config5 & MIPS_CONF_M;
640 static void decode_configs(struct cpuinfo_mips *c)
644 /* MIPS32 or MIPS64 compliant CPU. */
645 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
646 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
648 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
650 /* Enable FTLB if present and not disabled */
651 set_ftlb_enable(c, !mips_ftlb_disabled);
653 ok = decode_config0(c); /* Read Config registers. */
654 BUG_ON(!ok); /* Arch spec violation! */
656 ok = decode_config1(c);
658 ok = decode_config2(c);
660 ok = decode_config3(c);
662 ok = decode_config4(c);
664 ok = decode_config5(c);
666 mips_probe_watch_registers(c);
669 /* Enable the RIXI exceptions */
670 set_c0_pagegrain(PG_IEC);
671 back_to_back_c0_hazard();
672 /* Verify the IEC bit is set */
673 if (read_c0_pagegrain() & PG_IEC)
674 c->options |= MIPS_CPU_RIXIEX;
677 #ifndef CONFIG_MIPS_CPS
678 if (cpu_has_mips_r2_r6) {
679 c->core = get_ebase_cpunum();
681 c->core >>= fls(core_nvpes()) - 1;
686 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
689 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
691 switch (c->processor_id & PRID_IMP_MASK) {
693 c->cputype = CPU_R2000;
694 __cpu_name[cpu] = "R2000";
695 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
696 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
699 c->options |= MIPS_CPU_FPU;
703 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
704 if (cpu_has_confreg()) {
705 c->cputype = CPU_R3081E;
706 __cpu_name[cpu] = "R3081";
708 c->cputype = CPU_R3000A;
709 __cpu_name[cpu] = "R3000A";
712 c->cputype = CPU_R3000;
713 __cpu_name[cpu] = "R3000";
715 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
716 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
719 c->options |= MIPS_CPU_FPU;
723 if (read_c0_config() & CONF_SC) {
724 if ((c->processor_id & PRID_REV_MASK) >=
726 c->cputype = CPU_R4400PC;
727 __cpu_name[cpu] = "R4400PC";
729 c->cputype = CPU_R4000PC;
730 __cpu_name[cpu] = "R4000PC";
733 int cca = read_c0_config() & CONF_CM_CMASK;
737 * SC and MC versions can't be reliably told apart,
738 * but only the latter support coherent caching
739 * modes so assume the firmware has set the KSEG0
740 * coherency attribute reasonably (if uncached, we
744 case CONF_CM_CACHABLE_CE:
745 case CONF_CM_CACHABLE_COW:
746 case CONF_CM_CACHABLE_CUW:
753 if ((c->processor_id & PRID_REV_MASK) >=
755 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
756 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
758 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
759 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
763 set_isa(c, MIPS_CPU_ISA_III);
764 c->fpu_msk31 |= FPU_CSR_CONDX;
765 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
766 MIPS_CPU_WATCH | MIPS_CPU_VCE |
770 case PRID_IMP_VR41XX:
771 set_isa(c, MIPS_CPU_ISA_III);
772 c->fpu_msk31 |= FPU_CSR_CONDX;
773 c->options = R4K_OPTS;
775 switch (c->processor_id & 0xf0) {
776 case PRID_REV_VR4111:
777 c->cputype = CPU_VR4111;
778 __cpu_name[cpu] = "NEC VR4111";
780 case PRID_REV_VR4121:
781 c->cputype = CPU_VR4121;
782 __cpu_name[cpu] = "NEC VR4121";
784 case PRID_REV_VR4122:
785 if ((c->processor_id & 0xf) < 0x3) {
786 c->cputype = CPU_VR4122;
787 __cpu_name[cpu] = "NEC VR4122";
789 c->cputype = CPU_VR4181A;
790 __cpu_name[cpu] = "NEC VR4181A";
793 case PRID_REV_VR4130:
794 if ((c->processor_id & 0xf) < 0x4) {
795 c->cputype = CPU_VR4131;
796 __cpu_name[cpu] = "NEC VR4131";
798 c->cputype = CPU_VR4133;
799 c->options |= MIPS_CPU_LLSC;
800 __cpu_name[cpu] = "NEC VR4133";
804 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
805 c->cputype = CPU_VR41XX;
806 __cpu_name[cpu] = "NEC Vr41xx";
811 c->cputype = CPU_R4300;
812 __cpu_name[cpu] = "R4300";
813 set_isa(c, MIPS_CPU_ISA_III);
814 c->fpu_msk31 |= FPU_CSR_CONDX;
815 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
820 c->cputype = CPU_R4600;
821 __cpu_name[cpu] = "R4600";
822 set_isa(c, MIPS_CPU_ISA_III);
823 c->fpu_msk31 |= FPU_CSR_CONDX;
824 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
831 * This processor doesn't have an MMU, so it's not
832 * "real easy" to run Linux on it. It is left purely
833 * for documentation. Commented out because it shares
834 * it's c0_prid id number with the TX3900.
836 c->cputype = CPU_R4650;
837 __cpu_name[cpu] = "R4650";
838 set_isa(c, MIPS_CPU_ISA_III);
839 c->fpu_msk31 |= FPU_CSR_CONDX;
840 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
845 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
846 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
848 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
849 c->cputype = CPU_TX3927;
850 __cpu_name[cpu] = "TX3927";
853 switch (c->processor_id & PRID_REV_MASK) {
854 case PRID_REV_TX3912:
855 c->cputype = CPU_TX3912;
856 __cpu_name[cpu] = "TX3912";
859 case PRID_REV_TX3922:
860 c->cputype = CPU_TX3922;
861 __cpu_name[cpu] = "TX3922";
868 c->cputype = CPU_R4700;
869 __cpu_name[cpu] = "R4700";
870 set_isa(c, MIPS_CPU_ISA_III);
871 c->fpu_msk31 |= FPU_CSR_CONDX;
872 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
877 c->cputype = CPU_TX49XX;
878 __cpu_name[cpu] = "R49XX";
879 set_isa(c, MIPS_CPU_ISA_III);
880 c->fpu_msk31 |= FPU_CSR_CONDX;
881 c->options = R4K_OPTS | MIPS_CPU_LLSC;
882 if (!(c->processor_id & 0x08))
883 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
887 c->cputype = CPU_R5000;
888 __cpu_name[cpu] = "R5000";
889 set_isa(c, MIPS_CPU_ISA_IV);
890 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
895 c->cputype = CPU_R5432;
896 __cpu_name[cpu] = "R5432";
897 set_isa(c, MIPS_CPU_ISA_IV);
898 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
899 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
903 c->cputype = CPU_R5500;
904 __cpu_name[cpu] = "R5500";
905 set_isa(c, MIPS_CPU_ISA_IV);
906 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
907 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
910 case PRID_IMP_NEVADA:
911 c->cputype = CPU_NEVADA;
912 __cpu_name[cpu] = "Nevada";
913 set_isa(c, MIPS_CPU_ISA_IV);
914 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
915 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
919 c->cputype = CPU_R6000;
920 __cpu_name[cpu] = "R6000";
921 set_isa(c, MIPS_CPU_ISA_II);
922 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
923 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
927 case PRID_IMP_R6000A:
928 c->cputype = CPU_R6000A;
929 __cpu_name[cpu] = "R6000A";
930 set_isa(c, MIPS_CPU_ISA_II);
931 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
932 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
936 case PRID_IMP_RM7000:
937 c->cputype = CPU_RM7000;
938 __cpu_name[cpu] = "RM7000";
939 set_isa(c, MIPS_CPU_ISA_IV);
940 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
943 * Undocumented RM7000: Bit 29 in the info register of
944 * the RM7000 v2.0 indicates if the TLB has 48 or 64
947 * 29 1 => 64 entry JTLB
950 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
953 c->cputype = CPU_R8000;
954 __cpu_name[cpu] = "RM8000";
955 set_isa(c, MIPS_CPU_ISA_IV);
956 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
957 MIPS_CPU_FPU | MIPS_CPU_32FPR |
959 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
961 case PRID_IMP_R10000:
962 c->cputype = CPU_R10000;
963 __cpu_name[cpu] = "R10000";
964 set_isa(c, MIPS_CPU_ISA_IV);
965 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
966 MIPS_CPU_FPU | MIPS_CPU_32FPR |
967 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
971 case PRID_IMP_R12000:
972 c->cputype = CPU_R12000;
973 __cpu_name[cpu] = "R12000";
974 set_isa(c, MIPS_CPU_ISA_IV);
975 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
976 MIPS_CPU_FPU | MIPS_CPU_32FPR |
977 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
978 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
981 case PRID_IMP_R14000:
982 if (((c->processor_id >> 4) & 0x0f) > 2) {
983 c->cputype = CPU_R16000;
984 __cpu_name[cpu] = "R16000";
986 c->cputype = CPU_R14000;
987 __cpu_name[cpu] = "R14000";
989 set_isa(c, MIPS_CPU_ISA_IV);
990 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
991 MIPS_CPU_FPU | MIPS_CPU_32FPR |
992 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
993 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
996 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
997 switch (c->processor_id & PRID_REV_MASK) {
998 case PRID_REV_LOONGSON2E:
999 c->cputype = CPU_LOONGSON2;
1000 __cpu_name[cpu] = "ICT Loongson-2";
1001 set_elf_platform(cpu, "loongson2e");
1002 set_isa(c, MIPS_CPU_ISA_III);
1003 c->fpu_msk31 |= FPU_CSR_CONDX;
1005 case PRID_REV_LOONGSON2F:
1006 c->cputype = CPU_LOONGSON2;
1007 __cpu_name[cpu] = "ICT Loongson-2";
1008 set_elf_platform(cpu, "loongson2f");
1009 set_isa(c, MIPS_CPU_ISA_III);
1010 c->fpu_msk31 |= FPU_CSR_CONDX;
1012 case PRID_REV_LOONGSON3A:
1013 c->cputype = CPU_LOONGSON3;
1014 __cpu_name[cpu] = "ICT Loongson-3";
1015 set_elf_platform(cpu, "loongson3a");
1016 set_isa(c, MIPS_CPU_ISA_M64R1);
1018 case PRID_REV_LOONGSON3B_R1:
1019 case PRID_REV_LOONGSON3B_R2:
1020 c->cputype = CPU_LOONGSON3;
1021 __cpu_name[cpu] = "ICT Loongson-3";
1022 set_elf_platform(cpu, "loongson3b");
1023 set_isa(c, MIPS_CPU_ISA_M64R1);
1027 c->options = R4K_OPTS |
1028 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1031 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1033 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1036 c->cputype = CPU_LOONGSON1;
1038 switch (c->processor_id & PRID_REV_MASK) {
1039 case PRID_REV_LOONGSON1B:
1040 __cpu_name[cpu] = "Loongson 1B";
1048 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1050 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1051 switch (c->processor_id & PRID_IMP_MASK) {
1052 case PRID_IMP_QEMU_GENERIC:
1053 c->writecombine = _CACHE_UNCACHED;
1054 c->cputype = CPU_QEMU_GENERIC;
1055 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1058 c->cputype = CPU_4KC;
1059 c->writecombine = _CACHE_UNCACHED;
1060 __cpu_name[cpu] = "MIPS 4Kc";
1063 case PRID_IMP_4KECR2:
1064 c->cputype = CPU_4KEC;
1065 c->writecombine = _CACHE_UNCACHED;
1066 __cpu_name[cpu] = "MIPS 4KEc";
1070 c->cputype = CPU_4KSC;
1071 c->writecombine = _CACHE_UNCACHED;
1072 __cpu_name[cpu] = "MIPS 4KSc";
1075 c->cputype = CPU_5KC;
1076 c->writecombine = _CACHE_UNCACHED;
1077 __cpu_name[cpu] = "MIPS 5Kc";
1080 c->cputype = CPU_5KE;
1081 c->writecombine = _CACHE_UNCACHED;
1082 __cpu_name[cpu] = "MIPS 5KE";
1085 c->cputype = CPU_20KC;
1086 c->writecombine = _CACHE_UNCACHED;
1087 __cpu_name[cpu] = "MIPS 20Kc";
1090 c->cputype = CPU_24K;
1091 c->writecombine = _CACHE_UNCACHED;
1092 __cpu_name[cpu] = "MIPS 24Kc";
1095 c->cputype = CPU_24K;
1096 c->writecombine = _CACHE_UNCACHED;
1097 __cpu_name[cpu] = "MIPS 24KEc";
1100 c->cputype = CPU_25KF;
1101 c->writecombine = _CACHE_UNCACHED;
1102 __cpu_name[cpu] = "MIPS 25Kc";
1105 c->cputype = CPU_34K;
1106 c->writecombine = _CACHE_UNCACHED;
1107 __cpu_name[cpu] = "MIPS 34Kc";
1110 c->cputype = CPU_74K;
1111 c->writecombine = _CACHE_UNCACHED;
1112 __cpu_name[cpu] = "MIPS 74Kc";
1114 case PRID_IMP_M14KC:
1115 c->cputype = CPU_M14KC;
1116 c->writecombine = _CACHE_UNCACHED;
1117 __cpu_name[cpu] = "MIPS M14Kc";
1119 case PRID_IMP_M14KEC:
1120 c->cputype = CPU_M14KEC;
1121 c->writecombine = _CACHE_UNCACHED;
1122 __cpu_name[cpu] = "MIPS M14KEc";
1124 case PRID_IMP_1004K:
1125 c->cputype = CPU_1004K;
1126 c->writecombine = _CACHE_UNCACHED;
1127 __cpu_name[cpu] = "MIPS 1004Kc";
1129 case PRID_IMP_1074K:
1130 c->cputype = CPU_1074K;
1131 c->writecombine = _CACHE_UNCACHED;
1132 __cpu_name[cpu] = "MIPS 1074Kc";
1134 case PRID_IMP_INTERAPTIV_UP:
1135 c->cputype = CPU_INTERAPTIV;
1136 __cpu_name[cpu] = "MIPS interAptiv";
1138 case PRID_IMP_INTERAPTIV_MP:
1139 c->cputype = CPU_INTERAPTIV;
1140 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1142 case PRID_IMP_PROAPTIV_UP:
1143 c->cputype = CPU_PROAPTIV;
1144 __cpu_name[cpu] = "MIPS proAptiv";
1146 case PRID_IMP_PROAPTIV_MP:
1147 c->cputype = CPU_PROAPTIV;
1148 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1150 case PRID_IMP_P5600:
1151 c->cputype = CPU_P5600;
1152 __cpu_name[cpu] = "MIPS P5600";
1154 case PRID_IMP_I6400:
1155 c->cputype = CPU_I6400;
1156 __cpu_name[cpu] = "MIPS I6400";
1158 case PRID_IMP_M5150:
1159 c->cputype = CPU_M5150;
1160 __cpu_name[cpu] = "MIPS M5150";
1169 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1172 switch (c->processor_id & PRID_IMP_MASK) {
1173 case PRID_IMP_AU1_REV1:
1174 case PRID_IMP_AU1_REV2:
1175 c->cputype = CPU_ALCHEMY;
1176 switch ((c->processor_id >> 24) & 0xff) {
1178 __cpu_name[cpu] = "Au1000";
1181 __cpu_name[cpu] = "Au1500";
1184 __cpu_name[cpu] = "Au1100";
1187 __cpu_name[cpu] = "Au1550";
1190 __cpu_name[cpu] = "Au1200";
1191 if ((c->processor_id & PRID_REV_MASK) == 2)
1192 __cpu_name[cpu] = "Au1250";
1195 __cpu_name[cpu] = "Au1210";
1198 __cpu_name[cpu] = "Au1xxx";
1205 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1209 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1210 switch (c->processor_id & PRID_IMP_MASK) {
1212 c->cputype = CPU_SB1;
1213 __cpu_name[cpu] = "SiByte SB1";
1214 /* FPU in pass1 is known to have issues. */
1215 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1216 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1219 c->cputype = CPU_SB1A;
1220 __cpu_name[cpu] = "SiByte SB1A";
1225 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1228 switch (c->processor_id & PRID_IMP_MASK) {
1229 case PRID_IMP_SR71000:
1230 c->cputype = CPU_SR71000;
1231 __cpu_name[cpu] = "Sandcraft SR71000";
1238 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1241 switch (c->processor_id & PRID_IMP_MASK) {
1242 case PRID_IMP_PR4450:
1243 c->cputype = CPU_PR4450;
1244 __cpu_name[cpu] = "Philips PR4450";
1245 set_isa(c, MIPS_CPU_ISA_M32R1);
1250 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1253 switch (c->processor_id & PRID_IMP_MASK) {
1254 case PRID_IMP_BMIPS32_REV4:
1255 case PRID_IMP_BMIPS32_REV8:
1256 c->cputype = CPU_BMIPS32;
1257 __cpu_name[cpu] = "Broadcom BMIPS32";
1258 set_elf_platform(cpu, "bmips32");
1260 case PRID_IMP_BMIPS3300:
1261 case PRID_IMP_BMIPS3300_ALT:
1262 case PRID_IMP_BMIPS3300_BUG:
1263 c->cputype = CPU_BMIPS3300;
1264 __cpu_name[cpu] = "Broadcom BMIPS3300";
1265 set_elf_platform(cpu, "bmips3300");
1267 case PRID_IMP_BMIPS43XX: {
1268 int rev = c->processor_id & PRID_REV_MASK;
1270 if (rev >= PRID_REV_BMIPS4380_LO &&
1271 rev <= PRID_REV_BMIPS4380_HI) {
1272 c->cputype = CPU_BMIPS4380;
1273 __cpu_name[cpu] = "Broadcom BMIPS4380";
1274 set_elf_platform(cpu, "bmips4380");
1276 c->cputype = CPU_BMIPS4350;
1277 __cpu_name[cpu] = "Broadcom BMIPS4350";
1278 set_elf_platform(cpu, "bmips4350");
1282 case PRID_IMP_BMIPS5000:
1283 case PRID_IMP_BMIPS5200:
1284 c->cputype = CPU_BMIPS5000;
1285 __cpu_name[cpu] = "Broadcom BMIPS5000";
1286 set_elf_platform(cpu, "bmips5000");
1287 c->options |= MIPS_CPU_ULRI;
1292 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1295 switch (c->processor_id & PRID_IMP_MASK) {
1296 case PRID_IMP_CAVIUM_CN38XX:
1297 case PRID_IMP_CAVIUM_CN31XX:
1298 case PRID_IMP_CAVIUM_CN30XX:
1299 c->cputype = CPU_CAVIUM_OCTEON;
1300 __cpu_name[cpu] = "Cavium Octeon";
1302 case PRID_IMP_CAVIUM_CN58XX:
1303 case PRID_IMP_CAVIUM_CN56XX:
1304 case PRID_IMP_CAVIUM_CN50XX:
1305 case PRID_IMP_CAVIUM_CN52XX:
1306 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1307 __cpu_name[cpu] = "Cavium Octeon+";
1309 set_elf_platform(cpu, "octeon");
1311 case PRID_IMP_CAVIUM_CN61XX:
1312 case PRID_IMP_CAVIUM_CN63XX:
1313 case PRID_IMP_CAVIUM_CN66XX:
1314 case PRID_IMP_CAVIUM_CN68XX:
1315 case PRID_IMP_CAVIUM_CNF71XX:
1316 c->cputype = CPU_CAVIUM_OCTEON2;
1317 __cpu_name[cpu] = "Cavium Octeon II";
1318 set_elf_platform(cpu, "octeon2");
1320 case PRID_IMP_CAVIUM_CN70XX:
1321 case PRID_IMP_CAVIUM_CN78XX:
1322 c->cputype = CPU_CAVIUM_OCTEON3;
1323 __cpu_name[cpu] = "Cavium Octeon III";
1324 set_elf_platform(cpu, "octeon3");
1327 printk(KERN_INFO "Unknown Octeon chip!\n");
1328 c->cputype = CPU_UNKNOWN;
1333 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1336 /* JZRISC does not implement the CP0 counter. */
1337 c->options &= ~MIPS_CPU_COUNTER;
1338 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1339 switch (c->processor_id & PRID_IMP_MASK) {
1340 case PRID_IMP_JZRISC:
1341 c->cputype = CPU_JZRISC;
1342 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1343 __cpu_name[cpu] = "Ingenic JZRISC";
1346 panic("Unknown Ingenic Processor ID!");
1351 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1355 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1356 c->cputype = CPU_ALCHEMY;
1357 __cpu_name[cpu] = "Au1300";
1358 /* following stuff is not for Alchemy */
1362 c->options = (MIPS_CPU_TLB |
1370 switch (c->processor_id & PRID_IMP_MASK) {
1371 case PRID_IMP_NETLOGIC_XLP2XX:
1372 case PRID_IMP_NETLOGIC_XLP9XX:
1373 case PRID_IMP_NETLOGIC_XLP5XX:
1374 c->cputype = CPU_XLP;
1375 __cpu_name[cpu] = "Broadcom XLPII";
1378 case PRID_IMP_NETLOGIC_XLP8XX:
1379 case PRID_IMP_NETLOGIC_XLP3XX:
1380 c->cputype = CPU_XLP;
1381 __cpu_name[cpu] = "Netlogic XLP";
1384 case PRID_IMP_NETLOGIC_XLR732:
1385 case PRID_IMP_NETLOGIC_XLR716:
1386 case PRID_IMP_NETLOGIC_XLR532:
1387 case PRID_IMP_NETLOGIC_XLR308:
1388 case PRID_IMP_NETLOGIC_XLR532C:
1389 case PRID_IMP_NETLOGIC_XLR516C:
1390 case PRID_IMP_NETLOGIC_XLR508C:
1391 case PRID_IMP_NETLOGIC_XLR308C:
1392 c->cputype = CPU_XLR;
1393 __cpu_name[cpu] = "Netlogic XLR";
1396 case PRID_IMP_NETLOGIC_XLS608:
1397 case PRID_IMP_NETLOGIC_XLS408:
1398 case PRID_IMP_NETLOGIC_XLS404:
1399 case PRID_IMP_NETLOGIC_XLS208:
1400 case PRID_IMP_NETLOGIC_XLS204:
1401 case PRID_IMP_NETLOGIC_XLS108:
1402 case PRID_IMP_NETLOGIC_XLS104:
1403 case PRID_IMP_NETLOGIC_XLS616B:
1404 case PRID_IMP_NETLOGIC_XLS608B:
1405 case PRID_IMP_NETLOGIC_XLS416B:
1406 case PRID_IMP_NETLOGIC_XLS412B:
1407 case PRID_IMP_NETLOGIC_XLS408B:
1408 case PRID_IMP_NETLOGIC_XLS404B:
1409 c->cputype = CPU_XLR;
1410 __cpu_name[cpu] = "Netlogic XLS";
1414 pr_info("Unknown Netlogic chip id [%02x]!\n",
1416 c->cputype = CPU_XLR;
1420 if (c->cputype == CPU_XLP) {
1421 set_isa(c, MIPS_CPU_ISA_M64R2);
1422 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1423 /* This will be updated again after all threads are woken up */
1424 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1426 set_isa(c, MIPS_CPU_ISA_M64R1);
1427 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1429 c->kscratch_mask = 0xf;
1433 /* For use by uaccess.h */
1435 EXPORT_SYMBOL(__ua_limit);
1438 const char *__cpu_name[NR_CPUS];
1439 const char *__elf_platform;
1441 void cpu_probe(void)
1443 struct cpuinfo_mips *c = ¤t_cpu_data;
1444 unsigned int cpu = smp_processor_id();
1446 c->processor_id = PRID_IMP_UNKNOWN;
1447 c->fpu_id = FPIR_IMP_NONE;
1448 c->cputype = CPU_UNKNOWN;
1449 c->writecombine = _CACHE_UNCACHED;
1451 c->fpu_csr31 = FPU_CSR_RN;
1452 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1454 c->processor_id = read_c0_prid();
1455 switch (c->processor_id & PRID_COMP_MASK) {
1456 case PRID_COMP_LEGACY:
1457 cpu_probe_legacy(c, cpu);
1459 case PRID_COMP_MIPS:
1460 cpu_probe_mips(c, cpu);
1462 case PRID_COMP_ALCHEMY:
1463 cpu_probe_alchemy(c, cpu);
1465 case PRID_COMP_SIBYTE:
1466 cpu_probe_sibyte(c, cpu);
1468 case PRID_COMP_BROADCOM:
1469 cpu_probe_broadcom(c, cpu);
1471 case PRID_COMP_SANDCRAFT:
1472 cpu_probe_sandcraft(c, cpu);
1475 cpu_probe_nxp(c, cpu);
1477 case PRID_COMP_CAVIUM:
1478 cpu_probe_cavium(c, cpu);
1480 case PRID_COMP_INGENIC_D0:
1481 case PRID_COMP_INGENIC_D1:
1482 case PRID_COMP_INGENIC_E1:
1483 cpu_probe_ingenic(c, cpu);
1485 case PRID_COMP_NETLOGIC:
1486 cpu_probe_netlogic(c, cpu);
1490 BUG_ON(!__cpu_name[cpu]);
1491 BUG_ON(c->cputype == CPU_UNKNOWN);
1494 * Platform code can force the cpu type to optimize code
1495 * generation. In that case be sure the cpu type is correctly
1496 * manually setup otherwise it could trigger some nasty bugs.
1498 BUG_ON(current_cpu_type() != c->cputype);
1500 if (mips_fpu_disabled)
1501 c->options &= ~MIPS_CPU_FPU;
1503 if (mips_dsp_disabled)
1504 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1506 if (mips_htw_disabled) {
1507 c->options &= ~MIPS_CPU_HTW;
1508 write_c0_pwctl(read_c0_pwctl() &
1509 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1512 if (c->options & MIPS_CPU_FPU)
1513 cpu_set_fpu_opts(c);
1515 cpu_set_nofpu_opts(c);
1517 if (cpu_has_bp_ghist)
1518 write_c0_r10k_diag(read_c0_r10k_diag() |
1521 if (cpu_has_mips_r2_r6) {
1522 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1523 /* R2 has Performance Counter Interrupt indicator */
1524 c->options |= MIPS_CPU_PCI;
1529 if (cpu_has_mips_r6)
1530 elf_hwcap |= HWCAP_MIPS_R6;
1533 c->msa_id = cpu_get_msa_id();
1534 WARN(c->msa_id & MSA_IR_WRPF,
1535 "Vector register partitioning unimplemented!");
1536 elf_hwcap |= HWCAP_MIPS_MSA;
1539 cpu_probe_vmbits(c);
1543 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1547 void cpu_report(void)
1549 struct cpuinfo_mips *c = ¤t_cpu_data;
1551 pr_info("CPU%d revision is: %08x (%s)\n",
1552 smp_processor_id(), c->processor_id, cpu_name_string());
1553 if (c->options & MIPS_CPU_FPU)
1554 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1556 pr_info("MSA revision is: %08x\n", c->msa_id);