arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/fpu.h>
  24 #include <asm/mipsregs.h>
  25 #include <asm/watch.h>
  26 #include <asm/elf.h>
  27 #include <asm/spram.h>
  28 #include <asm/uaccess.h>
  29
  30 /*
  31  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  32  * the implementation of the "wait" feature differs between CPU families. This
  33  * points to the function that implements CPU specific wait.
  34  * The wait instruction stops the pipeline and reduces the power consumption of
  35  * the CPU very much.
  36  */
  37 void (*cpu_wait)(void);
  38 EXPORT_SYMBOL(cpu_wait);
  39
  40 static void r3081_wait(void)
  41 {
  42         unsigned long cfg = read_c0_conf();
  43         write_c0_conf(cfg | R30XX_CONF_HALT);
  44 }
  45
  46 static void r39xx_wait(void)
  47 {
  48         local_irq_disable();
  49         if (!need_resched())
  50                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
  51         local_irq_enable();
  52 }
  53
  54 extern void r4k_wait(void);
  55
  56 /*
  57  * This variant is preferable as it allows testing need_resched and going to
  58  * sleep depending on the outcome atomically.  Unfortunately the "It is
  59  * implementation-dependent whether the pipeline restarts when a non-enabled
  60  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  61  * using this version a gamble.
  62  */
  63 void r4k_wait_irqoff(void)
  64 {
  65         local_irq_disable();
  66         if (!need_resched())
  67                 __asm__("       .set    push            \n"
  68                         "       .set    mips3           \n"
  69                         "       wait                    \n"
  70                         "       .set    pop             \n");
  71         local_irq_enable();
  72         __asm__("       .globl __pastwait       \n"
  73                 "__pastwait:                    \n");
  74 }
  75
  76 /*
  77  * The RM7000 variant has to handle erratum 38.  The workaround is to not
  78  * have any pending stores when the WAIT instruction is executed.
  79  */
  80 static void rm7k_wait_irqoff(void)
  81 {
  82         local_irq_disable();
  83         if (!need_resched())
  84                 __asm__(
  85                 "       .set    push                                    \n"
  86                 "       .set    mips3                                   \n"
  87                 "       .set    noat                                    \n"
  88                 "       mfc0    $1, $12                                 \n"
  89                 "       sync                                            \n"
  90                 "       mtc0    $1, $12         # stalls until W stage  \n"
  91                 "       wait                                            \n"
  92                 "       mtc0    $1, $12         # stalls until W stage  \n"
  93                 "       .set    pop                                     \n");
  94         local_irq_enable();
  95 }
  96
  97 /*
  98  * The Au1xxx wait is available only if using 32khz counter or
  99  * external timer source, but specifically not CP0 Counter.
 100  * alchemy/common/time.c may override cpu_wait!
 101  */
 102 static void au1k_wait(void)
 103 {
 104         __asm__("       .set    mips3                   \n"
 105                 "       cache   0x14, 0(%0)             \n"
 106                 "       cache   0x14, 32(%0)            \n"
 107                 "       sync                            \n"
 108                 "       nop                             \n"
 109                 "       wait                            \n"
 110                 "       nop                             \n"
 111                 "       nop                             \n"
 112                 "       nop                             \n"
 113                 "       nop                             \n"
 114                 "       .set    mips0                   \n"
 115                 : : "r" (au1k_wait));
 116 }
 117
 118 static int __initdata nowait;
 119
 120 static int __init wait_disable(char *s)
 121 {
 122         nowait = 1;
 123
 124         return 1;
 125 }
 126
 127 __setup("nowait", wait_disable);
 128
 129 static int __cpuinitdata mips_fpu_disabled;
 130
 131 static int __init fpu_disable(char *s)
 132 {
 133         cpu_data[0].options &= ~MIPS_CPU_FPU;
 134         mips_fpu_disabled = 1;
 135
 136         return 1;
 137 }
 138
 139 __setup("nofpu", fpu_disable);
 140
 141 int __cpuinitdata mips_dsp_disabled;
 142
 143 static int __init dsp_disable(char *s)
 144 {
 145         cpu_data[0].ases &= ~MIPS_ASE_DSP;
 146         mips_dsp_disabled = 1;
 147
 148         return 1;
 149 }
 150
 151 __setup("nodsp", dsp_disable);
 152
 153 void __init check_wait(void)
 154 {
 155         struct cpuinfo_mips *c = &current_cpu_data;
 156
 157         if (nowait) {
 158                 printk("Wait instruction disabled.\n");
 159                 return;
 160         }
 161
 162         switch (c->cputype) {
 163         case CPU_R3081:
 164         case CPU_R3081E:
 165                 cpu_wait = r3081_wait;
 166                 break;
 167         case CPU_TX3927:
 168                 cpu_wait = r39xx_wait;
 169                 break;
 170         case CPU_R4200:
 171 /*      case CPU_R4300: */
 172         case CPU_R4600:
 173         case CPU_R4640:
 174         case CPU_R4650:
 175         case CPU_R4700:
 176         case CPU_R5000:
 177         case CPU_R5500:
 178         case CPU_NEVADA:
 179         case CPU_4KC:
 180         case CPU_4KEC:
 181         case CPU_4KSC:
 182         case CPU_5KC:
 183         case CPU_25KF:
 184         case CPU_PR4450:
 185         case CPU_BMIPS3300:
 186         case CPU_BMIPS4350:
 187         case CPU_BMIPS4380:
 188         case CPU_BMIPS5000:
 189         case CPU_CAVIUM_OCTEON:
 190         case CPU_CAVIUM_OCTEON_PLUS:
 191         case CPU_CAVIUM_OCTEON2:
 192         case CPU_JZRISC:
 193         case CPU_LOONGSON1:
 194         case CPU_XLR:
 195         case CPU_XLP:
 196                 cpu_wait = r4k_wait;
 197                 break;
 198
 199         case CPU_RM7000:
 200                 cpu_wait = rm7k_wait_irqoff;
 201                 break;
 202
 203         case CPU_M14KC:
 204         case CPU_24K:
 205         case CPU_34K:
 206         case CPU_1004K:
 207                 cpu_wait = r4k_wait;
 208                 if (read_c0_config7() & MIPS_CONF7_WII)
 209                         cpu_wait = r4k_wait_irqoff;
 210                 break;
 211
 212         case CPU_74K:
 213                 cpu_wait = r4k_wait;
 214                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
 215                         cpu_wait = r4k_wait_irqoff;
 216                 break;
 217
 218         case CPU_TX49XX:
 219                 cpu_wait = r4k_wait_irqoff;
 220                 break;
 221         case CPU_ALCHEMY:
 222                 cpu_wait = au1k_wait;
 223                 break;
 224         case CPU_20KC:
 225                 /*
 226                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
 227                  * WAIT on Rev2.0 and Rev3.0 has E16.
 228                  * Rev3.1 WAIT is nop, why bother
 229                  */
 230                 if ((c->processor_id & 0xff) <= 0x64)
 231                         break;
 232
 233                 /*
 234                  * Another rev is incremeting c0_count at a reduced clock
 235                  * rate while in WAIT mode.  So we basically have the choice
 236                  * between using the cp0 timer as clocksource or avoiding
 237                  * the WAIT instruction.  Until more details are known,
 238                  * disable the use of WAIT for 20Kc entirely.
 239                    cpu_wait = r4k_wait;
 240                  */
 241                 break;
 242         case CPU_RM9000:
 243                 if ((c->processor_id & 0x00ff) >= 0x40)
 244                         cpu_wait = r4k_wait;
 245                 break;
 246         default:
 247                 break;
 248         }
 249 }
 250
 251 static inline void check_errata(void)
 252 {
 253         struct cpuinfo_mips *c = &current_cpu_data;
 254
 255         switch (c->cputype) {
 256         case CPU_34K:
 257                 /*
 258                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 259                  * This code only handles VPE0, any SMP/SMTC/RTOS code
 260                  * making use of VPE1 will be responsable for that VPE.
 261                  */
 262                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 263                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 264                 break;
 265         default:
 266                 break;
 267         }
 268 }
 269
 270 void __init check_bugs32(void)
 271 {
 272         check_errata();
 273 }
 274
 275 /*
 276  * Probe whether cpu has config register by trying to play with
 277  * alternate cache bit and see whether it matters.
 278  * It's used by cpu_probe to distinguish between R3000A and R3081.
 279  */
 280 static inline int cpu_has_confreg(void)
 281 {
 282 #ifdef CONFIG_CPU_R3000
 283         extern unsigned long r3k_cache_size(unsigned long);
 284         unsigned long size1, size2;
 285         unsigned long cfg = read_c0_conf();
 286
 287         size1 = r3k_cache_size(ST0_ISC);
 288         write_c0_conf(cfg ^ R30XX_CONF_AC);
 289         size2 = r3k_cache_size(ST0_ISC);
 290         write_c0_conf(cfg);
 291         return size1 != size2;
 292 #else
 293         return 0;
 294 #endif
 295 }
 296
 297 static inline void set_elf_platform(int cpu, const char *plat)
 298 {
 299         if (cpu == 0)
 300                 __elf_platform = plat;
 301 }
 302
 303 /*
 304  * Get the FPU Implementation/Revision.
 305  */
 306 static inline unsigned long cpu_get_fpu_id(void)
 307 {
 308         unsigned long tmp, fpu_id;
 309
 310         tmp = read_c0_status();
 311         __enable_fpu();
 312         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 313         write_c0_status(tmp);
 314         return fpu_id;
 315 }
 316
 317 /*
 318  * Check the CPU has an FPU the official way.
 319  */
 320 static inline int __cpu_has_fpu(void)
 321 {
 322         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 323 }
 324
 325 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 326 {
 327 #ifdef __NEED_VMBITS_PROBE
 328         write_c0_entryhi(0x3fffffffffffe000ULL);
 329         back_to_back_c0_hazard();
 330         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 331 #endif
 332 }
 333
 334 static char unknown_isa[] __cpuinitdata = KERN_ERR \
 335         "Unsupported ISA type, c0.config0: %d.";
 336
 337 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 338 {
 339         unsigned int config0;
 340         int isa;
 341
 342         config0 = read_c0_config();
 343
 344         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 345                 c->options |= MIPS_CPU_TLB;
 346         isa = (config0 & MIPS_CONF_AT) >> 13;
 347         switch (isa) {
 348         case 0:
 349                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 350                 case 0:
 351                         c->isa_level = MIPS_CPU_ISA_M32R1;
 352                         break;
 353                 case 1:
 354                         c->isa_level = MIPS_CPU_ISA_M32R2;
 355                         break;
 356                 default:
 357                         goto unknown;
 358                 }
 359                 break;
 360         case 2:
 361                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 362                 case 0:
 363                         c->isa_level = MIPS_CPU_ISA_M64R1;
 364                         break;
 365                 case 1:
 366                         c->isa_level = MIPS_CPU_ISA_M64R2;
 367                         break;
 368                 default:
 369                         goto unknown;
 370                 }
 371                 break;
 372         default:
 373                 goto unknown;
 374         }
 375
 376         return config0 & MIPS_CONF_M;
 377
 378 unknown:
 379         panic(unknown_isa, config0);
 380 }
 381
 382 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 383 {
 384         unsigned int config1;
 385
 386         config1 = read_c0_config1();
 387
 388         if (config1 & MIPS_CONF1_MD)
 389                 c->ases |= MIPS_ASE_MDMX;
 390         if (config1 & MIPS_CONF1_WR)
 391                 c->options |= MIPS_CPU_WATCH;
 392         if (config1 & MIPS_CONF1_CA)
 393                 c->ases |= MIPS_ASE_MIPS16;
 394         if (config1 & MIPS_CONF1_EP)
 395                 c->options |= MIPS_CPU_EJTAG;
 396         if (config1 & MIPS_CONF1_FP) {
 397                 c->options |= MIPS_CPU_FPU;
 398                 c->options |= MIPS_CPU_32FPR;
 399         }
 400         if (cpu_has_tlb)
 401                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 402
 403         return config1 & MIPS_CONF_M;
 404 }
 405
 406 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 407 {
 408         unsigned int config2;
 409
 410         config2 = read_c0_config2();
 411
 412         if (config2 & MIPS_CONF2_SL)
 413                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 414
 415         return config2 & MIPS_CONF_M;
 416 }
 417
 418 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 419 {
 420         unsigned int config3;
 421
 422         config3 = read_c0_config3();
 423
 424         if (config3 & MIPS_CONF3_SM)
 425                 c->ases |= MIPS_ASE_SMARTMIPS;
 426         if (config3 & MIPS_CONF3_DSP)
 427                 c->ases |= MIPS_ASE_DSP;
 428         if (config3 & MIPS_CONF3_VINT)
 429                 c->options |= MIPS_CPU_VINT;
 430         if (config3 & MIPS_CONF3_VEIC)
 431                 c->options |= MIPS_CPU_VEIC;
 432         if (config3 & MIPS_CONF3_MT)
 433                 c->ases |= MIPS_ASE_MIPSMT;
 434         if (config3 & MIPS_CONF3_ULRI)
 435                 c->options |= MIPS_CPU_ULRI;
 436
 437         return config3 & MIPS_CONF_M;
 438 }
 439
 440 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 441 {
 442         unsigned int config4;
 443
 444         config4 = read_c0_config4();
 445
 446         if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
 447             && cpu_has_tlb)
 448                 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 449
 450         c->kscratch_mask = (config4 >> 16) & 0xff;
 451
 452         return config4 & MIPS_CONF_M;
 453 }
 454
 455 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 456 {
 457         int ok;
 458
 459         /* MIPS32 or MIPS64 compliant CPU.  */
 460         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 461                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 462
 463         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 464
 465         ok = decode_config0(c);                 /* Read Config registers.  */
 466         BUG_ON(!ok);                            /* Arch spec violation!  */
 467         if (ok)
 468                 ok = decode_config1(c);
 469         if (ok)
 470                 ok = decode_config2(c);
 471         if (ok)
 472                 ok = decode_config3(c);
 473         if (ok)
 474                 ok = decode_config4(c);
 475
 476         mips_probe_watch_registers(c);
 477
 478         if (cpu_has_mips_r2)
 479                 c->core = read_c0_ebase() & 0x3ff;
 480 }
 481
 482 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 483                 | MIPS_CPU_COUNTER)
 484
 485 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 486 {
 487         switch (c->processor_id & 0xff00) {
 488         case PRID_IMP_R2000:
 489                 c->cputype = CPU_R2000;
 490                 __cpu_name[cpu] = "R2000";
 491                 c->isa_level = MIPS_CPU_ISA_I;
 492                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 493                              MIPS_CPU_NOFPUEX;
 494                 if (__cpu_has_fpu())
 495                         c->options |= MIPS_CPU_FPU;
 496                 c->tlbsize = 64;
 497                 break;
 498         case PRID_IMP_R3000:
 499                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
 500                         if (cpu_has_confreg()) {
 501                                 c->cputype = CPU_R3081E;
 502                                 __cpu_name[cpu] = "R3081";
 503                         } else {
 504                                 c->cputype = CPU_R3000A;
 505                                 __cpu_name[cpu] = "R3000A";
 506                         }
 507                         break;
 508                 } else {
 509                         c->cputype = CPU_R3000;
 510                         __cpu_name[cpu] = "R3000";
 511                 }
 512                 c->isa_level = MIPS_CPU_ISA_I;
 513                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 514                              MIPS_CPU_NOFPUEX;
 515                 if (__cpu_has_fpu())
 516                         c->options |= MIPS_CPU_FPU;
 517                 c->tlbsize = 64;
 518                 break;
 519         case PRID_IMP_R4000:
 520                 if (read_c0_config() & CONF_SC) {
 521                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 522                                 c->cputype = CPU_R4400PC;
 523                                 __cpu_name[cpu] = "R4400PC";
 524                         } else {
 525                                 c->cputype = CPU_R4000PC;
 526                                 __cpu_name[cpu] = "R4000PC";
 527                         }
 528                 } else {
 529                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 530                                 c->cputype = CPU_R4400SC;
 531                                 __cpu_name[cpu] = "R4400SC";
 532                         } else {
 533                                 c->cputype = CPU_R4000SC;
 534                                 __cpu_name[cpu] = "R4000SC";
 535                         }
 536                 }
 537
 538                 c->isa_level = MIPS_CPU_ISA_III;
 539                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 540                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 541                              MIPS_CPU_LLSC;
 542                 c->tlbsize = 48;
 543                 break;
 544         case PRID_IMP_VR41XX:
 545                 switch (c->processor_id & 0xf0) {
 546                 case PRID_REV_VR4111:
 547                         c->cputype = CPU_VR4111;
 548                         __cpu_name[cpu] = "NEC VR4111";
 549                         break;
 550                 case PRID_REV_VR4121:
 551                         c->cputype = CPU_VR4121;
 552                         __cpu_name[cpu] = "NEC VR4121";
 553                         break;
 554                 case PRID_REV_VR4122:
 555                         if ((c->processor_id & 0xf) < 0x3) {
 556                                 c->cputype = CPU_VR4122;
 557                                 __cpu_name[cpu] = "NEC VR4122";
 558                         } else {
 559                                 c->cputype = CPU_VR4181A;
 560                                 __cpu_name[cpu] = "NEC VR4181A";
 561                         }
 562                         break;
 563                 case PRID_REV_VR4130:
 564                         if ((c->processor_id & 0xf) < 0x4) {
 565                                 c->cputype = CPU_VR4131;
 566                                 __cpu_name[cpu] = "NEC VR4131";
 567                         } else {
 568                                 c->cputype = CPU_VR4133;
 569                                 __cpu_name[cpu] = "NEC VR4133";
 570                         }
 571                         break;
 572                 default:
 573                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 574                         c->cputype = CPU_VR41XX;
 575                         __cpu_name[cpu] = "NEC Vr41xx";
 576                         break;
 577                 }
 578                 c->isa_level = MIPS_CPU_ISA_III;
 579                 c->options = R4K_OPTS;
 580                 c->tlbsize = 32;
 581                 break;
 582         case PRID_IMP_R4300:
 583                 c->cputype = CPU_R4300;
 584                 __cpu_name[cpu] = "R4300";
 585                 c->isa_level = MIPS_CPU_ISA_III;
 586                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 587                              MIPS_CPU_LLSC;
 588                 c->tlbsize = 32;
 589                 break;
 590         case PRID_IMP_R4600:
 591                 c->cputype = CPU_R4600;
 592                 __cpu_name[cpu] = "R4600";
 593                 c->isa_level = MIPS_CPU_ISA_III;
 594                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 595                              MIPS_CPU_LLSC;
 596                 c->tlbsize = 48;
 597                 break;
 598         #if 0
 599         case PRID_IMP_R4650:
 600                 /*
 601                  * This processor doesn't have an MMU, so it's not
 602                  * "real easy" to run Linux on it. It is left purely
 603                  * for documentation.  Commented out because it shares
 604                  * it's c0_prid id number with the TX3900.
 605                  */
 606                 c->cputype = CPU_R4650;
 607                 __cpu_name[cpu] = "R4650";
 608                 c->isa_level = MIPS_CPU_ISA_III;
 609                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 610                 c->tlbsize = 48;
 611                 break;
 612         #endif
 613         case PRID_IMP_TX39:
 614                 c->isa_level = MIPS_CPU_ISA_I;
 615                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 616
 617                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 618                         c->cputype = CPU_TX3927;
 619                         __cpu_name[cpu] = "TX3927";
 620                         c->tlbsize = 64;
 621                 } else {
 622                         switch (c->processor_id & 0xff) {
 623                         case PRID_REV_TX3912:
 624                                 c->cputype = CPU_TX3912;
 625                                 __cpu_name[cpu] = "TX3912";
 626                                 c->tlbsize = 32;
 627                                 break;
 628                         case PRID_REV_TX3922:
 629                                 c->cputype = CPU_TX3922;
 630                                 __cpu_name[cpu] = "TX3922";
 631                                 c->tlbsize = 64;
 632                                 break;
 633                         }
 634                 }
 635                 break;
 636         case PRID_IMP_R4700:
 637                 c->cputype = CPU_R4700;
 638                 __cpu_name[cpu] = "R4700";
 639                 c->isa_level = MIPS_CPU_ISA_III;
 640                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 641                              MIPS_CPU_LLSC;
 642                 c->tlbsize = 48;
 643                 break;
 644         case PRID_IMP_TX49:
 645                 c->cputype = CPU_TX49XX;
 646                 __cpu_name[cpu] = "R49XX";
 647                 c->isa_level = MIPS_CPU_ISA_III;
 648                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 649                 if (!(c->processor_id & 0x08))
 650                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 651                 c->tlbsize = 48;
 652                 break;
 653         case PRID_IMP_R5000:
 654                 c->cputype = CPU_R5000;
 655                 __cpu_name[cpu] = "R5000";
 656                 c->isa_level = MIPS_CPU_ISA_IV;
 657                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 658                              MIPS_CPU_LLSC;
 659                 c->tlbsize = 48;
 660                 break;
 661         case PRID_IMP_R5432:
 662                 c->cputype = CPU_R5432;
 663                 __cpu_name[cpu] = "R5432";
 664                 c->isa_level = MIPS_CPU_ISA_IV;
 665                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 666                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 667                 c->tlbsize = 48;
 668                 break;
 669         case PRID_IMP_R5500:
 670                 c->cputype = CPU_R5500;
 671                 __cpu_name[cpu] = "R5500";
 672                 c->isa_level = MIPS_CPU_ISA_IV;
 673                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 674                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 675                 c->tlbsize = 48;
 676                 break;
 677         case PRID_IMP_NEVADA:
 678                 c->cputype = CPU_NEVADA;
 679                 __cpu_name[cpu] = "Nevada";
 680                 c->isa_level = MIPS_CPU_ISA_IV;
 681                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 682                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 683                 c->tlbsize = 48;
 684                 break;
 685         case PRID_IMP_R6000:
 686                 c->cputype = CPU_R6000;
 687                 __cpu_name[cpu] = "R6000";
 688                 c->isa_level = MIPS_CPU_ISA_II;
 689                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 690                              MIPS_CPU_LLSC;
 691                 c->tlbsize = 32;
 692                 break;
 693         case PRID_IMP_R6000A:
 694                 c->cputype = CPU_R6000A;
 695                 __cpu_name[cpu] = "R6000A";
 696                 c->isa_level = MIPS_CPU_ISA_II;
 697                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 698                              MIPS_CPU_LLSC;
 699                 c->tlbsize = 32;
 700                 break;
 701         case PRID_IMP_RM7000:
 702                 c->cputype = CPU_RM7000;
 703                 __cpu_name[cpu] = "RM7000";
 704                 c->isa_level = MIPS_CPU_ISA_IV;
 705                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 706                              MIPS_CPU_LLSC;
 707                 /*
 708                  * Undocumented RM7000:  Bit 29 in the info register of
 709                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 710                  * entries.
 711                  *
 712                  * 29      1 =>    64 entry JTLB
 713                  *         0 =>    48 entry JTLB
 714                  */
 715                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 716                 break;
 717         case PRID_IMP_RM9000:
 718                 c->cputype = CPU_RM9000;
 719                 __cpu_name[cpu] = "RM9000";
 720                 c->isa_level = MIPS_CPU_ISA_IV;
 721                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 722                              MIPS_CPU_LLSC;
 723                 /*
 724                  * Bit 29 in the info register of the RM9000
 725                  * indicates if the TLB has 48 or 64 entries.
 726                  *
 727                  * 29      1 =>    64 entry JTLB
 728                  *         0 =>    48 entry JTLB
 729                  */
 730                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 731                 break;
 732         case PRID_IMP_R8000:
 733                 c->cputype = CPU_R8000;
 734                 __cpu_name[cpu] = "RM8000";
 735                 c->isa_level = MIPS_CPU_ISA_IV;
 736                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 737                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 738                              MIPS_CPU_LLSC;
 739                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 740                 break;
 741         case PRID_IMP_R10000:
 742                 c->cputype = CPU_R10000;
 743                 __cpu_name[cpu] = "R10000";
 744                 c->isa_level = MIPS_CPU_ISA_IV;
 745                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 746                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 747                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 748                              MIPS_CPU_LLSC;
 749                 c->tlbsize = 64;
 750                 break;
 751         case PRID_IMP_R12000:
 752                 c->cputype = CPU_R12000;
 753                 __cpu_name[cpu] = "R12000";
 754                 c->isa_level = MIPS_CPU_ISA_IV;
 755                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 756                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 757                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 758                              MIPS_CPU_LLSC;
 759                 c->tlbsize = 64;
 760                 break;
 761         case PRID_IMP_R14000:
 762                 c->cputype = CPU_R14000;
 763                 __cpu_name[cpu] = "R14000";
 764                 c->isa_level = MIPS_CPU_ISA_IV;
 765                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 766                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 767                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 768                              MIPS_CPU_LLSC;
 769                 c->tlbsize = 64;
 770                 break;
 771         case PRID_IMP_LOONGSON2:
 772                 c->cputype = CPU_LOONGSON2;
 773                 __cpu_name[cpu] = "ICT Loongson-2";
 774
 775                 switch (c->processor_id & PRID_REV_MASK) {
 776                 case PRID_REV_LOONGSON2E:
 777                         set_elf_platform(cpu, "loongson2e");
 778                         break;
 779                 case PRID_REV_LOONGSON2F:
 780                         set_elf_platform(cpu, "loongson2f");
 781                         break;
 782                 }
 783
 784                 c->isa_level = MIPS_CPU_ISA_III;
 785                 c->options = R4K_OPTS |
 786                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 787                              MIPS_CPU_32FPR;
 788                 c->tlbsize = 64;
 789                 break;
 790         case PRID_IMP_LOONGSON1:
 791                 decode_configs(c);
 792
 793                 c->cputype = CPU_LOONGSON1;
 794
 795                 switch (c->processor_id & PRID_REV_MASK) {
 796                 case PRID_REV_LOONGSON1B:
 797                         __cpu_name[cpu] = "Loongson 1B";
 798                         break;
 799                 }
 800
 801                 break;
 802         }
 803 }
 804
 805 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 806 {
 807         decode_configs(c);
 808         switch (c->processor_id & 0xff00) {
 809         case PRID_IMP_4KC:
 810                 c->cputype = CPU_4KC;
 811                 __cpu_name[cpu] = "MIPS 4Kc";
 812                 break;
 813         case PRID_IMP_4KEC:
 814         case PRID_IMP_4KECR2:
 815                 c->cputype = CPU_4KEC;
 816                 __cpu_name[cpu] = "MIPS 4KEc";
 817                 break;
 818         case PRID_IMP_4KSC:
 819         case PRID_IMP_4KSD:
 820                 c->cputype = CPU_4KSC;
 821                 __cpu_name[cpu] = "MIPS 4KSc";
 822                 break;
 823         case PRID_IMP_5KC:
 824                 c->cputype = CPU_5KC;
 825                 __cpu_name[cpu] = "MIPS 5Kc";
 826                 break;
 827         case PRID_IMP_5KE:
 828                 c->cputype = CPU_5KE;
 829                 __cpu_name[cpu] = "MIPS 5KE";
 830                 break;
 831         case PRID_IMP_20KC:
 832                 c->cputype = CPU_20KC;
 833                 __cpu_name[cpu] = "MIPS 20Kc";
 834                 break;
 835         case PRID_IMP_24K:
 836         case PRID_IMP_24KE:
 837                 c->cputype = CPU_24K;
 838                 __cpu_name[cpu] = "MIPS 24Kc";
 839                 break;
 840         case PRID_IMP_25KF:
 841                 c->cputype = CPU_25KF;
 842                 __cpu_name[cpu] = "MIPS 25Kc";
 843                 break;
 844         case PRID_IMP_34K:
 845                 c->cputype = CPU_34K;
 846                 __cpu_name[cpu] = "MIPS 34Kc";
 847                 break;
 848         case PRID_IMP_74K:
 849                 c->cputype = CPU_74K;
 850                 __cpu_name[cpu] = "MIPS 74Kc";
 851                 break;
 852         case PRID_IMP_M14KC:
 853                 c->cputype = CPU_M14KC;
 854                 __cpu_name[cpu] = "MIPS M14Kc";
 855                 break;
 856         case PRID_IMP_1004K:
 857                 c->cputype = CPU_1004K;
 858                 __cpu_name[cpu] = "MIPS 1004Kc";
 859                 break;
 860         }
 861
 862         spram_config();
 863 }
 864
 865 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 866 {
 867         decode_configs(c);
 868         switch (c->processor_id & 0xff00) {
 869         case PRID_IMP_AU1_REV1:
 870         case PRID_IMP_AU1_REV2:
 871                 c->cputype = CPU_ALCHEMY;
 872                 switch ((c->processor_id >> 24) & 0xff) {
 873                 case 0:
 874                         __cpu_name[cpu] = "Au1000";
 875                         break;
 876                 case 1:
 877                         __cpu_name[cpu] = "Au1500";
 878                         break;
 879                 case 2:
 880                         __cpu_name[cpu] = "Au1100";
 881                         break;
 882                 case 3:
 883                         __cpu_name[cpu] = "Au1550";
 884                         break;
 885                 case 4:
 886                         __cpu_name[cpu] = "Au1200";
 887                         if ((c->processor_id & 0xff) == 2)
 888                                 __cpu_name[cpu] = "Au1250";
 889                         break;
 890                 case 5:
 891                         __cpu_name[cpu] = "Au1210";
 892                         break;
 893                 default:
 894                         __cpu_name[cpu] = "Au1xxx";
 895                         break;
 896                 }
 897                 break;
 898         }
 899 }
 900
 901 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 902 {
 903         decode_configs(c);
 904
 905         switch (c->processor_id & 0xff00) {
 906         case PRID_IMP_SB1:
 907                 c->cputype = CPU_SB1;
 908                 __cpu_name[cpu] = "SiByte SB1";
 909                 /* FPU in pass1 is known to have issues. */
 910                 if ((c->processor_id & 0xff) < 0x02)
 911                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 912                 break;
 913         case PRID_IMP_SB1A:
 914                 c->cputype = CPU_SB1A;
 915                 __cpu_name[cpu] = "SiByte SB1A";
 916                 break;
 917         }
 918 }
 919
 920 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 921 {
 922         decode_configs(c);
 923         switch (c->processor_id & 0xff00) {
 924         case PRID_IMP_SR71000:
 925                 c->cputype = CPU_SR71000;
 926                 __cpu_name[cpu] = "Sandcraft SR71000";
 927                 c->scache.ways = 8;
 928                 c->tlbsize = 64;
 929                 break;
 930         }
 931 }
 932
 933 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 934 {
 935         decode_configs(c);
 936         switch (c->processor_id & 0xff00) {
 937         case PRID_IMP_PR4450:
 938                 c->cputype = CPU_PR4450;
 939                 __cpu_name[cpu] = "Philips PR4450";
 940                 c->isa_level = MIPS_CPU_ISA_M32R1;
 941                 break;
 942         }
 943 }
 944
 945 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 946 {
 947         decode_configs(c);
 948         switch (c->processor_id & 0xff00) {
 949         case PRID_IMP_BMIPS32_REV4:
 950         case PRID_IMP_BMIPS32_REV8:
 951                 c->cputype = CPU_BMIPS32;
 952                 __cpu_name[cpu] = "Broadcom BMIPS32";
 953                 set_elf_platform(cpu, "bmips32");
 954                 break;
 955         case PRID_IMP_BMIPS3300:
 956         case PRID_IMP_BMIPS3300_ALT:
 957         case PRID_IMP_BMIPS3300_BUG:
 958                 c->cputype = CPU_BMIPS3300;
 959                 __cpu_name[cpu] = "Broadcom BMIPS3300";
 960                 set_elf_platform(cpu, "bmips3300");
 961                 break;
 962         case PRID_IMP_BMIPS43XX: {
 963                 int rev = c->processor_id & 0xff;
 964
 965                 if (rev >= PRID_REV_BMIPS4380_LO &&
 966                                 rev <= PRID_REV_BMIPS4380_HI) {
 967                         c->cputype = CPU_BMIPS4380;
 968                         __cpu_name[cpu] = "Broadcom BMIPS4380";
 969                         set_elf_platform(cpu, "bmips4380");
 970                 } else {
 971                         c->cputype = CPU_BMIPS4350;
 972                         __cpu_name[cpu] = "Broadcom BMIPS4350";
 973                         set_elf_platform(cpu, "bmips4350");
 974                 }
 975                 break;
 976         }
 977         case PRID_IMP_BMIPS5000:
 978                 c->cputype = CPU_BMIPS5000;
 979                 __cpu_name[cpu] = "Broadcom BMIPS5000";
 980                 set_elf_platform(cpu, "bmips5000");
 981                 c->options |= MIPS_CPU_ULRI;
 982                 break;
 983         }
 984 }
 985
 986 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 987 {
 988         decode_configs(c);
 989         switch (c->processor_id & 0xff00) {
 990         case PRID_IMP_CAVIUM_CN38XX:
 991         case PRID_IMP_CAVIUM_CN31XX:
 992         case PRID_IMP_CAVIUM_CN30XX:
 993                 c->cputype = CPU_CAVIUM_OCTEON;
 994                 __cpu_name[cpu] = "Cavium Octeon";
 995                 goto platform;
 996         case PRID_IMP_CAVIUM_CN58XX:
 997         case PRID_IMP_CAVIUM_CN56XX:
 998         case PRID_IMP_CAVIUM_CN50XX:
 999         case PRID_IMP_CAVIUM_CN52XX:
1000                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1001                 __cpu_name[cpu] = "Cavium Octeon+";
1002 platform:
1003                 set_elf_platform(cpu, "octeon");
1004                 break;
1005         case PRID_IMP_CAVIUM_CN61XX:
1006         case PRID_IMP_CAVIUM_CN63XX:
1007         case PRID_IMP_CAVIUM_CN66XX:
1008         case PRID_IMP_CAVIUM_CN68XX:
1009                 c->cputype = CPU_CAVIUM_OCTEON2;
1010                 __cpu_name[cpu] = "Cavium Octeon II";
1011                 set_elf_platform(cpu, "octeon2");
1012                 break;
1013         default:
1014                 printk(KERN_INFO "Unknown Octeon chip!\n");
1015                 c->cputype = CPU_UNKNOWN;
1016                 break;
1017         }
1018 }
1019
1020 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1021 {
1022         decode_configs(c);
1023         /* JZRISC does not implement the CP0 counter. */
1024         c->options &= ~MIPS_CPU_COUNTER;
1025         switch (c->processor_id & 0xff00) {
1026         case PRID_IMP_JZRISC:
1027                 c->cputype = CPU_JZRISC;
1028                 __cpu_name[cpu] = "Ingenic JZRISC";
1029                 break;
1030         default:
1031                 panic("Unknown Ingenic Processor ID!");
1032                 break;
1033         }
1034 }
1035
1036 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1037 {
1038         decode_configs(c);
1039
1040         if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1041                 c->cputype = CPU_ALCHEMY;
1042                 __cpu_name[cpu] = "Au1300";
1043                 /* following stuff is not for Alchemy */
1044                 return;
1045         }
1046
1047         c->options = (MIPS_CPU_TLB       |
1048                         MIPS_CPU_4KEX    |
1049                         MIPS_CPU_COUNTER |
1050                         MIPS_CPU_DIVEC   |
1051                         MIPS_CPU_WATCH   |
1052                         MIPS_CPU_EJTAG   |
1053                         MIPS_CPU_LLSC);
1054
1055         switch (c->processor_id & 0xff00) {
1056         case PRID_IMP_NETLOGIC_XLP8XX:
1057         case PRID_IMP_NETLOGIC_XLP3XX:
1058                 c->cputype = CPU_XLP;
1059                 __cpu_name[cpu] = "Netlogic XLP";
1060                 break;
1061
1062         case PRID_IMP_NETLOGIC_XLR732:
1063         case PRID_IMP_NETLOGIC_XLR716:
1064         case PRID_IMP_NETLOGIC_XLR532:
1065         case PRID_IMP_NETLOGIC_XLR308:
1066         case PRID_IMP_NETLOGIC_XLR532C:
1067         case PRID_IMP_NETLOGIC_XLR516C:
1068         case PRID_IMP_NETLOGIC_XLR508C:
1069         case PRID_IMP_NETLOGIC_XLR308C:
1070                 c->cputype = CPU_XLR;
1071                 __cpu_name[cpu] = "Netlogic XLR";
1072                 break;
1073
1074         case PRID_IMP_NETLOGIC_XLS608:
1075         case PRID_IMP_NETLOGIC_XLS408:
1076         case PRID_IMP_NETLOGIC_XLS404:
1077         case PRID_IMP_NETLOGIC_XLS208:
1078         case PRID_IMP_NETLOGIC_XLS204:
1079         case PRID_IMP_NETLOGIC_XLS108:
1080         case PRID_IMP_NETLOGIC_XLS104:
1081         case PRID_IMP_NETLOGIC_XLS616B:
1082         case PRID_IMP_NETLOGIC_XLS608B:
1083         case PRID_IMP_NETLOGIC_XLS416B:
1084         case PRID_IMP_NETLOGIC_XLS412B:
1085         case PRID_IMP_NETLOGIC_XLS408B:
1086         case PRID_IMP_NETLOGIC_XLS404B:
1087                 c->cputype = CPU_XLR;
1088                 __cpu_name[cpu] = "Netlogic XLS";
1089                 break;
1090
1091         default:
1092                 pr_info("Unknown Netlogic chip id [%02x]!\n",
1093                        c->processor_id);
1094                 c->cputype = CPU_XLR;
1095                 break;
1096         }
1097
1098         if (c->cputype == CPU_XLP) {
1099                 c->isa_level = MIPS_CPU_ISA_M64R2;
1100                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1101                 /* This will be updated again after all threads are woken up */
1102                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1103         } else {
1104                 c->isa_level = MIPS_CPU_ISA_M64R1;
1105                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1106         }
1107 }
1108
1109 #ifdef CONFIG_64BIT
1110 /* For use by uaccess.h */
1111 u64 __ua_limit;
1112 EXPORT_SYMBOL(__ua_limit);
1113 #endif
1114
1115 const char *__cpu_name[NR_CPUS];
1116 const char *__elf_platform;
1117
1118 __cpuinit void cpu_probe(void)
1119 {
1120         struct cpuinfo_mips *c = &current_cpu_data;
1121         unsigned int cpu = smp_processor_id();
1122
1123         c->processor_id = PRID_IMP_UNKNOWN;
1124         c->fpu_id       = FPIR_IMP_NONE;
1125         c->cputype      = CPU_UNKNOWN;
1126
1127         c->processor_id = read_c0_prid();
1128         switch (c->processor_id & 0xff0000) {
1129         case PRID_COMP_LEGACY:
1130                 cpu_probe_legacy(c, cpu);
1131                 break;
1132         case PRID_COMP_MIPS:
1133                 cpu_probe_mips(c, cpu);
1134                 break;
1135         case PRID_COMP_ALCHEMY:
1136                 cpu_probe_alchemy(c, cpu);
1137                 break;
1138         case PRID_COMP_SIBYTE:
1139                 cpu_probe_sibyte(c, cpu);
1140                 break;
1141         case PRID_COMP_BROADCOM:
1142                 cpu_probe_broadcom(c, cpu);
1143                 break;
1144         case PRID_COMP_SANDCRAFT:
1145                 cpu_probe_sandcraft(c, cpu);
1146                 break;
1147         case PRID_COMP_NXP:
1148                 cpu_probe_nxp(c, cpu);
1149                 break;
1150         case PRID_COMP_CAVIUM:
1151                 cpu_probe_cavium(c, cpu);
1152                 break;
1153         case PRID_COMP_INGENIC:
1154                 cpu_probe_ingenic(c, cpu);
1155                 break;
1156         case PRID_COMP_NETLOGIC:
1157                 cpu_probe_netlogic(c, cpu);
1158                 break;
1159         }
1160
1161         BUG_ON(!__cpu_name[cpu]);
1162         BUG_ON(c->cputype == CPU_UNKNOWN);
1163
1164         /*
1165          * Platform code can force the cpu type to optimize code
1166          * generation. In that case be sure the cpu type is correctly
1167          * manually setup otherwise it could trigger some nasty bugs.
1168          */
1169         BUG_ON(current_cpu_type() != c->cputype);
1170
1171         if (mips_fpu_disabled)
1172                 c->options &= ~MIPS_CPU_FPU;
1173
1174         if (mips_dsp_disabled)
1175                 c->ases &= ~MIPS_ASE_DSP;
1176
1177         if (c->options & MIPS_CPU_FPU) {
1178                 c->fpu_id = cpu_get_fpu_id();
1179
1180                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1181                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
1182                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
1183                     c->isa_level == MIPS_CPU_ISA_M64R2) {
1184                         if (c->fpu_id & MIPS_FPIR_3D)
1185                                 c->ases |= MIPS_ASE_MIPS3D;
1186                 }
1187         }
1188
1189         if (cpu_has_mips_r2)
1190                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1191         else
1192                 c->srsets = 1;
1193
1194         cpu_probe_vmbits(c);
1195
1196 #ifdef CONFIG_64BIT
1197         if (cpu == 0)
1198                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1199 #endif
1200 }
1201
1202 __cpuinit void cpu_report(void)
1203 {
1204         struct cpuinfo_mips *c = &current_cpu_data;
1205
1206         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1207                c->processor_id, cpu_name_string());
1208         if (c->options & MIPS_CPU_FPU)
1209                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1210 }