2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
11 #include <asm/addrspace.h>
13 #include <asm/asm-offsets.h>
14 #include <asm/asmmacro.h>
15 #include <asm/cacheops.h>
16 #include <asm/mipsregs.h>
17 #include <asm/mipsmtregs.h>
20 #define GCR_CL_COHERENCE_OFS 0x2008
21 #define GCR_CL_ID_OFS 0x2028
28 * Set dest to non-zero if the core supports the MT ASE, else zero. If
29 * MT is not supported then branch to nomt.
31 .macro has_mt dest, nomt
32 mfc0 \dest, CP0_CONFIG
34 mfc0 \dest, CP0_CONFIG, 1
36 mfc0 \dest, CP0_CONFIG, 2
38 mfc0 \dest, CP0_CONFIG, 3
39 andi \dest, \dest, MIPS_CONF3_MT
43 .section .text.cps-vec
46 LEAF(mips_cps_core_entry)
48 * These first 12 bytes will be patched by cps_smp_setup to load the
49 * base address of the CM GCRs into register v1 and the CCA to use into
55 /* Check whether we're here due to an NMI */
72 li t0, ST0_CU1 | ST0_CU0
76 * Clear the bits used to index the caches. Note that the architecture
77 * dictates that writing to any of TagLo or TagHi selects 0 or 2 should
78 * be valid for all MIPS32 CPUs, even those for which said writes are
81 mtc0 zero, CP0_TAGLO, 0
82 mtc0 zero, CP0_TAGHI, 0
83 mtc0 zero, CP0_TAGLO, 2
84 mtc0 zero, CP0_TAGHI, 2
87 /* Primary cache configuration is indicated by Config1 */
88 mfc0 v0, CP0_CONFIG, 1
90 /* Detect I-cache line size */
91 _EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
96 /* Detect I-cache size */
97 _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
103 1: /* At this point t1 == I-cache sets per way */
104 _EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
111 1: cache Index_Store_Tag_I, 0(a0)
117 /* Detect D-cache line size */
118 _EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
123 /* Detect D-cache size */
124 _EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
130 1: /* At this point t1 == D-cache sets per way */
131 _EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
139 1: cache Index_Store_Tag_D, 0(a0)
144 /* Set Kseg0 CCA to that in s0 */
152 /* Enter the coherent domain */
154 sw t0, GCR_CL_COHERENCE_OFS(v1)
163 * We're up, cached & coherent. Perform any further required core-level
166 1: jal mips_cps_core_init
170 * Boot any other VPEs within this core that should be online, and
171 * deactivate this VPE if it should be offline.
173 jal mips_cps_boot_vpes
177 lw t1, VPEBOOTCFG_PC(v0)
178 lw gp, VPEBOOTCFG_GP(v0)
179 lw sp, VPEBOOTCFG_SP(v0)
182 END(mips_cps_core_entry)
216 la k0, ejtag_debug_handler
221 LEAF(mips_cps_core_init)
222 #ifdef CONFIG_MIPS_MT
223 /* Check that the core implements the MT ASE */
230 /* Only allow 1 TC per VPE to execute... */
233 /* ...and for the moment only 1 VPE */
239 /* Enter VPE configuration state */
240 1: mfc0 t0, CP0_MVPCONTROL
241 ori t0, t0, MVPCONTROL_VPC
242 mtc0 t0, CP0_MVPCONTROL
244 /* Retrieve the number of VPEs within the core */
245 mfc0 t0, CP0_MVPCONF0
246 srl t0, t0, MVPCONF0_PVPE_SHIFT
247 andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
250 /* If there's only 1, we're done */
254 /* Loop through each VPE within this core */
257 1: /* Operate on the appropriate TC */
258 mtc0 t5, CP0_VPECONTROL
261 /* Bind TC to VPE (1:1 TC:VPE mapping) */
264 /* Set exclusive TC, non-active, master */
266 sll t1, t5, VPECONF0_XTC_SHIFT
268 mttc0 t0, CP0_VPECONF0
270 /* Set TC non-active, non-allocatable */
271 mttc0 zero, CP0_TCSTATUS
283 /* Leave VPE configuration state */
284 2: mfc0 t0, CP0_MVPCONTROL
285 xori t0, t0, MVPCONTROL_VPC
286 mtc0 t0, CP0_MVPCONTROL
292 END(mips_cps_core_init)
294 LEAF(mips_cps_boot_vpes)
295 /* Retrieve CM base address */
299 /* Calculate a pointer to this cores struct core_boot_config */
300 lw t0, GCR_CL_ID_OFS(t0)
301 li t1, COREBOOTCFG_SIZE
303 la t1, mips_cps_core_bootcfg
307 /* Calculate this VPEs ID. If the core doesn't support MT use 0 */
311 /* Find the number of VPEs present in the core */
312 mfc0 t1, CP0_MVPCONF0
313 srl t1, t1, MVPCONF0_PVPE_SHIFT
314 andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
317 /* Calculate a mask for the VPE ID from EBase.CPUNum */
325 /* Retrieve the VPE ID from EBase.CPUNum */
329 1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
330 li t1, VPEBOOTCFG_SIZE
332 lw t7, COREBOOTCFG_VPECONFIG(t0)
335 #ifdef CONFIG_MIPS_MT
337 /* If the core doesn't support MT then return */
346 1: /* Enter VPE configuration state */
351 1: mfc0 t1, CP0_MVPCONTROL
352 ori t1, t1, MVPCONTROL_VPC
353 mtc0 t1, CP0_MVPCONTROL
356 /* Loop through each VPE */
357 lw t6, COREBOOTCFG_VPEMASK(t0)
361 /* Check whether the VPE should be running. If not, skip it */
366 /* Operate on the appropriate TC */
367 mfc0 t0, CP0_VPECONTROL
368 ori t0, t0, VPECONTROL_TARGTC
369 xori t0, t0, VPECONTROL_TARGTC
371 mtc0 t0, CP0_VPECONTROL
374 /* Skip the VPE if its TC is not halted */
379 /* Calculate a pointer to the VPEs struct vpe_boot_config */
380 li t0, VPEBOOTCFG_SIZE
384 /* Set the TC restart PC */
385 lw t1, VPEBOOTCFG_PC(t0)
386 mttc0 t1, CP0_TCRESTART
388 /* Set the TC stack pointer */
389 lw t1, VPEBOOTCFG_SP(t0)
392 /* Set the TC global pointer */
393 lw t1, VPEBOOTCFG_GP(t0)
396 /* Copy config from this VPE */
400 /* Ensure no software interrupts are pending */
401 mttc0 zero, CP0_CAUSE
402 mttc0 zero, CP0_STATUS
404 /* Set TC active, not interrupt exempt */
405 mftc0 t0, CP0_TCSTATUS
406 li t1, ~TCSTATUS_IXMT
408 ori t0, t0, TCSTATUS_A
409 mttc0 t0, CP0_TCSTATUS
411 /* Clear the TC halt bit */
412 mttc0 zero, CP0_TCHALT
415 mftc0 t0, CP0_VPECONF0
416 ori t0, t0, VPECONF0_VPA
417 mttc0 t0, CP0_VPECONF0
425 /* Leave VPE configuration state */
426 mfc0 t1, CP0_MVPCONTROL
427 xori t1, t1, MVPCONTROL_VPC
428 mtc0 t1, CP0_MVPCONTROL
432 /* Check whether this VPE is meant to be running */
439 /* This VPE should be offline, halt the TC */
448 #endif /* CONFIG_MIPS_MT */
453 END(mips_cps_boot_vpes)
455 #if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)
457 /* Calculate a pointer to this CPUs struct mips_static_suspend_state */
463 la \dest, __per_cpu_offset
466 la \dest, cps_cpu_state
467 addu \dest, \dest, $1
471 LEAF(mips_cps_pm_save)
478 END(mips_cps_pm_save)
480 LEAF(mips_cps_pm_restore)
481 /* Restore CPU state */
483 RESUME_RESTORE_STATIC
484 RESUME_RESTORE_REGS_RETURN
485 END(mips_cps_pm_restore)
487 #endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */