2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
11 #include <asm/addrspace.h>
13 #include <asm/asm-offsets.h>
14 #include <asm/asmmacro.h>
15 #include <asm/cacheops.h>
17 #include <asm/mipsregs.h>
18 #include <asm/mipsmtregs.h>
21 #define GCR_CL_COHERENCE_OFS 0x2008
22 #define GCR_CL_ID_OFS 0x2028
29 * Set dest to non-zero if the core supports the MT ASE, else zero. If
30 * MT is not supported then branch to nomt.
32 .macro has_mt dest, nomt
33 mfc0 \dest, CP0_CONFIG
35 mfc0 \dest, CP0_CONFIG, 1
37 mfc0 \dest, CP0_CONFIG, 2
39 mfc0 \dest, CP0_CONFIG, 3
40 andi \dest, \dest, MIPS_CONF3_MT
44 .section .text.cps-vec
47 LEAF(mips_cps_core_entry)
49 * These first 12 bytes will be patched by cps_smp_setup to load the
50 * base address of the CM GCRs into register v1 and the CCA to use into
56 /* Check whether we're here due to an NMI */
73 li t0, ST0_CU1 | ST0_CU0
77 * Clear the bits used to index the caches. Note that the architecture
78 * dictates that writing to any of TagLo or TagHi selects 0 or 2 should
79 * be valid for all MIPS32 CPUs, even those for which said writes are
82 mtc0 zero, CP0_TAGLO, 0
83 mtc0 zero, CP0_TAGHI, 0
84 mtc0 zero, CP0_TAGLO, 2
85 mtc0 zero, CP0_TAGHI, 2
88 /* Primary cache configuration is indicated by Config1 */
89 mfc0 v0, CP0_CONFIG, 1
91 /* Detect I-cache line size */
92 _EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
97 /* Detect I-cache size */
98 _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
104 1: /* At this point t1 == I-cache sets per way */
105 _EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
112 1: cache Index_Store_Tag_I, 0(a0)
118 /* Detect D-cache line size */
119 _EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
124 /* Detect D-cache size */
125 _EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
131 1: /* At this point t1 == D-cache sets per way */
132 _EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
140 1: cache Index_Store_Tag_D, 0(a0)
145 /* Set Kseg0 CCA to that in s0 */
153 /* Enter the coherent domain */
155 sw t0, GCR_CL_COHERENCE_OFS(v1)
164 * We're up, cached & coherent. Perform any further required core-level
167 1: jal mips_cps_core_init
170 /* Do any EVA initialization if necessary */
174 * Boot any other VPEs within this core that should be online, and
175 * deactivate this VPE if it should be offline.
177 jal mips_cps_boot_vpes
181 lw t1, VPEBOOTCFG_PC(v0)
182 lw gp, VPEBOOTCFG_GP(v0)
183 lw sp, VPEBOOTCFG_SP(v0)
186 END(mips_cps_core_entry)
220 la k0, ejtag_debug_handler
225 LEAF(mips_cps_core_init)
226 #ifdef CONFIG_MIPS_MT
227 /* Check that the core implements the MT ASE */
234 /* Only allow 1 TC per VPE to execute... */
237 /* ...and for the moment only 1 VPE */
243 /* Enter VPE configuration state */
244 1: mfc0 t0, CP0_MVPCONTROL
245 ori t0, t0, MVPCONTROL_VPC
246 mtc0 t0, CP0_MVPCONTROL
248 /* Retrieve the number of VPEs within the core */
249 mfc0 t0, CP0_MVPCONF0
250 srl t0, t0, MVPCONF0_PVPE_SHIFT
251 andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
254 /* If there's only 1, we're done */
258 /* Loop through each VPE within this core */
261 1: /* Operate on the appropriate TC */
262 mtc0 t5, CP0_VPECONTROL
265 /* Bind TC to VPE (1:1 TC:VPE mapping) */
268 /* Set exclusive TC, non-active, master */
270 sll t1, t5, VPECONF0_XTC_SHIFT
272 mttc0 t0, CP0_VPECONF0
274 /* Set TC non-active, non-allocatable */
275 mttc0 zero, CP0_TCSTATUS
287 /* Leave VPE configuration state */
288 2: mfc0 t0, CP0_MVPCONTROL
289 xori t0, t0, MVPCONTROL_VPC
290 mtc0 t0, CP0_MVPCONTROL
296 END(mips_cps_core_init)
298 LEAF(mips_cps_boot_vpes)
299 /* Retrieve CM base address */
303 /* Calculate a pointer to this cores struct core_boot_config */
304 lw t0, GCR_CL_ID_OFS(t0)
305 li t1, COREBOOTCFG_SIZE
307 la t1, mips_cps_core_bootcfg
311 /* Calculate this VPEs ID. If the core doesn't support MT use 0 */
315 /* Find the number of VPEs present in the core */
316 mfc0 t1, CP0_MVPCONF0
317 srl t1, t1, MVPCONF0_PVPE_SHIFT
318 andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
321 /* Calculate a mask for the VPE ID from EBase.CPUNum */
329 /* Retrieve the VPE ID from EBase.CPUNum */
333 1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
334 li t1, VPEBOOTCFG_SIZE
336 lw t7, COREBOOTCFG_VPECONFIG(t0)
339 #ifdef CONFIG_MIPS_MT
341 /* If the core doesn't support MT then return */
350 1: /* Enter VPE configuration state */
355 1: mfc0 t1, CP0_MVPCONTROL
356 ori t1, t1, MVPCONTROL_VPC
357 mtc0 t1, CP0_MVPCONTROL
360 /* Loop through each VPE */
361 lw t6, COREBOOTCFG_VPEMASK(t0)
365 /* Check whether the VPE should be running. If not, skip it */
370 /* Operate on the appropriate TC */
371 mfc0 t0, CP0_VPECONTROL
372 ori t0, t0, VPECONTROL_TARGTC
373 xori t0, t0, VPECONTROL_TARGTC
375 mtc0 t0, CP0_VPECONTROL
378 /* Skip the VPE if its TC is not halted */
383 /* Calculate a pointer to the VPEs struct vpe_boot_config */
384 li t0, VPEBOOTCFG_SIZE
388 /* Set the TC restart PC */
389 lw t1, VPEBOOTCFG_PC(t0)
390 mttc0 t1, CP0_TCRESTART
392 /* Set the TC stack pointer */
393 lw t1, VPEBOOTCFG_SP(t0)
396 /* Set the TC global pointer */
397 lw t1, VPEBOOTCFG_GP(t0)
400 /* Copy config from this VPE */
404 /* Ensure no software interrupts are pending */
405 mttc0 zero, CP0_CAUSE
406 mttc0 zero, CP0_STATUS
408 /* Set TC active, not interrupt exempt */
409 mftc0 t0, CP0_TCSTATUS
410 li t1, ~TCSTATUS_IXMT
412 ori t0, t0, TCSTATUS_A
413 mttc0 t0, CP0_TCSTATUS
415 /* Clear the TC halt bit */
416 mttc0 zero, CP0_TCHALT
419 mftc0 t0, CP0_VPECONF0
420 ori t0, t0, VPECONF0_VPA
421 mttc0 t0, CP0_VPECONF0
429 /* Leave VPE configuration state */
430 mfc0 t1, CP0_MVPCONTROL
431 xori t1, t1, MVPCONTROL_VPC
432 mtc0 t1, CP0_MVPCONTROL
436 /* Check whether this VPE is meant to be running */
443 /* This VPE should be offline, halt the TC */
452 #endif /* CONFIG_MIPS_MT */
457 END(mips_cps_boot_vpes)
459 #if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)
461 /* Calculate a pointer to this CPUs struct mips_static_suspend_state */
467 la \dest, __per_cpu_offset
470 la \dest, cps_cpu_state
471 addu \dest, \dest, $1
475 LEAF(mips_cps_pm_save)
482 END(mips_cps_pm_save)
484 LEAF(mips_cps_pm_restore)
485 /* Restore CPU state */
487 RESUME_RESTORE_STATIC
488 RESUME_RESTORE_REGS_RETURN
489 END(mips_cps_pm_restore)
491 #endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */