2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
7 * Copyright (C) 1996 by Paul M. Antoine
8 * Copyright (C) 1999 Silicon Graphics
9 * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc.
15 #include <linux/types.h>
16 #include <linux/irqflags.h>
18 #include <asm/addrspace.h>
19 #include <asm/barrier.h>
20 #include <asm/cmpxchg.h>
21 #include <asm/cpu-features.h>
23 #include <asm/watch.h>
28 * switch_to(n) should switch tasks to task nr n, first
29 * checking that n isn't the current task, in which case it does nothing.
31 extern asmlinkage void *resume(void *last, void *next, void *next_ti);
35 #ifdef CONFIG_MIPS_MT_FPAFF
38 * Handle the scheduler resume end of FPU affinity management. We do this
39 * inline to try to keep the overhead down. If we have been forced to run on
40 * a "CPU" with an FPU because of a previous high level of FP computation,
41 * but did not actually use the FPU during the most recent time-slice (CU1
42 * isn't set), we undo the restriction on cpus_allowed.
44 * We're not calling set_cpus_allowed() here, because we have no need to
45 * force prompt migration - we're already switching the current CPU to a
49 #define __mips_mt_fpaff_switch_to(prev) \
51 struct thread_info *__prev_ti = task_thread_info(prev); \
54 test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \
55 (!(KSTK_STATUS(prev) & ST0_CU1))) { \
56 clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \
57 prev->cpus_allowed = prev->thread.user_cpus_allowed; \
59 next->thread.emulated_fp = 0; \
63 #define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
66 #ifdef CONFIG_CPU_HAS_LLSC
67 #define __clear_software_ll_bit() do { } while (0)
69 extern unsigned long ll_bit;
71 #define __clear_software_ll_bit() \
77 #define switch_to(prev, next, last) \
79 __mips_mt_fpaff_switch_to(prev); \
82 __clear_software_ll_bit(); \
83 (last) = resume(prev, next, task_thread_info(next)); \
86 #define finish_arch_switch(prev) \
89 __restore_dsp(current); \
90 if (cpu_has_userlocal) \
91 write_c0_userlocal(current_thread_info()->tp_value); \
95 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
99 if (cpu_has_llsc && R10000_LLSC_WAR) {
102 __asm__ __volatile__(
104 "1: ll %0, %3 # xchg_u32 \n"
111 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
112 : "R" (*m), "Jr" (val)
114 } else if (cpu_has_llsc) {
117 __asm__ __volatile__(
119 "1: ll %0, %3 # xchg_u32 \n"
129 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
130 : "R" (*m), "Jr" (val)
135 raw_local_irq_save(flags);
138 raw_local_irq_restore(flags); /* implies memory barrier */
147 static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
151 if (cpu_has_llsc && R10000_LLSC_WAR) {
154 __asm__ __volatile__(
156 "1: lld %0, %3 # xchg_u64 \n"
161 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
162 : "R" (*m), "Jr" (val)
164 } else if (cpu_has_llsc) {
167 __asm__ __volatile__(
169 "1: lld %0, %3 # xchg_u64 \n"
177 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
178 : "R" (*m), "Jr" (val)
183 raw_local_irq_save(flags);
186 raw_local_irq_restore(flags); /* implies memory barrier */
194 extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
195 #define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
198 /* This function doesn't exist, so you'll get a linker error
199 if something tries to do an invalid xchg(). */
200 extern void __xchg_called_with_bad_pointer(void);
202 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
206 return __xchg_u32(ptr, x);
208 return __xchg_u64(ptr, x);
210 __xchg_called_with_bad_pointer();
214 #define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
216 extern void set_handler(unsigned long offset, void *addr, unsigned long len);
217 extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
219 typedef void (*vi_handler_t)(void);
220 extern void *set_vi_handler(int n, vi_handler_t addr);
222 extern void *set_except_vector(int n, void *addr);
223 extern unsigned long ebase;
224 extern void per_cpu_trap_init(void);
227 * See include/asm-ia64/system.h; prevents deadlock on SMP
230 #define __ARCH_WANT_UNLOCKED_CTXSW
232 extern unsigned long arch_align_stack(unsigned long sp);
234 #endif /* _ASM_SYSTEM_H */