arch/mips/include/asm/processor.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 Waldorf GMBH
   7  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
   8  * Copyright (C) 1996 Paul M. Antoine
   9  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  10  */
  11 #ifndef _ASM_PROCESSOR_H
  12 #define _ASM_PROCESSOR_H
  13
  14 #include <linux/cpumask.h>
  15 #include <linux/threads.h>
  16
  17 #include <asm/cachectl.h>
  18 #include <asm/cpu.h>
  19 #include <asm/cpu-info.h>
  20 #include <asm/mipsregs.h>
  21 #include <asm/prefetch.h>
  22
  23 /*
  24  * Return current * instruction pointer ("program counter").
  25  */
  26 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
  27
  28 /*
  29  * System setup and hardware flags..
  30  */
  31 extern void (*cpu_wait)(void);
  32
  33 extern unsigned int vced_count, vcei_count;
  34
  35 /*
  36  * MIPS does have an arch_pick_mmap_layout()
  37  */
  38 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
  39
  40 /*
  41  * A special page (the vdso) is mapped into all processes at the very
  42  * top of the virtual memory space.
  43  */
  44 #define SPECIAL_PAGES_SIZE PAGE_SIZE
  45
  46 #ifdef CONFIG_32BIT
  47 #ifdef CONFIG_KVM_GUEST
  48 /* User space process size is limited to 1GB in KVM Guest Mode */
  49 #define TASK_SIZE       0x3fff8000UL
  50 #else
  51 /*
  52  * User space process size: 2GB. This is hardcoded into a few places,
  53  * so don't change it unless you know what you are doing.
  54  */
  55 #define TASK_SIZE       0x7fff8000UL
  56 #endif
  57
  58 #ifdef __KERNEL__
  59 #define STACK_TOP_MAX   TASK_SIZE
  60 #endif
  61
  62 #define TASK_IS_32BIT_ADDR 1
  63
  64 #endif
  65
  66 #ifdef CONFIG_64BIT
  67 /*
  68  * User space process size: 1TB. This is hardcoded into a few places,
  69  * so don't change it unless you know what you are doing.  TASK_SIZE
  70  * is limited to 1TB by the R4000 architecture; R10000 and better can
  71  * support 16TB; the architectural reserve for future expansion is
  72  * 8192EB ...
  73  */
  74 #define TASK_SIZE32     0x7fff8000UL
  75 #define TASK_SIZE64     0x10000000000UL
  76 #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
  77
  78 #ifdef __KERNEL__
  79 #define STACK_TOP_MAX   TASK_SIZE64
  80 #endif
  81
  82
  83 #define TASK_SIZE_OF(tsk)                                               \
  84         (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
  85
  86 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
  87
  88 #endif
  89
  90 #define STACK_TOP       ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
  91
  92 /*
  93  * This decides where the kernel will search for a free chunk of vm
  94  * space during mmap's.
  95  */
  96 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
  97
  98
  99 #define NUM_FPU_REGS    32
 100
 101 typedef __u64 fpureg_t;
 102
 103 /*
 104  * It would be nice to add some more fields for emulator statistics, but there
 105  * are a number of fixed offsets in offset.h and elsewhere that would have to
 106  * be recalculated by hand.  So the additional information will be private to
 107  * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
 108  */
 109
 110 struct mips_fpu_struct {
 111         fpureg_t        fpr[NUM_FPU_REGS];
 112         unsigned int    fcr31;
 113 };
 114
 115 #define NUM_DSP_REGS   6
 116
 117 typedef __u32 dspreg_t;
 118
 119 struct mips_dsp_state {
 120         dspreg_t        dspr[NUM_DSP_REGS];
 121         unsigned int    dspcontrol;
 122 };
 123
 124 #define INIT_CPUMASK { \
 125         {0,} \
 126 }
 127
 128 struct mips3264_watch_reg_state {
 129         /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
 130            64 bit kernel.  We use unsigned long as it has the same
 131            property. */
 132         unsigned long watchlo[NUM_WATCH_REGS];
 133         /* Only the mask and IRW bits from watchhi. */
 134         u16 watchhi[NUM_WATCH_REGS];
 135 };
 136
 137 union mips_watch_reg_state {
 138         struct mips3264_watch_reg_state mips3264;
 139 };
 140
 141 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 142
 143 struct octeon_cop2_state {
 144         /* DMFC2 rt, 0x0201 */
 145         unsigned long   cop2_crc_iv;
 146         /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
 147         unsigned long   cop2_crc_length;
 148         /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
 149         unsigned long   cop2_crc_poly;
 150         /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
 151         unsigned long   cop2_llm_dat[2];
 152        /* DMFC2 rt, 0x0084 */
 153         unsigned long   cop2_3des_iv;
 154         /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
 155         unsigned long   cop2_3des_key[3];
 156         /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
 157         unsigned long   cop2_3des_result;
 158         /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
 159         unsigned long   cop2_aes_inp0;
 160         /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
 161         unsigned long   cop2_aes_iv[2];
 162         /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
 163          * rt, 0x0107 */
 164         unsigned long   cop2_aes_key[4];
 165         /* DMFC2 rt, 0x0110 */
 166         unsigned long   cop2_aes_keylen;
 167         /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
 168         unsigned long   cop2_aes_result[2];
 169         /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
 170          * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
 171          * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
 172          * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
 173          * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
 174         unsigned long   cop2_hsh_datw[15];
 175         /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
 176          * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
 177          * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
 178         unsigned long   cop2_hsh_ivw[8];
 179         /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
 180         unsigned long   cop2_gfm_mult[2];
 181         /* DMFC2 rt, 0x025E - Pass2 */
 182         unsigned long   cop2_gfm_poly;
 183         /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
 184         unsigned long   cop2_gfm_result[2];
 185 };
 186 #define INIT_OCTEON_COP2 {0,}
 187
 188 struct octeon_cvmseg_state {
 189         unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
 190                             [cpu_dcache_line_size() / sizeof(unsigned long)];
 191 };
 192
 193 #endif
 194
 195 typedef struct {
 196         unsigned long seg;
 197 } mm_segment_t;
 198
 199 #define ARCH_MIN_TASKALIGN      8
 200
 201 struct mips_abi;
 202
 203 /*
 204  * If you change thread_struct remember to change the #defines below too!
 205  */
 206 struct thread_struct {
 207         /* Saved main processor registers. */
 208         unsigned long reg16;
 209         unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
 210         unsigned long reg29, reg30, reg31;
 211
 212         /* Saved cp0 stuff. */
 213         unsigned long cp0_status;
 214
 215         /* Saved fpu/fpu emulator stuff. */
 216         struct mips_fpu_struct fpu;
 217 #ifdef CONFIG_MIPS_MT_FPAFF
 218         /* Emulated instruction count */
 219         unsigned long emulated_fp;
 220         /* Saved per-thread scheduler affinity mask */
 221         cpumask_t user_cpus_allowed;
 222 #endif /* CONFIG_MIPS_MT_FPAFF */
 223
 224         /* Saved state of the DSP ASE, if available. */
 225         struct mips_dsp_state dsp;
 226
 227         /* Saved watch register state, if available. */
 228         union mips_watch_reg_state watch;
 229
 230         /* Other stuff associated with the thread. */
 231         unsigned long cp0_badvaddr;     /* Last user fault */
 232         unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
 233         unsigned long error_code;
 234 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 235     struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
 236     struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
 237 #endif
 238         struct mips_abi *abi;
 239 };
 240
 241 #ifdef CONFIG_MIPS_MT_FPAFF
 242 #define FPAFF_INIT                                              \
 243         .emulated_fp                    = 0,                    \
 244         .user_cpus_allowed              = INIT_CPUMASK,
 245 #else
 246 #define FPAFF_INIT
 247 #endif /* CONFIG_MIPS_MT_FPAFF */
 248
 249 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 250 #define OCTEON_INIT                                             \
 251         .cp2                    = INIT_OCTEON_COP2,
 252 #else
 253 #define OCTEON_INIT
 254 #endif /* CONFIG_CPU_CAVIUM_OCTEON */
 255
 256 #define INIT_THREAD  {                                          \
 257         /*                                                      \
 258          * Saved main processor registers                       \
 259          */                                                     \
 260         .reg16                  = 0,                            \
 261         .reg17                  = 0,                            \
 262         .reg18                  = 0,                            \
 263         .reg19                  = 0,                            \
 264         .reg20                  = 0,                            \
 265         .reg21                  = 0,                            \
 266         .reg22                  = 0,                            \
 267         .reg23                  = 0,                            \
 268         .reg29                  = 0,                            \
 269         .reg30                  = 0,                            \
 270         .reg31                  = 0,                            \
 271         /*                                                      \
 272          * Saved cp0 stuff                                      \
 273          */                                                     \
 274         .cp0_status             = 0,                            \
 275         /*                                                      \
 276          * Saved FPU/FPU emulator stuff                         \
 277          */                                                     \
 278         .fpu                    = {                             \
 279                 .fpr            = {0,},                         \
 280                 .fcr31          = 0,                            \
 281         },                                                      \
 282         /*                                                      \
 283          * FPU affinity state (null if not FPAFF)               \
 284          */                                                     \
 285         FPAFF_INIT                                              \
 286         /*                                                      \
 287          * Saved DSP stuff                                      \
 288          */                                                     \
 289         .dsp                    = {                             \
 290                 .dspr           = {0, },                        \
 291                 .dspcontrol     = 0,                            \
 292         },                                                      \
 293         /*                                                      \
 294          * saved watch register stuff                           \
 295          */                                                     \
 296         .watch = {{{0,},},},                                    \
 297         /*                                                      \
 298          * Other stuff associated with the process              \
 299          */                                                     \
 300         .cp0_badvaddr           = 0,                            \
 301         .cp0_baduaddr           = 0,                            \
 302         .error_code             = 0,                            \
 303         /*                                                      \
 304          * Cavium Octeon specifics (null if not Octeon)         \
 305          */                                                     \
 306         OCTEON_INIT                                             \
 307 }
 308
 309 struct task_struct;
 310
 311 /* Free all resources held by a thread. */
 312 #define release_thread(thread) do { } while(0)
 313
 314 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 315
 316 /*
 317  * Do necessary setup to start up a newly executed thread.
 318  */
 319 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
 320
 321 unsigned long get_wchan(struct task_struct *p);
 322
 323 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
 324                          THREAD_SIZE - 32 - sizeof(struct pt_regs))
 325 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
 326 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
 327 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
 328 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
 329
 330 #define cpu_relax()     barrier()
 331
 332 /*
 333  * Return_address is a replacement for __builtin_return_address(count)
 334  * which on certain architectures cannot reasonably be implemented in GCC
 335  * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
 336  * Note that __builtin_return_address(x>=1) is forbidden because GCC
 337  * aborts compilation on some CPUs.  It's simply not possible to unwind
 338  * some CPU's stackframes.
 339  *
 340  * __builtin_return_address works only for non-leaf functions.  We avoid the
 341  * overhead of a function call by forcing the compiler to save the return
 342  * address register on the stack.
 343  */
 344 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
 345
 346 #ifdef CONFIG_CPU_HAS_PREFETCH
 347
 348 #define ARCH_HAS_PREFETCH
 349 #define prefetch(x) __builtin_prefetch((x), 0, 1)
 350
 351 #define ARCH_HAS_PREFETCHW
 352 #define prefetchw(x) __builtin_prefetch((x), 1, 1)
 353
 354 /*
 355  * See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP
 356  * systems.
 357  */
 358 #define __ARCH_WANT_UNLOCKED_CTXSW
 359
 360 #endif
 361
 362 #endif /* _ASM_PROCESSOR_H */