1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_SRIOX_DEFS_H__
29 #define __CVMX_SRIOX_DEFS_H__
31 #define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
32 #define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
33 #define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
34 #define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
35 #define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull)
36 #define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull)
37 #define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
38 #define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
39 #define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
40 #define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull)
41 #define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull)
42 #define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull)
43 #define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull)
44 #define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull)
45 #define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull)
46 #define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull)
47 #define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull)
48 #define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull)
49 #define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull)
50 #define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull)
51 #define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull)
52 #define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull)
53 #define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull)
54 #define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull)
55 #define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull)
56 #define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
57 #define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
58 #define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
59 #define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
60 #define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
61 #define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull)
62 #define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
63 #define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
64 #define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull)
65 #define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull)
66 #define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull)
67 #define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8)
68 #define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull)
69 #define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull)
70 #define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull)
71 #define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull)
72 #define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull)
73 #define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull)
74 #define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull)
75 #define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull)
76 #define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull)
77 #define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull)
79 union cvmx_sriox_acc_ctrl {
81 struct cvmx_sriox_acc_ctrl_s {
82 #ifdef __BIG_ENDIAN_BITFIELD
83 uint64_t reserved_7_63:57;
87 uint64_t reserved_3_3:1;
95 uint64_t reserved_3_3:1;
99 uint64_t reserved_7_63:57;
102 struct cvmx_sriox_acc_ctrl_cn63xx {
103 #ifdef __BIG_ENDIAN_BITFIELD
104 uint64_t reserved_3_63:61;
105 uint64_t deny_bar2:1;
106 uint64_t deny_bar1:1;
107 uint64_t deny_bar0:1;
109 uint64_t deny_bar0:1;
110 uint64_t deny_bar1:1;
111 uint64_t deny_bar2:1;
112 uint64_t reserved_3_63:61;
115 struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1;
116 struct cvmx_sriox_acc_ctrl_s cn66xx;
119 union cvmx_sriox_asmbly_id {
121 struct cvmx_sriox_asmbly_id_s {
122 #ifdef __BIG_ENDIAN_BITFIELD
123 uint64_t reserved_32_63:32;
125 uint64_t assy_ven:16;
127 uint64_t assy_ven:16;
129 uint64_t reserved_32_63:32;
132 struct cvmx_sriox_asmbly_id_s cn63xx;
133 struct cvmx_sriox_asmbly_id_s cn63xxp1;
134 struct cvmx_sriox_asmbly_id_s cn66xx;
137 union cvmx_sriox_asmbly_info {
139 struct cvmx_sriox_asmbly_info_s {
140 #ifdef __BIG_ENDIAN_BITFIELD
141 uint64_t reserved_32_63:32;
142 uint64_t assy_rev:16;
143 uint64_t reserved_0_15:16;
145 uint64_t reserved_0_15:16;
146 uint64_t assy_rev:16;
147 uint64_t reserved_32_63:32;
150 struct cvmx_sriox_asmbly_info_s cn63xx;
151 struct cvmx_sriox_asmbly_info_s cn63xxp1;
152 struct cvmx_sriox_asmbly_info_s cn66xx;
155 union cvmx_sriox_bell_resp_ctrl {
157 struct cvmx_sriox_bell_resp_ctrl_s {
158 #ifdef __BIG_ENDIAN_BITFIELD
159 uint64_t reserved_6_63:58;
169 uint64_t reserved_6_63:58;
172 struct cvmx_sriox_bell_resp_ctrl_s cn63xx;
173 struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1;
174 struct cvmx_sriox_bell_resp_ctrl_s cn66xx;
177 union cvmx_sriox_bist_status {
179 struct cvmx_sriox_bist_status_s {
180 #ifdef __BIG_ENDIAN_BITFIELD
181 uint64_t reserved_45_63:19;
221 uint64_t reserved_45_63:19;
224 struct cvmx_sriox_bist_status_cn63xx {
225 #ifdef __BIG_ENDIAN_BITFIELD
226 uint64_t reserved_44_63:20;
264 uint64_t reserved_44_63:20;
267 struct cvmx_sriox_bist_status_cn63xxp1 {
268 #ifdef __BIG_ENDIAN_BITFIELD
269 uint64_t reserved_44_63:20;
279 uint64_t reserved_20_23:4;
295 uint64_t reserved_20_23:4;
305 uint64_t reserved_44_63:20;
308 struct cvmx_sriox_bist_status_s cn66xx;
311 union cvmx_sriox_imsg_ctrl {
313 struct cvmx_sriox_imsg_ctrl_s {
314 #ifdef __BIG_ENDIAN_BITFIELD
315 uint64_t reserved_32_63:32;
317 uint64_t reserved_30_30:1;
319 uint64_t reserved_22_23:2;
324 uint64_t reserved_15_15:1;
334 uint64_t reserved_15_15:1;
339 uint64_t reserved_22_23:2;
341 uint64_t reserved_30_30:1;
343 uint64_t reserved_32_63:32;
346 struct cvmx_sriox_imsg_ctrl_s cn63xx;
347 struct cvmx_sriox_imsg_ctrl_s cn63xxp1;
348 struct cvmx_sriox_imsg_ctrl_s cn66xx;
351 union cvmx_sriox_imsg_inst_hdrx {
353 struct cvmx_sriox_imsg_inst_hdrx_s {
354 #ifdef __BIG_ENDIAN_BITFIELD
356 uint64_t reserved_58_62:5;
358 uint64_t reserved_55_55:1;
360 uint64_t reserved_46_47:2;
365 uint64_t reserved_35_41:7;
373 uint64_t reserved_35_41:7;
378 uint64_t reserved_46_47:2;
380 uint64_t reserved_55_55:1;
382 uint64_t reserved_58_62:5;
386 struct cvmx_sriox_imsg_inst_hdrx_s cn63xx;
387 struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1;
388 struct cvmx_sriox_imsg_inst_hdrx_s cn66xx;
391 union cvmx_sriox_imsg_qos_grpx {
393 struct cvmx_sriox_imsg_qos_grpx_s {
394 #ifdef __BIG_ENDIAN_BITFIELD
395 uint64_t reserved_63_63:1;
398 uint64_t reserved_55_55:1;
401 uint64_t reserved_47_47:1;
404 uint64_t reserved_39_39:1;
407 uint64_t reserved_31_31:1;
410 uint64_t reserved_23_23:1;
413 uint64_t reserved_15_15:1;
416 uint64_t reserved_7_7:1;
422 uint64_t reserved_7_7:1;
425 uint64_t reserved_15_15:1;
428 uint64_t reserved_23_23:1;
431 uint64_t reserved_31_31:1;
434 uint64_t reserved_39_39:1;
437 uint64_t reserved_47_47:1;
440 uint64_t reserved_55_55:1;
443 uint64_t reserved_63_63:1;
446 struct cvmx_sriox_imsg_qos_grpx_s cn63xx;
447 struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1;
448 struct cvmx_sriox_imsg_qos_grpx_s cn66xx;
451 union cvmx_sriox_imsg_statusx {
453 struct cvmx_sriox_imsg_statusx_s {
454 #ifdef __BIG_ENDIAN_BITFIELD
460 uint64_t reserved_58_58:1;
472 uint64_t reserved_26_26:1;
486 uint64_t reserved_26_26:1;
498 uint64_t reserved_58_58:1;
506 struct cvmx_sriox_imsg_statusx_s cn63xx;
507 struct cvmx_sriox_imsg_statusx_s cn63xxp1;
508 struct cvmx_sriox_imsg_statusx_s cn66xx;
511 union cvmx_sriox_imsg_vport_thr {
513 struct cvmx_sriox_imsg_vport_thr_s {
514 #ifdef __BIG_ENDIAN_BITFIELD
515 uint64_t reserved_54_63:10;
517 uint64_t reserved_46_47:2;
519 uint64_t reserved_38_39:2;
522 uint64_t reserved_20_30:11;
524 uint64_t reserved_14_15:2;
526 uint64_t reserved_6_7:2;
530 uint64_t reserved_6_7:2;
532 uint64_t reserved_14_15:2;
534 uint64_t reserved_20_30:11;
537 uint64_t reserved_38_39:2;
539 uint64_t reserved_46_47:2;
541 uint64_t reserved_54_63:10;
544 struct cvmx_sriox_imsg_vport_thr_s cn63xx;
545 struct cvmx_sriox_imsg_vport_thr_s cn63xxp1;
546 struct cvmx_sriox_imsg_vport_thr_s cn66xx;
549 union cvmx_sriox_imsg_vport_thr2 {
551 struct cvmx_sriox_imsg_vport_thr2_s {
552 #ifdef __BIG_ENDIAN_BITFIELD
553 uint64_t reserved_46_63:18;
555 uint64_t reserved_38_39:2;
557 uint64_t reserved_0_31:32;
559 uint64_t reserved_0_31:32;
561 uint64_t reserved_38_39:2;
563 uint64_t reserved_46_63:18;
566 struct cvmx_sriox_imsg_vport_thr2_s cn66xx;
569 union cvmx_sriox_int2_enable {
571 struct cvmx_sriox_int2_enable_s {
572 #ifdef __BIG_ENDIAN_BITFIELD
573 uint64_t reserved_1_63:63;
577 uint64_t reserved_1_63:63;
580 struct cvmx_sriox_int2_enable_s cn63xx;
581 struct cvmx_sriox_int2_enable_s cn66xx;
584 union cvmx_sriox_int2_reg {
586 struct cvmx_sriox_int2_reg_s {
587 #ifdef __BIG_ENDIAN_BITFIELD
588 uint64_t reserved_32_63:32;
590 uint64_t reserved_1_30:30;
594 uint64_t reserved_1_30:30;
596 uint64_t reserved_32_63:32;
599 struct cvmx_sriox_int2_reg_s cn63xx;
600 struct cvmx_sriox_int2_reg_s cn66xx;
603 union cvmx_sriox_int_enable {
605 struct cvmx_sriox_int_enable_s {
606 #ifdef __BIG_ENDIAN_BITFIELD
607 uint64_t reserved_27_63:37;
663 uint64_t reserved_27_63:37;
666 struct cvmx_sriox_int_enable_s cn63xx;
667 struct cvmx_sriox_int_enable_cn63xxp1 {
668 #ifdef __BIG_ENDIAN_BITFIELD
669 uint64_t reserved_22_63:42;
715 uint64_t reserved_22_63:42;
718 struct cvmx_sriox_int_enable_s cn66xx;
721 union cvmx_sriox_int_info0 {
723 struct cvmx_sriox_int_info0_s {
724 #ifdef __BIG_ENDIAN_BITFIELD
728 uint64_t reserved_42_47:6;
731 uint64_t reserved_16_28:13;
737 uint64_t reserved_16_28:13;
740 uint64_t reserved_42_47:6;
746 struct cvmx_sriox_int_info0_s cn63xx;
747 struct cvmx_sriox_int_info0_s cn63xxp1;
748 struct cvmx_sriox_int_info0_s cn66xx;
751 union cvmx_sriox_int_info1 {
753 struct cvmx_sriox_int_info1_s {
754 #ifdef __BIG_ENDIAN_BITFIELD
760 struct cvmx_sriox_int_info1_s cn63xx;
761 struct cvmx_sriox_int_info1_s cn63xxp1;
762 struct cvmx_sriox_int_info1_s cn66xx;
765 union cvmx_sriox_int_info2 {
767 struct cvmx_sriox_int_info2_s {
768 #ifdef __BIG_ENDIAN_BITFIELD
794 struct cvmx_sriox_int_info2_s cn63xx;
795 struct cvmx_sriox_int_info2_s cn63xxp1;
796 struct cvmx_sriox_int_info2_s cn66xx;
799 union cvmx_sriox_int_info3 {
801 struct cvmx_sriox_int_info3_s {
802 #ifdef __BIG_ENDIAN_BITFIELD
807 uint64_t reserved_0_7:8;
809 uint64_t reserved_0_7:8;
816 struct cvmx_sriox_int_info3_s cn63xx;
817 struct cvmx_sriox_int_info3_s cn63xxp1;
818 struct cvmx_sriox_int_info3_s cn66xx;
821 union cvmx_sriox_int_reg {
823 struct cvmx_sriox_int_reg_s {
824 #ifdef __BIG_ENDIAN_BITFIELD
825 uint64_t reserved_32_63:32;
827 uint64_t reserved_27_30:4;
883 uint64_t reserved_27_30:4;
885 uint64_t reserved_32_63:32;
888 struct cvmx_sriox_int_reg_s cn63xx;
889 struct cvmx_sriox_int_reg_cn63xxp1 {
890 #ifdef __BIG_ENDIAN_BITFIELD
891 uint64_t reserved_22_63:42;
937 uint64_t reserved_22_63:42;
940 struct cvmx_sriox_int_reg_s cn66xx;
943 union cvmx_sriox_ip_feature {
945 struct cvmx_sriox_ip_feature_s {
946 #ifdef __BIG_ENDIAN_BITFIELD
948 uint64_t reserved_15_31:17;
952 uint64_t reserved_11_11:1;
962 uint64_t reserved_11_11:1;
966 uint64_t reserved_15_31:17;
970 struct cvmx_sriox_ip_feature_cn63xx {
971 #ifdef __BIG_ENDIAN_BITFIELD
973 uint64_t reserved_14_31:18;
976 uint64_t reserved_11_11:1;
986 uint64_t reserved_11_11:1;
989 uint64_t reserved_14_31:18;
993 struct cvmx_sriox_ip_feature_cn63xx cn63xxp1;
994 struct cvmx_sriox_ip_feature_s cn66xx;
997 union cvmx_sriox_mac_buffers {
999 struct cvmx_sriox_mac_buffers_s {
1000 #ifdef __BIG_ENDIAN_BITFIELD
1001 uint64_t reserved_56_63:8;
1003 uint64_t reserved_44_47:4;
1004 uint64_t tx_inuse:4;
1006 uint64_t reserved_24_31:8;
1008 uint64_t reserved_12_15:4;
1009 uint64_t rx_inuse:4;
1013 uint64_t rx_inuse:4;
1014 uint64_t reserved_12_15:4;
1016 uint64_t reserved_24_31:8;
1018 uint64_t tx_inuse:4;
1019 uint64_t reserved_44_47:4;
1021 uint64_t reserved_56_63:8;
1024 struct cvmx_sriox_mac_buffers_s cn63xx;
1025 struct cvmx_sriox_mac_buffers_s cn66xx;
1028 union cvmx_sriox_maint_op {
1030 struct cvmx_sriox_maint_op_s {
1031 #ifdef __BIG_ENDIAN_BITFIELD
1032 uint64_t wr_data:32;
1033 uint64_t reserved_27_31:5;
1043 uint64_t reserved_27_31:5;
1044 uint64_t wr_data:32;
1047 struct cvmx_sriox_maint_op_s cn63xx;
1048 struct cvmx_sriox_maint_op_s cn63xxp1;
1049 struct cvmx_sriox_maint_op_s cn66xx;
1052 union cvmx_sriox_maint_rd_data {
1054 struct cvmx_sriox_maint_rd_data_s {
1055 #ifdef __BIG_ENDIAN_BITFIELD
1056 uint64_t reserved_33_63:31;
1058 uint64_t rd_data:32;
1060 uint64_t rd_data:32;
1062 uint64_t reserved_33_63:31;
1065 struct cvmx_sriox_maint_rd_data_s cn63xx;
1066 struct cvmx_sriox_maint_rd_data_s cn63xxp1;
1067 struct cvmx_sriox_maint_rd_data_s cn66xx;
1070 union cvmx_sriox_mce_tx_ctl {
1072 struct cvmx_sriox_mce_tx_ctl_s {
1073 #ifdef __BIG_ENDIAN_BITFIELD
1074 uint64_t reserved_1_63:63;
1078 uint64_t reserved_1_63:63;
1081 struct cvmx_sriox_mce_tx_ctl_s cn63xx;
1082 struct cvmx_sriox_mce_tx_ctl_s cn63xxp1;
1083 struct cvmx_sriox_mce_tx_ctl_s cn66xx;
1086 union cvmx_sriox_mem_op_ctrl {
1088 struct cvmx_sriox_mem_op_ctrl_s {
1089 #ifdef __BIG_ENDIAN_BITFIELD
1090 uint64_t reserved_10_63:54;
1093 uint64_t reserved_6_7:2;
1103 uint64_t reserved_6_7:2;
1106 uint64_t reserved_10_63:54;
1109 struct cvmx_sriox_mem_op_ctrl_s cn63xx;
1110 struct cvmx_sriox_mem_op_ctrl_s cn63xxp1;
1111 struct cvmx_sriox_mem_op_ctrl_s cn66xx;
1114 union cvmx_sriox_omsg_ctrlx {
1116 struct cvmx_sriox_omsg_ctrlx_s {
1117 #ifdef __BIG_ENDIAN_BITFIELD
1118 uint64_t testmode:1;
1119 uint64_t reserved_37_62:26;
1120 uint64_t silo_max:5;
1121 uint64_t rtry_thr:16;
1123 uint64_t reserved_11_14:4;
1135 uint64_t reserved_11_14:4;
1137 uint64_t rtry_thr:16;
1138 uint64_t silo_max:5;
1139 uint64_t reserved_37_62:26;
1140 uint64_t testmode:1;
1143 struct cvmx_sriox_omsg_ctrlx_s cn63xx;
1144 struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
1145 #ifdef __BIG_ENDIAN_BITFIELD
1146 uint64_t testmode:1;
1147 uint64_t reserved_32_62:31;
1148 uint64_t rtry_thr:16;
1150 uint64_t reserved_11_14:4;
1162 uint64_t reserved_11_14:4;
1164 uint64_t rtry_thr:16;
1165 uint64_t reserved_32_62:31;
1166 uint64_t testmode:1;
1169 struct cvmx_sriox_omsg_ctrlx_s cn66xx;
1172 union cvmx_sriox_omsg_done_countsx {
1174 struct cvmx_sriox_omsg_done_countsx_s {
1175 #ifdef __BIG_ENDIAN_BITFIELD
1176 uint64_t reserved_32_63:32;
1182 uint64_t reserved_32_63:32;
1185 struct cvmx_sriox_omsg_done_countsx_s cn63xx;
1186 struct cvmx_sriox_omsg_done_countsx_s cn66xx;
1189 union cvmx_sriox_omsg_fmp_mrx {
1191 struct cvmx_sriox_omsg_fmp_mrx_s {
1192 #ifdef __BIG_ENDIAN_BITFIELD
1193 uint64_t reserved_15_63:49;
1195 uint64_t ctlr_fmp:1;
1196 uint64_t ctlr_nmp:1;
1202 uint64_t mbox_fmp:1;
1203 uint64_t mbox_nmp:1;
1204 uint64_t mbox_psd:1;
1214 uint64_t mbox_psd:1;
1215 uint64_t mbox_nmp:1;
1216 uint64_t mbox_fmp:1;
1222 uint64_t ctlr_nmp:1;
1223 uint64_t ctlr_fmp:1;
1225 uint64_t reserved_15_63:49;
1228 struct cvmx_sriox_omsg_fmp_mrx_s cn63xx;
1229 struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1;
1230 struct cvmx_sriox_omsg_fmp_mrx_s cn66xx;
1233 union cvmx_sriox_omsg_nmp_mrx {
1235 struct cvmx_sriox_omsg_nmp_mrx_s {
1236 #ifdef __BIG_ENDIAN_BITFIELD
1237 uint64_t reserved_15_63:49;
1239 uint64_t ctlr_fmp:1;
1240 uint64_t ctlr_nmp:1;
1244 uint64_t reserved_8_8:1;
1246 uint64_t mbox_fmp:1;
1247 uint64_t mbox_nmp:1;
1248 uint64_t reserved_4_4:1;
1252 uint64_t reserved_0_0:1;
1254 uint64_t reserved_0_0:1;
1258 uint64_t reserved_4_4:1;
1259 uint64_t mbox_nmp:1;
1260 uint64_t mbox_fmp:1;
1262 uint64_t reserved_8_8:1;
1266 uint64_t ctlr_nmp:1;
1267 uint64_t ctlr_fmp:1;
1269 uint64_t reserved_15_63:49;
1272 struct cvmx_sriox_omsg_nmp_mrx_s cn63xx;
1273 struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1;
1274 struct cvmx_sriox_omsg_nmp_mrx_s cn66xx;
1277 union cvmx_sriox_omsg_portx {
1279 struct cvmx_sriox_omsg_portx_s {
1280 #ifdef __BIG_ENDIAN_BITFIELD
1281 uint64_t reserved_32_63:32;
1283 uint64_t reserved_3_30:28;
1287 uint64_t reserved_3_30:28;
1289 uint64_t reserved_32_63:32;
1292 struct cvmx_sriox_omsg_portx_cn63xx {
1293 #ifdef __BIG_ENDIAN_BITFIELD
1294 uint64_t reserved_32_63:32;
1296 uint64_t reserved_2_30:29;
1300 uint64_t reserved_2_30:29;
1302 uint64_t reserved_32_63:32;
1305 struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1;
1306 struct cvmx_sriox_omsg_portx_s cn66xx;
1309 union cvmx_sriox_omsg_silo_thr {
1311 struct cvmx_sriox_omsg_silo_thr_s {
1312 #ifdef __BIG_ENDIAN_BITFIELD
1313 uint64_t reserved_5_63:59;
1314 uint64_t tot_silo:5;
1316 uint64_t tot_silo:5;
1317 uint64_t reserved_5_63:59;
1320 struct cvmx_sriox_omsg_silo_thr_s cn63xx;
1321 struct cvmx_sriox_omsg_silo_thr_s cn66xx;
1324 union cvmx_sriox_omsg_sp_mrx {
1326 struct cvmx_sriox_omsg_sp_mrx_s {
1327 #ifdef __BIG_ENDIAN_BITFIELD
1328 uint64_t reserved_16_63:48;
1329 uint64_t xmbox_sp:1;
1331 uint64_t ctlr_fmp:1;
1332 uint64_t ctlr_nmp:1;
1338 uint64_t mbox_fmp:1;
1339 uint64_t mbox_nmp:1;
1340 uint64_t mbox_psd:1;
1350 uint64_t mbox_psd:1;
1351 uint64_t mbox_nmp:1;
1352 uint64_t mbox_fmp:1;
1358 uint64_t ctlr_nmp:1;
1359 uint64_t ctlr_fmp:1;
1361 uint64_t xmbox_sp:1;
1362 uint64_t reserved_16_63:48;
1365 struct cvmx_sriox_omsg_sp_mrx_s cn63xx;
1366 struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1;
1367 struct cvmx_sriox_omsg_sp_mrx_s cn66xx;
1370 union cvmx_sriox_priox_in_use {
1372 struct cvmx_sriox_priox_in_use_s {
1373 #ifdef __BIG_ENDIAN_BITFIELD
1374 uint64_t reserved_32_63:32;
1375 uint64_t end_cnt:16;
1376 uint64_t start_cnt:16;
1378 uint64_t start_cnt:16;
1379 uint64_t end_cnt:16;
1380 uint64_t reserved_32_63:32;
1383 struct cvmx_sriox_priox_in_use_s cn63xx;
1384 struct cvmx_sriox_priox_in_use_s cn66xx;
1387 union cvmx_sriox_rx_bell {
1389 struct cvmx_sriox_rx_bell_s {
1390 #ifdef __BIG_ENDIAN_BITFIELD
1391 uint64_t reserved_48_63:16;
1395 uint64_t reserved_5_7:3;
1398 uint64_t reserved_2_2:1;
1399 uint64_t priority:2;
1401 uint64_t priority:2;
1402 uint64_t reserved_2_2:1;
1405 uint64_t reserved_5_7:3;
1409 uint64_t reserved_48_63:16;
1412 struct cvmx_sriox_rx_bell_s cn63xx;
1413 struct cvmx_sriox_rx_bell_s cn63xxp1;
1414 struct cvmx_sriox_rx_bell_s cn66xx;
1417 union cvmx_sriox_rx_bell_seq {
1419 struct cvmx_sriox_rx_bell_seq_s {
1420 #ifdef __BIG_ENDIAN_BITFIELD
1421 uint64_t reserved_40_63:24;
1427 uint64_t reserved_40_63:24;
1430 struct cvmx_sriox_rx_bell_seq_s cn63xx;
1431 struct cvmx_sriox_rx_bell_seq_s cn63xxp1;
1432 struct cvmx_sriox_rx_bell_seq_s cn66xx;
1435 union cvmx_sriox_rx_status {
1437 struct cvmx_sriox_rx_status_s {
1438 #ifdef __BIG_ENDIAN_BITFIELD
1442 uint64_t reserved_28_39:12;
1445 uint64_t reserved_13_15:3;
1451 uint64_t reserved_13_15:3;
1454 uint64_t reserved_28_39:12;
1460 struct cvmx_sriox_rx_status_s cn63xx;
1461 struct cvmx_sriox_rx_status_s cn63xxp1;
1462 struct cvmx_sriox_rx_status_s cn66xx;
1465 union cvmx_sriox_s2m_typex {
1467 struct cvmx_sriox_s2m_typex_s {
1468 #ifdef __BIG_ENDIAN_BITFIELD
1469 uint64_t reserved_19_63:45;
1471 uint64_t reserved_15_15:1;
1473 uint64_t wr_prior:2;
1474 uint64_t rd_prior:2;
1475 uint64_t reserved_6_7:2;
1478 uint64_t reserved_2_3:2;
1479 uint64_t iaow_sel:2;
1481 uint64_t iaow_sel:2;
1482 uint64_t reserved_2_3:2;
1485 uint64_t reserved_6_7:2;
1486 uint64_t rd_prior:2;
1487 uint64_t wr_prior:2;
1489 uint64_t reserved_15_15:1;
1491 uint64_t reserved_19_63:45;
1494 struct cvmx_sriox_s2m_typex_s cn63xx;
1495 struct cvmx_sriox_s2m_typex_s cn63xxp1;
1496 struct cvmx_sriox_s2m_typex_s cn66xx;
1499 union cvmx_sriox_seq {
1501 struct cvmx_sriox_seq_s {
1502 #ifdef __BIG_ENDIAN_BITFIELD
1503 uint64_t reserved_32_63:32;
1507 uint64_t reserved_32_63:32;
1510 struct cvmx_sriox_seq_s cn63xx;
1511 struct cvmx_sriox_seq_s cn63xxp1;
1512 struct cvmx_sriox_seq_s cn66xx;
1515 union cvmx_sriox_status_reg {
1517 struct cvmx_sriox_status_reg_s {
1518 #ifdef __BIG_ENDIAN_BITFIELD
1519 uint64_t reserved_2_63:62;
1525 uint64_t reserved_2_63:62;
1528 struct cvmx_sriox_status_reg_s cn63xx;
1529 struct cvmx_sriox_status_reg_s cn63xxp1;
1530 struct cvmx_sriox_status_reg_s cn66xx;
1533 union cvmx_sriox_tag_ctrl {
1535 struct cvmx_sriox_tag_ctrl_s {
1536 #ifdef __BIG_ENDIAN_BITFIELD
1537 uint64_t reserved_17_63:47;
1539 uint64_t reserved_13_15:3;
1541 uint64_t reserved_5_7:3;
1545 uint64_t reserved_5_7:3;
1547 uint64_t reserved_13_15:3;
1549 uint64_t reserved_17_63:47;
1552 struct cvmx_sriox_tag_ctrl_s cn63xx;
1553 struct cvmx_sriox_tag_ctrl_s cn63xxp1;
1554 struct cvmx_sriox_tag_ctrl_s cn66xx;
1557 union cvmx_sriox_tlp_credits {
1559 struct cvmx_sriox_tlp_credits_s {
1560 #ifdef __BIG_ENDIAN_BITFIELD
1561 uint64_t reserved_28_63:36;
1564 uint64_t reserved_13_15:3;
1570 uint64_t reserved_13_15:3;
1573 uint64_t reserved_28_63:36;
1576 struct cvmx_sriox_tlp_credits_s cn63xx;
1577 struct cvmx_sriox_tlp_credits_s cn63xxp1;
1578 struct cvmx_sriox_tlp_credits_s cn66xx;
1581 union cvmx_sriox_tx_bell {
1583 struct cvmx_sriox_tx_bell_s {
1584 #ifdef __BIG_ENDIAN_BITFIELD
1585 uint64_t reserved_48_63:16;
1587 uint64_t dest_id:16;
1588 uint64_t reserved_9_15:7;
1590 uint64_t reserved_5_7:3;
1593 uint64_t reserved_2_2:1;
1594 uint64_t priority:2;
1596 uint64_t priority:2;
1597 uint64_t reserved_2_2:1;
1600 uint64_t reserved_5_7:3;
1602 uint64_t reserved_9_15:7;
1603 uint64_t dest_id:16;
1605 uint64_t reserved_48_63:16;
1608 struct cvmx_sriox_tx_bell_s cn63xx;
1609 struct cvmx_sriox_tx_bell_s cn63xxp1;
1610 struct cvmx_sriox_tx_bell_s cn66xx;
1613 union cvmx_sriox_tx_bell_info {
1615 struct cvmx_sriox_tx_bell_info_s {
1616 #ifdef __BIG_ENDIAN_BITFIELD
1617 uint64_t reserved_48_63:16;
1619 uint64_t dest_id:16;
1620 uint64_t reserved_8_15:8;
1626 uint64_t reserved_2_2:1;
1627 uint64_t priority:2;
1629 uint64_t priority:2;
1630 uint64_t reserved_2_2:1;
1636 uint64_t reserved_8_15:8;
1637 uint64_t dest_id:16;
1639 uint64_t reserved_48_63:16;
1642 struct cvmx_sriox_tx_bell_info_s cn63xx;
1643 struct cvmx_sriox_tx_bell_info_s cn63xxp1;
1644 struct cvmx_sriox_tx_bell_info_s cn66xx;
1647 union cvmx_sriox_tx_ctrl {
1649 struct cvmx_sriox_tx_ctrl_s {
1650 #ifdef __BIG_ENDIAN_BITFIELD
1651 uint64_t reserved_53_63:11;
1653 uint64_t reserved_45_47:3;
1655 uint64_t reserved_37_39:3;
1657 uint64_t reserved_20_31:12;
1659 uint64_t reserved_12_15:4;
1661 uint64_t reserved_4_7:4;
1665 uint64_t reserved_4_7:4;
1667 uint64_t reserved_12_15:4;
1669 uint64_t reserved_20_31:12;
1671 uint64_t reserved_37_39:3;
1673 uint64_t reserved_45_47:3;
1675 uint64_t reserved_53_63:11;
1678 struct cvmx_sriox_tx_ctrl_s cn63xx;
1679 struct cvmx_sriox_tx_ctrl_s cn63xxp1;
1680 struct cvmx_sriox_tx_ctrl_s cn66xx;
1683 union cvmx_sriox_tx_emphasis {
1685 struct cvmx_sriox_tx_emphasis_s {
1686 #ifdef __BIG_ENDIAN_BITFIELD
1687 uint64_t reserved_4_63:60;
1691 uint64_t reserved_4_63:60;
1694 struct cvmx_sriox_tx_emphasis_s cn63xx;
1695 struct cvmx_sriox_tx_emphasis_s cn66xx;
1698 union cvmx_sriox_tx_status {
1700 struct cvmx_sriox_tx_status_s {
1701 #ifdef __BIG_ENDIAN_BITFIELD
1702 uint64_t reserved_32_63:32;
1712 uint64_t reserved_32_63:32;
1715 struct cvmx_sriox_tx_status_s cn63xx;
1716 struct cvmx_sriox_tx_status_s cn63xxp1;
1717 struct cvmx_sriox_tx_status_s cn66xx;
1720 union cvmx_sriox_wr_done_counts {
1722 struct cvmx_sriox_wr_done_counts_s {
1723 #ifdef __BIG_ENDIAN_BITFIELD
1724 uint64_t reserved_32_63:32;
1730 uint64_t reserved_32_63:32;
1733 struct cvmx_sriox_wr_done_counts_s cn63xx;
1734 struct cvmx_sriox_wr_done_counts_s cn66xx;