arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/war.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #else
  38 #define _ULCAST_ (unsigned long)
  39 #endif
  40
  41 /*
  42  * Coprocessor 0 register names
  43  */
  44 #define CP0_INDEX $0
  45 #define CP0_RANDOM $1
  46 #define CP0_ENTRYLO0 $2
  47 #define CP0_ENTRYLO1 $3
  48 #define CP0_CONF $3
  49 #define CP0_CONTEXT $4
  50 #define CP0_PAGEMASK $5
  51 #define CP0_WIRED $6
  52 #define CP0_INFO $7
  53 #define CP0_BADVADDR $8
  54 #define CP0_COUNT $9
  55 #define CP0_ENTRYHI $10
  56 #define CP0_COMPARE $11
  57 #define CP0_STATUS $12
  58 #define CP0_CAUSE $13
  59 #define CP0_EPC $14
  60 #define CP0_PRID $15
  61 #define CP0_CONFIG $16
  62 #define CP0_LLADDR $17
  63 #define CP0_WATCHLO $18
  64 #define CP0_WATCHHI $19
  65 #define CP0_XCONTEXT $20
  66 #define CP0_FRAMEMASK $21
  67 #define CP0_DIAGNOSTIC $22
  68 #define CP0_DEBUG $23
  69 #define CP0_DEPC $24
  70 #define CP0_PERFORMANCE $25
  71 #define CP0_ECC $26
  72 #define CP0_CACHEERR $27
  73 #define CP0_TAGLO $28
  74 #define CP0_TAGHI $29
  75 #define CP0_ERROREPC $30
  76 #define CP0_DESAVE $31
  77
  78 /*
  79  * R4640/R4650 cp0 register names.  These registers are listed
  80  * here only for completeness; without MMU these CPUs are not useable
  81  * by Linux.  A future ELKS port might take make Linux run on them
  82  * though ...
  83  */
  84 #define CP0_IBASE $0
  85 #define CP0_IBOUND $1
  86 #define CP0_DBASE $2
  87 #define CP0_DBOUND $3
  88 #define CP0_CALG $17
  89 #define CP0_IWATCH $18
  90 #define CP0_DWATCH $19
  91
  92 /*
  93  * Coprocessor 0 Set 1 register names
  94  */
  95 #define CP0_S1_DERRADDR0  $26
  96 #define CP0_S1_DERRADDR1  $27
  97 #define CP0_S1_INTCONTROL $20
  98
  99 /*
 100  * Coprocessor 0 Set 2 register names
 101  */
 102 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 103
 104 /*
 105  * Coprocessor 0 Set 3 register names
 106  */
 107 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 108
 109 /*
 110  *  TX39 Series
 111  */
 112 #define CP0_TX39_CACHE  $7
 113
 114 /*
 115  * Coprocessor 1 (FPU) register names
 116  */
 117 #define CP1_REVISION   $0
 118 #define CP1_STATUS     $31
 119
 120 /*
 121  * FPU Status Register Values
 122  */
 123 #define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
 124 #define FPU_CSR_COND    0x00800000      /* $fcc0 */
 125 #define FPU_CSR_COND0   0x00800000      /* $fcc0 */
 126 #define FPU_CSR_COND1   0x02000000      /* $fcc1 */
 127 #define FPU_CSR_COND2   0x04000000      /* $fcc2 */
 128 #define FPU_CSR_COND3   0x08000000      /* $fcc3 */
 129 #define FPU_CSR_COND4   0x10000000      /* $fcc4 */
 130 #define FPU_CSR_COND5   0x20000000      /* $fcc5 */
 131 #define FPU_CSR_COND6   0x40000000      /* $fcc6 */
 132 #define FPU_CSR_COND7   0x80000000      /* $fcc7 */
 133
 134 /*
 135  * Bits 18 - 20 of the FPU Status Register will be read as 0,
 136  * and should be written as zero.
 137  */
 138 #define FPU_CSR_RSVD    0x001c0000
 139
 140 /*
 141  * X the exception cause indicator
 142  * E the exception enable
 143  * S the sticky/flag bit
 144 */
 145 #define FPU_CSR_ALL_X   0x0003f000
 146 #define FPU_CSR_UNI_X   0x00020000
 147 #define FPU_CSR_INV_X   0x00010000
 148 #define FPU_CSR_DIV_X   0x00008000
 149 #define FPU_CSR_OVF_X   0x00004000
 150 #define FPU_CSR_UDF_X   0x00002000
 151 #define FPU_CSR_INE_X   0x00001000
 152
 153 #define FPU_CSR_ALL_E   0x00000f80
 154 #define FPU_CSR_INV_E   0x00000800
 155 #define FPU_CSR_DIV_E   0x00000400
 156 #define FPU_CSR_OVF_E   0x00000200
 157 #define FPU_CSR_UDF_E   0x00000100
 158 #define FPU_CSR_INE_E   0x00000080
 159
 160 #define FPU_CSR_ALL_S   0x0000007c
 161 #define FPU_CSR_INV_S   0x00000040
 162 #define FPU_CSR_DIV_S   0x00000020
 163 #define FPU_CSR_OVF_S   0x00000010
 164 #define FPU_CSR_UDF_S   0x00000008
 165 #define FPU_CSR_INE_S   0x00000004
 166
 167 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
 168 #define FPU_CSR_RM      0x00000003
 169 #define FPU_CSR_RN      0x0     /* nearest */
 170 #define FPU_CSR_RZ      0x1     /* towards zero */
 171 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 172 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 173
 174
 175 /*
 176  * Values for PageMask register
 177  */
 178 #ifdef CONFIG_CPU_VR41XX
 179
 180 /* Why doesn't stupidity hurt ... */
 181
 182 #define PM_1K           0x00000000
 183 #define PM_4K           0x00001800
 184 #define PM_16K          0x00007800
 185 #define PM_64K          0x0001f800
 186 #define PM_256K         0x0007f800
 187
 188 #else
 189
 190 #define PM_4K           0x00000000
 191 #define PM_8K           0x00002000
 192 #define PM_16K          0x00006000
 193 #define PM_32K          0x0000e000
 194 #define PM_64K          0x0001e000
 195 #define PM_128K         0x0003e000
 196 #define PM_256K         0x0007e000
 197 #define PM_512K         0x000fe000
 198 #define PM_1M           0x001fe000
 199 #define PM_2M           0x003fe000
 200 #define PM_4M           0x007fe000
 201 #define PM_8M           0x00ffe000
 202 #define PM_16M          0x01ffe000
 203 #define PM_32M          0x03ffe000
 204 #define PM_64M          0x07ffe000
 205 #define PM_256M         0x1fffe000
 206 #define PM_1G           0x7fffe000
 207
 208 #endif
 209
 210 /*
 211  * Default page size for a given kernel configuration
 212  */
 213 #ifdef CONFIG_PAGE_SIZE_4KB
 214 #define PM_DEFAULT_MASK PM_4K
 215 #elif defined(CONFIG_PAGE_SIZE_8KB)
 216 #define PM_DEFAULT_MASK PM_8K
 217 #elif defined(CONFIG_PAGE_SIZE_16KB)
 218 #define PM_DEFAULT_MASK PM_16K
 219 #elif defined(CONFIG_PAGE_SIZE_32KB)
 220 #define PM_DEFAULT_MASK PM_32K
 221 #elif defined(CONFIG_PAGE_SIZE_64KB)
 222 #define PM_DEFAULT_MASK PM_64K
 223 #else
 224 #error Bad page size configuration!
 225 #endif
 226
 227 /*
 228  * Default huge tlb size for a given kernel configuration
 229  */
 230 #ifdef CONFIG_PAGE_SIZE_4KB
 231 #define PM_HUGE_MASK    PM_1M
 232 #elif defined(CONFIG_PAGE_SIZE_8KB)
 233 #define PM_HUGE_MASK    PM_4M
 234 #elif defined(CONFIG_PAGE_SIZE_16KB)
 235 #define PM_HUGE_MASK    PM_16M
 236 #elif defined(CONFIG_PAGE_SIZE_32KB)
 237 #define PM_HUGE_MASK    PM_64M
 238 #elif defined(CONFIG_PAGE_SIZE_64KB)
 239 #define PM_HUGE_MASK    PM_256M
 240 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 241 #error Bad page size configuration for hugetlbfs!
 242 #endif
 243
 244 /*
 245  * Values used for computation of new tlb entries
 246  */
 247 #define PL_4K           12
 248 #define PL_16K          14
 249 #define PL_64K          16
 250 #define PL_256K         18
 251 #define PL_1M           20
 252 #define PL_4M           22
 253 #define PL_16M          24
 254 #define PL_64M          26
 255 #define PL_256M         28
 256
 257 /*
 258  * PageGrain bits
 259  */
 260 #define PG_RIE          (_ULCAST_(1) <<  31)
 261 #define PG_XIE          (_ULCAST_(1) <<  30)
 262 #define PG_ELPA         (_ULCAST_(1) <<  29)
 263 #define PG_ESP          (_ULCAST_(1) <<  28)
 264 #define PG_IEC          (_ULCAST_(1) <<  27)
 265
 266 /*
 267  * R4x00 interrupt enable / cause bits
 268  */
 269 #define IE_SW0          (_ULCAST_(1) <<  8)
 270 #define IE_SW1          (_ULCAST_(1) <<  9)
 271 #define IE_IRQ0         (_ULCAST_(1) << 10)
 272 #define IE_IRQ1         (_ULCAST_(1) << 11)
 273 #define IE_IRQ2         (_ULCAST_(1) << 12)
 274 #define IE_IRQ3         (_ULCAST_(1) << 13)
 275 #define IE_IRQ4         (_ULCAST_(1) << 14)
 276 #define IE_IRQ5         (_ULCAST_(1) << 15)
 277
 278 /*
 279  * R4x00 interrupt cause bits
 280  */
 281 #define C_SW0           (_ULCAST_(1) <<  8)
 282 #define C_SW1           (_ULCAST_(1) <<  9)
 283 #define C_IRQ0          (_ULCAST_(1) << 10)
 284 #define C_IRQ1          (_ULCAST_(1) << 11)
 285 #define C_IRQ2          (_ULCAST_(1) << 12)
 286 #define C_IRQ3          (_ULCAST_(1) << 13)
 287 #define C_IRQ4          (_ULCAST_(1) << 14)
 288 #define C_IRQ5          (_ULCAST_(1) << 15)
 289
 290 /*
 291  * Bitfields in the R4xx0 cp0 status register
 292  */
 293 #define ST0_IE                  0x00000001
 294 #define ST0_EXL                 0x00000002
 295 #define ST0_ERL                 0x00000004
 296 #define ST0_KSU                 0x00000018
 297 #  define KSU_USER              0x00000010
 298 #  define KSU_SUPERVISOR        0x00000008
 299 #  define KSU_KERNEL            0x00000000
 300 #define ST0_UX                  0x00000020
 301 #define ST0_SX                  0x00000040
 302 #define ST0_KX                  0x00000080
 303 #define ST0_DE                  0x00010000
 304 #define ST0_CE                  0x00020000
 305
 306 /*
 307  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 308  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 309  * processors.
 310  */
 311 #define ST0_CO                  0x08000000
 312
 313 /*
 314  * Bitfields in the R[23]000 cp0 status register.
 315  */
 316 #define ST0_IEC                 0x00000001
 317 #define ST0_KUC                 0x00000002
 318 #define ST0_IEP                 0x00000004
 319 #define ST0_KUP                 0x00000008
 320 #define ST0_IEO                 0x00000010
 321 #define ST0_KUO                 0x00000020
 322 /* bits 6 & 7 are reserved on R[23]000 */
 323 #define ST0_ISC                 0x00010000
 324 #define ST0_SWC                 0x00020000
 325 #define ST0_CM                  0x00080000
 326
 327 /*
 328  * Bits specific to the R4640/R4650
 329  */
 330 #define ST0_UM                  (_ULCAST_(1) <<  4)
 331 #define ST0_IL                  (_ULCAST_(1) << 23)
 332 #define ST0_DL                  (_ULCAST_(1) << 24)
 333
 334 /*
 335  * Enable the MIPS MDMX and DSP ASEs
 336  */
 337 #define ST0_MX                  0x01000000
 338
 339 /*
 340  * Bitfields in the TX39 family CP0 Configuration Register 3
 341  */
 342 #define TX39_CONF_ICS_SHIFT     19
 343 #define TX39_CONF_ICS_MASK      0x00380000
 344 #define TX39_CONF_ICS_1KB       0x00000000
 345 #define TX39_CONF_ICS_2KB       0x00080000
 346 #define TX39_CONF_ICS_4KB       0x00100000
 347 #define TX39_CONF_ICS_8KB       0x00180000
 348 #define TX39_CONF_ICS_16KB      0x00200000
 349
 350 #define TX39_CONF_DCS_SHIFT     16
 351 #define TX39_CONF_DCS_MASK      0x00070000
 352 #define TX39_CONF_DCS_1KB       0x00000000
 353 #define TX39_CONF_DCS_2KB       0x00010000
 354 #define TX39_CONF_DCS_4KB       0x00020000
 355 #define TX39_CONF_DCS_8KB       0x00030000
 356 #define TX39_CONF_DCS_16KB      0x00040000
 357
 358 #define TX39_CONF_CWFON         0x00004000
 359 #define TX39_CONF_WBON          0x00002000
 360 #define TX39_CONF_RF_SHIFT      10
 361 #define TX39_CONF_RF_MASK       0x00000c00
 362 #define TX39_CONF_DOZE          0x00000200
 363 #define TX39_CONF_HALT          0x00000100
 364 #define TX39_CONF_LOCK          0x00000080
 365 #define TX39_CONF_ICE           0x00000020
 366 #define TX39_CONF_DCE           0x00000010
 367 #define TX39_CONF_IRSIZE_SHIFT  2
 368 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 369 #define TX39_CONF_DRSIZE_SHIFT  0
 370 #define TX39_CONF_DRSIZE_MASK   0x00000003
 371
 372 /*
 373  * Status register bits available in all MIPS CPUs.
 374  */
 375 #define ST0_IM                  0x0000ff00
 376 #define  STATUSB_IP0            8
 377 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 378 #define  STATUSB_IP1            9
 379 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 380 #define  STATUSB_IP2            10
 381 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 382 #define  STATUSB_IP3            11
 383 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 384 #define  STATUSB_IP4            12
 385 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 386 #define  STATUSB_IP5            13
 387 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 388 #define  STATUSB_IP6            14
 389 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 390 #define  STATUSB_IP7            15
 391 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 392 #define  STATUSB_IP8            0
 393 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 394 #define  STATUSB_IP9            1
 395 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 396 #define  STATUSB_IP10           2
 397 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 398 #define  STATUSB_IP11           3
 399 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 400 #define  STATUSB_IP12           4
 401 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 402 #define  STATUSB_IP13           5
 403 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 404 #define  STATUSB_IP14           6
 405 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 406 #define  STATUSB_IP15           7
 407 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 408 #define ST0_CH                  0x00040000
 409 #define ST0_NMI                 0x00080000
 410 #define ST0_SR                  0x00100000
 411 #define ST0_TS                  0x00200000
 412 #define ST0_BEV                 0x00400000
 413 #define ST0_RE                  0x02000000
 414 #define ST0_FR                  0x04000000
 415 #define ST0_CU                  0xf0000000
 416 #define ST0_CU0                 0x10000000
 417 #define ST0_CU1                 0x20000000
 418 #define ST0_CU2                 0x40000000
 419 #define ST0_CU3                 0x80000000
 420 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 421
 422 /*
 423  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 424  */
 425 #define INTCTLB_IPFDC           23
 426 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 427 #define INTCTLB_IPPCI           26
 428 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 429 #define INTCTLB_IPTI            29
 430 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 431
 432 /*
 433  * Bitfields and bit numbers in the coprocessor 0 cause register.
 434  *
 435  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 436  */
 437 #define  CAUSEB_EXCCODE         2
 438 #define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
 439 #define  CAUSEB_IP              8
 440 #define  CAUSEF_IP              (_ULCAST_(255) <<  8)
 441 #define  CAUSEB_IP0             8
 442 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 443 #define  CAUSEB_IP1             9
 444 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 445 #define  CAUSEB_IP2             10
 446 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 447 #define  CAUSEB_IP3             11
 448 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 449 #define  CAUSEB_IP4             12
 450 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 451 #define  CAUSEB_IP5             13
 452 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 453 #define  CAUSEB_IP6             14
 454 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 455 #define  CAUSEB_IP7             15
 456 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 457 #define  CAUSEB_FDCI            21
 458 #define  CAUSEF_FDCI            (_ULCAST_(1)   << 21)
 459 #define  CAUSEB_IV              23
 460 #define  CAUSEF_IV              (_ULCAST_(1)   << 23)
 461 #define  CAUSEB_PCI             26
 462 #define  CAUSEF_PCI             (_ULCAST_(1)   << 26)
 463 #define  CAUSEB_CE              28
 464 #define  CAUSEF_CE              (_ULCAST_(3)   << 28)
 465 #define  CAUSEB_TI              30
 466 #define  CAUSEF_TI              (_ULCAST_(1)   << 30)
 467 #define  CAUSEB_BD              31
 468 #define  CAUSEF_BD              (_ULCAST_(1)   << 31)
 469
 470 /*
 471  * Bits in the coprocessor 0 config register.
 472  */
 473 /* Generic bits.  */
 474 #define CONF_CM_CACHABLE_NO_WA          0
 475 #define CONF_CM_CACHABLE_WA             1
 476 #define CONF_CM_UNCACHED                2
 477 #define CONF_CM_CACHABLE_NONCOHERENT    3
 478 #define CONF_CM_CACHABLE_CE             4
 479 #define CONF_CM_CACHABLE_COW            5
 480 #define CONF_CM_CACHABLE_CUW            6
 481 #define CONF_CM_CACHABLE_ACCELERATED    7
 482 #define CONF_CM_CMASK                   7
 483 #define CONF_BE                 (_ULCAST_(1) << 15)
 484
 485 /* Bits common to various processors.  */
 486 #define CONF_CU                 (_ULCAST_(1) <<  3)
 487 #define CONF_DB                 (_ULCAST_(1) <<  4)
 488 #define CONF_IB                 (_ULCAST_(1) <<  5)
 489 #define CONF_DC                 (_ULCAST_(7) <<  6)
 490 #define CONF_IC                 (_ULCAST_(7) <<  9)
 491 #define CONF_EB                 (_ULCAST_(1) << 13)
 492 #define CONF_EM                 (_ULCAST_(1) << 14)
 493 #define CONF_SM                 (_ULCAST_(1) << 16)
 494 #define CONF_SC                 (_ULCAST_(1) << 17)
 495 #define CONF_EW                 (_ULCAST_(3) << 18)
 496 #define CONF_EP                 (_ULCAST_(15)<< 24)
 497 #define CONF_EC                 (_ULCAST_(7) << 28)
 498 #define CONF_CM                 (_ULCAST_(1) << 31)
 499
 500 /* Bits specific to the R4xx0.  */
 501 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 502 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 503 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 504
 505 /* Bits specific to the R5000.  */
 506 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 507 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 508
 509 /* Bits specific to the RM7000.  */
 510 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 511 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 512 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 513 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 514 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 515 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 516
 517 /* Bits specific to the R10000.  */
 518 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 519 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 520 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 521 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 522 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 523 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 524 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 525 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 526 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 527 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 528 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 529
 530 /* Bits specific to the VR41xx.  */
 531 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 532 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 533 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 534 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 535 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 536
 537 /* Bits specific to the R30xx.  */
 538 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 539 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 540 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 541 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 542 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 543 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 544 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 545 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 546 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 547
 548 /* Bits specific to the TX49.  */
 549 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 550 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 551 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 552 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 553
 554 /* Bits specific to the MIPS32/64 PRA.  */
 555 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 556 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 557 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 558 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 559
 560 /*
 561  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 562  */
 563 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 564 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 565 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 566 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 567 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 568 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 569 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 570 #define MIPS_CONF1_DA_SHF       7
 571 #define MIPS_CONF1_DA_SZ        3
 572 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 573 #define MIPS_CONF1_DL_SHF       10
 574 #define MIPS_CONF1_DL_SZ        3
 575 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 576 #define MIPS_CONF1_DS_SHF       13
 577 #define MIPS_CONF1_DS_SZ        3
 578 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 579 #define MIPS_CONF1_IA_SHF       16
 580 #define MIPS_CONF1_IA_SZ        3
 581 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 582 #define MIPS_CONF1_IL_SHF       19
 583 #define MIPS_CONF1_IL_SZ        3
 584 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 585 #define MIPS_CONF1_IS_SHF       22
 586 #define MIPS_CONF1_IS_SZ        3
 587 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 588 #define MIPS_CONF1_TLBS_SHIFT   (25)
 589 #define MIPS_CONF1_TLBS_SIZE    (6)
 590 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 591
 592 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 593 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 594 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 595 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 596 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 597 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 598 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 599 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 600
 601 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 602 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 603 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 604 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 605 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 606 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 607 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 608 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 609 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 610 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 611 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 612 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 613 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 614 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 615 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 616 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 617 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 618 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 619 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 620 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 621 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 622 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 623 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 624 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 625 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 626 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 627 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 628
 629 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 630 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 631 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 632 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 633 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 634 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 635 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 636 /* bits 10:8 in FTLB-only configurations */
 637 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 638 /* bits 12:8 in VTLB-FTLB only configurations */
 639 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 640 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 641 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 642 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 643 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 644 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << 16)
 645 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 646 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 647 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 648 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 649 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 650
 651 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 652 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 653 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 654 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 655 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 656 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 657 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 658 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 659 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 660 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 661 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 662
 663 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 664 /* proAptiv FTLB on/off bit */
 665 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 666 /* FTLB probability bits */
 667 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 668
 669 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 670
 671 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 672
 673 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 674 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 675
 676 /* MAAR bit definitions */
 677 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 678 #define MIPS_MAAR_ADDR_SHIFT    12
 679 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 680 #define MIPS_MAAR_V             (_ULCAST_(1) << 0)
 681
 682 /*  EntryHI bit definition */
 683 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 684
 685 /* CMGCRBase bit definitions */
 686 #define MIPS_CMGCRB_BASE        11
 687 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 688
 689 /*
 690  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 691  */
 692 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 693 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 694 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 695 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 696 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 697 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 698 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 699 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
 700
 701 /*
 702  * Bits in the MIPS32 Memory Segmentation registers.
 703  */
 704 #define MIPS_SEGCFG_PA_SHIFT    9
 705 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 706 #define MIPS_SEGCFG_AM_SHIFT    4
 707 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 708 #define MIPS_SEGCFG_EU_SHIFT    3
 709 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 710 #define MIPS_SEGCFG_C_SHIFT     0
 711 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 712
 713 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 714 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 715 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 716 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 717 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 718 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 719 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 720
 721 #define MIPS_PWFIELD_GDI_SHIFT  24
 722 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 723 #define MIPS_PWFIELD_UDI_SHIFT  18
 724 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 725 #define MIPS_PWFIELD_MDI_SHIFT  12
 726 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 727 #define MIPS_PWFIELD_PTI_SHIFT  6
 728 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 729 #define MIPS_PWFIELD_PTEI_SHIFT 0
 730 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 731
 732 #define MIPS_PWSIZE_GDW_SHIFT   24
 733 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 734 #define MIPS_PWSIZE_UDW_SHIFT   18
 735 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 736 #define MIPS_PWSIZE_MDW_SHIFT   12
 737 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 738 #define MIPS_PWSIZE_PTW_SHIFT   6
 739 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 740 #define MIPS_PWSIZE_PTEW_SHIFT  0
 741 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 742
 743 #define MIPS_PWCTL_PWEN_SHIFT   31
 744 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 745 #define MIPS_PWCTL_DPH_SHIFT    7
 746 #define MIPS_PWCTL_DPH_MASK     0x00000080
 747 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 748 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 749 #define MIPS_PWCTL_PSN_SHIFT    0
 750 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 751
 752 /* CDMMBase register bit definitions */
 753 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 754 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 755 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 756 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 757 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 758 #define MIPS_CDMMBASE_ADDR_START 15
 759
 760 #ifndef __ASSEMBLY__
 761
 762 /*
 763  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
 764  */
 765 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
 766     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
 767 #define get_isa16_mode(x)               ((x) & 0x1)
 768 #define msk_isa16_mode(x)               ((x) & ~0x1)
 769 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
 770 #else
 771 #define get_isa16_mode(x)               0
 772 #define msk_isa16_mode(x)               (x)
 773 #define set_isa16_mode(x)               do { } while(0)
 774 #endif
 775
 776 /*
 777  * microMIPS instructions can be 16-bit or 32-bit in length. This
 778  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
 779  */
 780 static inline int mm_insn_16bit(u16 insn)
 781 {
 782         u16 opcode = (insn >> 10) & 0x7;
 783
 784         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
 785 }
 786
 787 /*
 788  * TLB Invalidate Flush
 789  */
 790 static inline void tlbinvf(void)
 791 {
 792         __asm__ __volatile__(
 793                 ".set push\n\t"
 794                 ".set noreorder\n\t"
 795                 ".word 0x42000004\n\t" /* tlbinvf */
 796                 ".set pop");
 797 }
 798
 799
 800 /*
 801  * Functions to access the R10000 performance counters.  These are basically
 802  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
 803  * performance counter number encoded into bits 1 ... 5 of the instruction.
 804  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
 805  * disassembler these will look like an access to sel 0 or 1.
 806  */
 807 #define read_r10k_perf_cntr(counter)                            \
 808 ({                                                              \
 809         unsigned int __res;                                     \
 810         __asm__ __volatile__(                                   \
 811         "mfpc\t%0, %1"                                          \
 812         : "=r" (__res)                                          \
 813         : "i" (counter));                                       \
 814                                                                 \
 815         __res;                                                  \
 816 })
 817
 818 #define write_r10k_perf_cntr(counter,val)                       \
 819 do {                                                            \
 820         __asm__ __volatile__(                                   \
 821         "mtpc\t%0, %1"                                          \
 822         :                                                       \
 823         : "r" (val), "i" (counter));                            \
 824 } while (0)
 825
 826 #define read_r10k_perf_event(counter)                           \
 827 ({                                                              \
 828         unsigned int __res;                                     \
 829         __asm__ __volatile__(                                   \
 830         "mfps\t%0, %1"                                          \
 831         : "=r" (__res)                                          \
 832         : "i" (counter));                                       \
 833                                                                 \
 834         __res;                                                  \
 835 })
 836
 837 #define write_r10k_perf_cntl(counter,val)                       \
 838 do {                                                            \
 839         __asm__ __volatile__(                                   \
 840         "mtps\t%0, %1"                                          \
 841         :                                                       \
 842         : "r" (val), "i" (counter));                            \
 843 } while (0)
 844
 845
 846 /*
 847  * Macros to access the system control coprocessor
 848  */
 849
 850 #define __read_32bit_c0_register(source, sel)                           \
 851 ({ int __res;                                                           \
 852         if (sel == 0)                                                   \
 853                 __asm__ __volatile__(                                   \
 854                         "mfc0\t%0, " #source "\n\t"                     \
 855                         : "=r" (__res));                                \
 856         else                                                            \
 857                 __asm__ __volatile__(                                   \
 858                         ".set\tmips32\n\t"                              \
 859                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
 860                         ".set\tmips0\n\t"                               \
 861                         : "=r" (__res));                                \
 862         __res;                                                          \
 863 })
 864
 865 #define __read_64bit_c0_register(source, sel)                           \
 866 ({ unsigned long long __res;                                            \
 867         if (sizeof(unsigned long) == 4)                                 \
 868                 __res = __read_64bit_c0_split(source, sel);             \
 869         else if (sel == 0)                                              \
 870                 __asm__ __volatile__(                                   \
 871                         ".set\tmips3\n\t"                               \
 872                         "dmfc0\t%0, " #source "\n\t"                    \
 873                         ".set\tmips0"                                   \
 874                         : "=r" (__res));                                \
 875         else                                                            \
 876                 __asm__ __volatile__(                                   \
 877                         ".set\tmips64\n\t"                              \
 878                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
 879                         ".set\tmips0"                                   \
 880                         : "=r" (__res));                                \
 881         __res;                                                          \
 882 })
 883
 884 #define __write_32bit_c0_register(register, sel, value)                 \
 885 do {                                                                    \
 886         if (sel == 0)                                                   \
 887                 __asm__ __volatile__(                                   \
 888                         "mtc0\t%z0, " #register "\n\t"                  \
 889                         : : "Jr" ((unsigned int)(value)));              \
 890         else                                                            \
 891                 __asm__ __volatile__(                                   \
 892                         ".set\tmips32\n\t"                              \
 893                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
 894                         ".set\tmips0"                                   \
 895                         : : "Jr" ((unsigned int)(value)));              \
 896 } while (0)
 897
 898 #define __write_64bit_c0_register(register, sel, value)                 \
 899 do {                                                                    \
 900         if (sizeof(unsigned long) == 4)                                 \
 901                 __write_64bit_c0_split(register, sel, value);           \
 902         else if (sel == 0)                                              \
 903                 __asm__ __volatile__(                                   \
 904                         ".set\tmips3\n\t"                               \
 905                         "dmtc0\t%z0, " #register "\n\t"                 \
 906                         ".set\tmips0"                                   \
 907                         : : "Jr" (value));                              \
 908         else                                                            \
 909                 __asm__ __volatile__(                                   \
 910                         ".set\tmips64\n\t"                              \
 911                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
 912                         ".set\tmips0"                                   \
 913                         : : "Jr" (value));                              \
 914 } while (0)
 915
 916 #define __read_ulong_c0_register(reg, sel)                              \
 917         ((sizeof(unsigned long) == 4) ?                                 \
 918         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
 919         (unsigned long) __read_64bit_c0_register(reg, sel))
 920
 921 #define __write_ulong_c0_register(reg, sel, val)                        \
 922 do {                                                                    \
 923         if (sizeof(unsigned long) == 4)                                 \
 924                 __write_32bit_c0_register(reg, sel, val);               \
 925         else                                                            \
 926                 __write_64bit_c0_register(reg, sel, val);               \
 927 } while (0)
 928
 929 /*
 930  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
 931  */
 932 #define __read_32bit_c0_ctrl_register(source)                           \
 933 ({ int __res;                                                           \
 934         __asm__ __volatile__(                                           \
 935                 "cfc0\t%0, " #source "\n\t"                             \
 936                 : "=r" (__res));                                        \
 937         __res;                                                          \
 938 })
 939
 940 #define __write_32bit_c0_ctrl_register(register, value)                 \
 941 do {                                                                    \
 942         __asm__ __volatile__(                                           \
 943                 "ctc0\t%z0, " #register "\n\t"                          \
 944                 : : "Jr" ((unsigned int)(value)));                      \
 945 } while (0)
 946
 947 /*
 948  * These versions are only needed for systems with more than 38 bits of
 949  * physical address space running the 32-bit kernel.  That's none atm :-)
 950  */
 951 #define __read_64bit_c0_split(source, sel)                              \
 952 ({                                                                      \
 953         unsigned long long __val;                                       \
 954         unsigned long __flags;                                          \
 955                                                                         \
 956         local_irq_save(__flags);                                        \
 957         if (sel == 0)                                                   \
 958                 __asm__ __volatile__(                                   \
 959                         ".set\tmips64\n\t"                              \
 960                         "dmfc0\t%M0, " #source "\n\t"                   \
 961                         "dsll\t%L0, %M0, 32\n\t"                        \
 962                         "dsra\t%M0, %M0, 32\n\t"                        \
 963                         "dsra\t%L0, %L0, 32\n\t"                        \
 964                         ".set\tmips0"                                   \
 965                         : "=r" (__val));                                \
 966         else                                                            \
 967                 __asm__ __volatile__(                                   \
 968                         ".set\tmips64\n\t"                              \
 969                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
 970                         "dsll\t%L0, %M0, 32\n\t"                        \
 971                         "dsra\t%M0, %M0, 32\n\t"                        \
 972                         "dsra\t%L0, %L0, 32\n\t"                        \
 973                         ".set\tmips0"                                   \
 974                         : "=r" (__val));                                \
 975         local_irq_restore(__flags);                                     \
 976                                                                         \
 977         __val;                                                          \
 978 })
 979
 980 #define __write_64bit_c0_split(source, sel, val)                        \
 981 do {                                                                    \
 982         unsigned long __flags;                                          \
 983                                                                         \
 984         local_irq_save(__flags);                                        \
 985         if (sel == 0)                                                   \
 986                 __asm__ __volatile__(                                   \
 987                         ".set\tmips64\n\t"                              \
 988                         "dsll\t%L0, %L0, 32\n\t"                        \
 989                         "dsrl\t%L0, %L0, 32\n\t"                        \
 990                         "dsll\t%M0, %M0, 32\n\t"                        \
 991                         "or\t%L0, %L0, %M0\n\t"                         \
 992                         "dmtc0\t%L0, " #source "\n\t"                   \
 993                         ".set\tmips0"                                   \
 994                         : : "r" (val));                                 \
 995         else                                                            \
 996                 __asm__ __volatile__(                                   \
 997                         ".set\tmips64\n\t"                              \
 998                         "dsll\t%L0, %L0, 32\n\t"                        \
 999                         "dsrl\t%L0, %L0, 32\n\t"                        \
1000                         "dsll\t%M0, %M0, 32\n\t"                        \
1001                         "or\t%L0, %L0, %M0\n\t"                         \
1002                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1003                         ".set\tmips0"                                   \
1004                         : : "r" (val));                                 \
1005         local_irq_restore(__flags);                                     \
1006 } while (0)
1007
1008 #define __readx_32bit_c0_register(source)                               \
1009 ({                                                                      \
1010         unsigned int __res;                                             \
1011                                                                         \
1012         __asm__ __volatile__(                                           \
1013         "       .set    push                                    \n"     \
1014         "       .set    noat                                    \n"     \
1015         "       .set    mips32r2                                \n"     \
1016         "       .insn                                           \n"     \
1017         "       # mfhc0 $1, %1                                  \n"     \
1018         "       .word   (0x40410000 | ((%1 & 0x1f) << 11))      \n"     \
1019         "       move    %0, $1                                  \n"     \
1020         "       .set    pop                                     \n"     \
1021         : "=r" (__res)                                                  \
1022         : "i" (source));                                                \
1023         __res;                                                          \
1024 })
1025
1026 #define __writex_32bit_c0_register(register, value)                     \
1027 do {                                                                    \
1028         __asm__ __volatile__(                                           \
1029         "       .set    push                                    \n"     \
1030         "       .set    noat                                    \n"     \
1031         "       .set    mips32r2                                \n"     \
1032         "       move    $1, %0                                  \n"     \
1033         "       # mthc0 $1, %1                                  \n"     \
1034         "       .insn                                           \n"     \
1035         "       .word   (0x40c10000 | ((%1 & 0x1f) << 11))      \n"     \
1036         "       .set    pop                                     \n"     \
1037         :                                                               \
1038         : "r" (value), "i" (register));                                 \
1039 } while (0)
1040
1041 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1042 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1043
1044 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1045 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1046
1047 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1048 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1049
1050 #define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
1051 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1052
1053 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1054 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1055
1056 #define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
1057 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1058
1059 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1060 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1061
1062 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1063 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1064
1065 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1066 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1067
1068 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1069 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1070
1071 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1072 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1073
1074 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1075 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1076
1077 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1078
1079 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1080 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1081
1082 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1083 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1084
1085 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1086 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1087
1088 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1089 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1090
1091 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1092 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1093
1094 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1095 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1096
1097 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1098 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1099
1100 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1101 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1102
1103 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1104 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1105
1106 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1107
1108 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1109
1110 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1111 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1112
1113 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1114 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1115
1116 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1117
1118 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1119
1120 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1121 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1122 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1123 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1124 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1125 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1126 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1127 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1128 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1129 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1130 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1131 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1132 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1133 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1134 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1135 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1136
1137 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1138 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1139 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1140 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1141 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1142 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1143
1144 /*
1145  * The WatchLo register.  There may be up to 8 of them.
1146  */
1147 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1148 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1149 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1150 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1151 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1152 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1153 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1154 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1155 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1156 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1157 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1158 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1159 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1160 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1161 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1162 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1163
1164 /*
1165  * The WatchHi register.  There may be up to 8 of them.
1166  */
1167 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1168 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1169 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1170 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1171 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1172 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1173 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1174 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1175
1176 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1177 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1178 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1179 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1180 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1181 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1182 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1183 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1184
1185 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1186 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1187
1188 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1189 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1190
1191 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1192 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1193
1194 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1195 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1196
1197 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1198 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1199
1200 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1201 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1202
1203 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1204 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1205
1206 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1207 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1208
1209 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1210 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1211
1212 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1213 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1214
1215 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1216 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1217
1218 /*
1219  * MIPS32 / MIPS64 performance counters
1220  */
1221 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1222 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1223 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1224 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1225 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1226 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1227 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1228 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1229 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1230 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1231 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1232 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1233 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1234 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1235 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1236 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1237 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1238 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1239 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1240 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1241 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1242 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1243 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1244 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1245
1246 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1247 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1248
1249 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1250 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1251
1252 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1253
1254 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1255 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1256
1257 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1258 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1259
1260 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1261 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1262
1263 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1264 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1265
1266 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1267 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1268
1269 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1270 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1271
1272 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1273 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1274
1275 /* MIPSR2 */
1276 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1277 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1278
1279 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1280 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1281
1282 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1283 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1284
1285 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1286 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1287
1288 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1289 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1290
1291 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1292 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1293
1294 /* MIPSR3 */
1295 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1296 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1297
1298 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1299 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1300
1301 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1302 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1303
1304 /* Hardware Page Table Walker */
1305 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1306 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1307
1308 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1309 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1310
1311 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1312 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1313
1314 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1315 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1316
1317 /* Cavium OCTEON (cnMIPS) */
1318 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1319 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1320
1321 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1322 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1323
1324 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1325 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1326 /*
1327  * The cacheerr registers are not standardized.  On OCTEON, they are
1328  * 64 bits wide.
1329  */
1330 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1331 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1332
1333 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1334 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1335
1336 /* BMIPS3300 */
1337 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1338 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1339
1340 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1341 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1342
1343 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1344 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1345
1346 /* BMIPS43xx */
1347 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1348 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1349
1350 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1351 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1352
1353 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1354 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1355
1356 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1357 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1358
1359 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1360 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1361
1362 /* BMIPS5000 */
1363 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1364 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1365
1366 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1367 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1368
1369 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1370 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1371
1372 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1373 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1374
1375 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1376 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1377
1378 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1379 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1380
1381 /*
1382  * Macros to access the floating point coprocessor control registers
1383  */
1384 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
1385 ({                                                                      \
1386         int __res;                                                      \
1387                                                                         \
1388         __asm__ __volatile__(                                           \
1389         "       .set    push                                    \n"     \
1390         "       .set    reorder                                 \n"     \
1391         "       # gas fails to assemble cfc1 for some archs,    \n"     \
1392         "       # like Octeon.                                  \n"     \
1393         "       .set    mips1                                   \n"     \
1394         "       "STR(gas_hardfloat)"                            \n"     \
1395         "       cfc1    %0,"STR(source)"                        \n"     \
1396         "       .set    pop                                     \n"     \
1397         : "=r" (__res));                                                \
1398         __res;                                                          \
1399 })
1400
1401 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
1402 do {                                                                    \
1403         __asm__ __volatile__(                                           \
1404         "       .set    push                                    \n"     \
1405         "       .set    reorder                                 \n"     \
1406         "       "STR(gas_hardfloat)"                            \n"     \
1407         "       ctc1    %0,"STR(dest)"                          \n"     \
1408         "       .set    pop                                     \n"     \
1409         : : "r" (val));                                                 \
1410 } while (0)
1411
1412 #ifdef GAS_HAS_SET_HARDFLOAT
1413 #define read_32bit_cp1_register(source)                                 \
1414         _read_32bit_cp1_register(source, .set hardfloat)
1415 #define write_32bit_cp1_register(dest, val)                             \
1416         _write_32bit_cp1_register(dest, val, .set hardfloat)
1417 #else
1418 #define read_32bit_cp1_register(source)                                 \
1419         _read_32bit_cp1_register(source, )
1420 #define write_32bit_cp1_register(dest, val)                             \
1421         _write_32bit_cp1_register(dest, val, )
1422 #endif
1423
1424 #ifdef HAVE_AS_DSP
1425 #define rddsp(mask)                                                     \
1426 ({                                                                      \
1427         unsigned int __dspctl;                                          \
1428                                                                         \
1429         __asm__ __volatile__(                                           \
1430         "       .set push                                       \n"     \
1431         "       .set dsp                                        \n"     \
1432         "       rddsp   %0, %x1                                 \n"     \
1433         "       .set pop                                        \n"     \
1434         : "=r" (__dspctl)                                               \
1435         : "i" (mask));                                                  \
1436         __dspctl;                                                       \
1437 })
1438
1439 #define wrdsp(val, mask)                                                \
1440 do {                                                                    \
1441         __asm__ __volatile__(                                           \
1442         "       .set push                                       \n"     \
1443         "       .set dsp                                        \n"     \
1444         "       wrdsp   %0, %x1                                 \n"     \
1445         "       .set pop                                        \n"     \
1446         :                                                               \
1447         : "r" (val), "i" (mask));                                       \
1448 } while (0)
1449
1450 #define mflo0()                                                         \
1451 ({                                                                      \
1452         long mflo0;                                                     \
1453         __asm__(                                                        \
1454         "       .set push                                       \n"     \
1455         "       .set dsp                                        \n"     \
1456         "       mflo %0, $ac0                                   \n"     \
1457         "       .set pop                                        \n"     \
1458         : "=r" (mflo0));                                                \
1459         mflo0;                                                          \
1460 })
1461
1462 #define mflo1()                                                         \
1463 ({                                                                      \
1464         long mflo1;                                                     \
1465         __asm__(                                                        \
1466         "       .set push                                       \n"     \
1467         "       .set dsp                                        \n"     \
1468         "       mflo %0, $ac1                                   \n"     \
1469         "       .set pop                                        \n"     \
1470         : "=r" (mflo1));                                                \
1471         mflo1;                                                          \
1472 })
1473
1474 #define mflo2()                                                         \
1475 ({                                                                      \
1476         long mflo2;                                                     \
1477         __asm__(                                                        \
1478         "       .set push                                       \n"     \
1479         "       .set dsp                                        \n"     \
1480         "       mflo %0, $ac2                                   \n"     \
1481         "       .set pop                                        \n"     \
1482         : "=r" (mflo2));                                                \
1483         mflo2;                                                          \
1484 })
1485
1486 #define mflo3()                                                         \
1487 ({                                                                      \
1488         long mflo3;                                                     \
1489         __asm__(                                                        \
1490         "       .set push                                       \n"     \
1491         "       .set dsp                                        \n"     \
1492         "       mflo %0, $ac3                                   \n"     \
1493         "       .set pop                                        \n"     \
1494         : "=r" (mflo3));                                                \
1495         mflo3;                                                          \
1496 })
1497
1498 #define mfhi0()                                                         \
1499 ({                                                                      \
1500         long mfhi0;                                                     \
1501         __asm__(                                                        \
1502         "       .set push                                       \n"     \
1503         "       .set dsp                                        \n"     \
1504         "       mfhi %0, $ac0                                   \n"     \
1505         "       .set pop                                        \n"     \
1506         : "=r" (mfhi0));                                                \
1507         mfhi0;                                                          \
1508 })
1509
1510 #define mfhi1()                                                         \
1511 ({                                                                      \
1512         long mfhi1;                                                     \
1513         __asm__(                                                        \
1514         "       .set push                                       \n"     \
1515         "       .set dsp                                        \n"     \
1516         "       mfhi %0, $ac1                                   \n"     \
1517         "       .set pop                                        \n"     \
1518         : "=r" (mfhi1));                                                \
1519         mfhi1;                                                          \
1520 })
1521
1522 #define mfhi2()                                                         \
1523 ({                                                                      \
1524         long mfhi2;                                                     \
1525         __asm__(                                                        \
1526         "       .set push                                       \n"     \
1527         "       .set dsp                                        \n"     \
1528         "       mfhi %0, $ac2                                   \n"     \
1529         "       .set pop                                        \n"     \
1530         : "=r" (mfhi2));                                                \
1531         mfhi2;                                                          \
1532 })
1533
1534 #define mfhi3()                                                         \
1535 ({                                                                      \
1536         long mfhi3;                                                     \
1537         __asm__(                                                        \
1538         "       .set push                                       \n"     \
1539         "       .set dsp                                        \n"     \
1540         "       mfhi %0, $ac3                                   \n"     \
1541         "       .set pop                                        \n"     \
1542         : "=r" (mfhi3));                                                \
1543         mfhi3;                                                          \
1544 })
1545
1546
1547 #define mtlo0(x)                                                        \
1548 ({                                                                      \
1549         __asm__(                                                        \
1550         "       .set push                                       \n"     \
1551         "       .set dsp                                        \n"     \
1552         "       mtlo %0, $ac0                                   \n"     \
1553         "       .set pop                                        \n"     \
1554         :                                                               \
1555         : "r" (x));                                                     \
1556 })
1557
1558 #define mtlo1(x)                                                        \
1559 ({                                                                      \
1560         __asm__(                                                        \
1561         "       .set push                                       \n"     \
1562         "       .set dsp                                        \n"     \
1563         "       mtlo %0, $ac1                                   \n"     \
1564         "       .set pop                                        \n"     \
1565         :                                                               \
1566         : "r" (x));                                                     \
1567 })
1568
1569 #define mtlo2(x)                                                        \
1570 ({                                                                      \
1571         __asm__(                                                        \
1572         "       .set push                                       \n"     \
1573         "       .set dsp                                        \n"     \
1574         "       mtlo %0, $ac2                                   \n"     \
1575         "       .set pop                                        \n"     \
1576         :                                                               \
1577         : "r" (x));                                                     \
1578 })
1579
1580 #define mtlo3(x)                                                        \
1581 ({                                                                      \
1582         __asm__(                                                        \
1583         "       .set push                                       \n"     \
1584         "       .set dsp                                        \n"     \
1585         "       mtlo %0, $ac3                                   \n"     \
1586         "       .set pop                                        \n"     \
1587         :                                                               \
1588         : "r" (x));                                                     \
1589 })
1590
1591 #define mthi0(x)                                                        \
1592 ({                                                                      \
1593         __asm__(                                                        \
1594         "       .set push                                       \n"     \
1595         "       .set dsp                                        \n"     \
1596         "       mthi %0, $ac0                                   \n"     \
1597         "       .set pop                                        \n"     \
1598         :                                                               \
1599         : "r" (x));                                                     \
1600 })
1601
1602 #define mthi1(x)                                                        \
1603 ({                                                                      \
1604         __asm__(                                                        \
1605         "       .set push                                       \n"     \
1606         "       .set dsp                                        \n"     \
1607         "       mthi %0, $ac1                                   \n"     \
1608         "       .set pop                                        \n"     \
1609         :                                                               \
1610         : "r" (x));                                                     \
1611 })
1612
1613 #define mthi2(x)                                                        \
1614 ({                                                                      \
1615         __asm__(                                                        \
1616         "       .set push                                       \n"     \
1617         "       .set dsp                                        \n"     \
1618         "       mthi %0, $ac2                                   \n"     \
1619         "       .set pop                                        \n"     \
1620         :                                                               \
1621         : "r" (x));                                                     \
1622 })
1623
1624 #define mthi3(x)                                                        \
1625 ({                                                                      \
1626         __asm__(                                                        \
1627         "       .set push                                       \n"     \
1628         "       .set dsp                                        \n"     \
1629         "       mthi %0, $ac3                                   \n"     \
1630         "       .set pop                                        \n"     \
1631         :                                                               \
1632         : "r" (x));                                                     \
1633 })
1634
1635 #else
1636
1637 #ifdef CONFIG_CPU_MICROMIPS
1638 #define rddsp(mask)                                                     \
1639 ({                                                                      \
1640         unsigned int __res;                                             \
1641                                                                         \
1642         __asm__ __volatile__(                                           \
1643         "       .set    push                                    \n"     \
1644         "       .set    noat                                    \n"     \
1645         "       # rddsp $1, %x1                                 \n"     \
1646         "       .hword  ((0x0020067c | (%x1 << 14)) >> 16)      \n"     \
1647         "       .hword  ((0x0020067c | (%x1 << 14)) & 0xffff)   \n"     \
1648         "       move    %0, $1                                  \n"     \
1649         "       .set    pop                                     \n"     \
1650         : "=r" (__res)                                                  \
1651         : "i" (mask));                                                  \
1652         __res;                                                          \
1653 })
1654
1655 #define wrdsp(val, mask)                                                \
1656 do {                                                                    \
1657         __asm__ __volatile__(                                           \
1658         "       .set    push                                    \n"     \
1659         "       .set    noat                                    \n"     \
1660         "       move    $1, %0                                  \n"     \
1661         "       # wrdsp $1, %x1                                 \n"     \
1662         "       .hword  ((0x0020167c | (%x1 << 14)) >> 16)      \n"     \
1663         "       .hword  ((0x0020167c | (%x1 << 14)) & 0xffff)   \n"     \
1664         "       .set    pop                                     \n"     \
1665         :                                                               \
1666         : "r" (val), "i" (mask));                                       \
1667 } while (0)
1668
1669 #define _umips_dsp_mfxxx(ins)                                           \
1670 ({                                                                      \
1671         unsigned long __treg;                                           \
1672                                                                         \
1673         __asm__ __volatile__(                                           \
1674         "       .set    push                                    \n"     \
1675         "       .set    noat                                    \n"     \
1676         "       .hword  0x0001                                  \n"     \
1677         "       .hword  %x1                                     \n"     \
1678         "       move    %0, $1                                  \n"     \
1679         "       .set    pop                                     \n"     \
1680         : "=r" (__treg)                                                 \
1681         : "i" (ins));                                                   \
1682         __treg;                                                         \
1683 })
1684
1685 #define _umips_dsp_mtxxx(val, ins)                                      \
1686 do {                                                                    \
1687         __asm__ __volatile__(                                           \
1688         "       .set    push                                    \n"     \
1689         "       .set    noat                                    \n"     \
1690         "       move    $1, %0                                  \n"     \
1691         "       .hword  0x0001                                  \n"     \
1692         "       .hword  %x1                                     \n"     \
1693         "       .set    pop                                     \n"     \
1694         :                                                               \
1695         : "r" (val), "i" (ins));                                        \
1696 } while (0)
1697
1698 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1699 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1700
1701 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1702 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1703
1704 #define mflo0() _umips_dsp_mflo(0)
1705 #define mflo1() _umips_dsp_mflo(1)
1706 #define mflo2() _umips_dsp_mflo(2)
1707 #define mflo3() _umips_dsp_mflo(3)
1708
1709 #define mfhi0() _umips_dsp_mfhi(0)
1710 #define mfhi1() _umips_dsp_mfhi(1)
1711 #define mfhi2() _umips_dsp_mfhi(2)
1712 #define mfhi3() _umips_dsp_mfhi(3)
1713
1714 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1715 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1716 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1717 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1718
1719 #define mthi0(x) _umips_dsp_mthi(x, 0)
1720 #define mthi1(x) _umips_dsp_mthi(x, 1)
1721 #define mthi2(x) _umips_dsp_mthi(x, 2)
1722 #define mthi3(x) _umips_dsp_mthi(x, 3)
1723
1724 #else  /* !CONFIG_CPU_MICROMIPS */
1725 #define rddsp(mask)                                                     \
1726 ({                                                                      \
1727         unsigned int __res;                                             \
1728                                                                         \
1729         __asm__ __volatile__(                                           \
1730         "       .set    push                            \n"             \
1731         "       .set    noat                            \n"             \
1732         "       # rddsp $1, %x1                         \n"             \
1733         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1734         "       move    %0, $1                          \n"             \
1735         "       .set    pop                             \n"             \
1736         : "=r" (__res)                                                  \
1737         : "i" (mask));                                                  \
1738         __res;                                                          \
1739 })
1740
1741 #define wrdsp(val, mask)                                                \
1742 do {                                                                    \
1743         __asm__ __volatile__(                                           \
1744         "       .set    push                                    \n"     \
1745         "       .set    noat                                    \n"     \
1746         "       move    $1, %0                                  \n"     \
1747         "       # wrdsp $1, %x1                                 \n"     \
1748         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1749         "       .set    pop                                     \n"     \
1750         :                                                               \
1751         : "r" (val), "i" (mask));                                       \
1752 } while (0)
1753
1754 #define _dsp_mfxxx(ins)                                                 \
1755 ({                                                                      \
1756         unsigned long __treg;                                           \
1757                                                                         \
1758         __asm__ __volatile__(                                           \
1759         "       .set    push                                    \n"     \
1760         "       .set    noat                                    \n"     \
1761         "       .word   (0x00000810 | %1)                       \n"     \
1762         "       move    %0, $1                                  \n"     \
1763         "       .set    pop                                     \n"     \
1764         : "=r" (__treg)                                                 \
1765         : "i" (ins));                                                   \
1766         __treg;                                                         \
1767 })
1768
1769 #define _dsp_mtxxx(val, ins)                                            \
1770 do {                                                                    \
1771         __asm__ __volatile__(                                           \
1772         "       .set    push                                    \n"     \
1773         "       .set    noat                                    \n"     \
1774         "       move    $1, %0                                  \n"     \
1775         "       .word   (0x00200011 | %1)                       \n"     \
1776         "       .set    pop                                     \n"     \
1777         :                                                               \
1778         : "r" (val), "i" (ins));                                        \
1779 } while (0)
1780
1781 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1782 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1783
1784 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1785 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1786
1787 #define mflo0() _dsp_mflo(0)
1788 #define mflo1() _dsp_mflo(1)
1789 #define mflo2() _dsp_mflo(2)
1790 #define mflo3() _dsp_mflo(3)
1791
1792 #define mfhi0() _dsp_mfhi(0)
1793 #define mfhi1() _dsp_mfhi(1)
1794 #define mfhi2() _dsp_mfhi(2)
1795 #define mfhi3() _dsp_mfhi(3)
1796
1797 #define mtlo0(x) _dsp_mtlo(x, 0)
1798 #define mtlo1(x) _dsp_mtlo(x, 1)
1799 #define mtlo2(x) _dsp_mtlo(x, 2)
1800 #define mtlo3(x) _dsp_mtlo(x, 3)
1801
1802 #define mthi0(x) _dsp_mthi(x, 0)
1803 #define mthi1(x) _dsp_mthi(x, 1)
1804 #define mthi2(x) _dsp_mthi(x, 2)
1805 #define mthi3(x) _dsp_mthi(x, 3)
1806
1807 #endif /* CONFIG_CPU_MICROMIPS */
1808 #endif
1809
1810 /*
1811  * TLB operations.
1812  *
1813  * It is responsibility of the caller to take care of any TLB hazards.
1814  */
1815 static inline void tlb_probe(void)
1816 {
1817         __asm__ __volatile__(
1818                 ".set noreorder\n\t"
1819                 "tlbp\n\t"
1820                 ".set reorder");
1821 }
1822
1823 static inline void tlb_read(void)
1824 {
1825 #if MIPS34K_MISSED_ITLB_WAR
1826         int res = 0;
1827
1828         __asm__ __volatile__(
1829         "       .set    push                                    \n"
1830         "       .set    noreorder                               \n"
1831         "       .set    noat                                    \n"
1832         "       .set    mips32r2                                \n"
1833         "       .word   0x41610001              # dvpe $1       \n"
1834         "       move    %0, $1                                  \n"
1835         "       ehb                                             \n"
1836         "       .set    pop                                     \n"
1837         : "=r" (res));
1838
1839         instruction_hazard();
1840 #endif
1841
1842         __asm__ __volatile__(
1843                 ".set noreorder\n\t"
1844                 "tlbr\n\t"
1845                 ".set reorder");
1846
1847 #if MIPS34K_MISSED_ITLB_WAR
1848         if ((res & _ULCAST_(1)))
1849                 __asm__ __volatile__(
1850                 "       .set    push                            \n"
1851                 "       .set    noreorder                       \n"
1852                 "       .set    noat                            \n"
1853                 "       .set    mips32r2                        \n"
1854                 "       .word   0x41600021      # evpe          \n"
1855                 "       ehb                                     \n"
1856                 "       .set    pop                             \n");
1857 #endif
1858 }
1859
1860 static inline void tlb_write_indexed(void)
1861 {
1862         __asm__ __volatile__(
1863                 ".set noreorder\n\t"
1864                 "tlbwi\n\t"
1865                 ".set reorder");
1866 }
1867
1868 static inline void tlb_write_random(void)
1869 {
1870         __asm__ __volatile__(
1871                 ".set noreorder\n\t"
1872                 "tlbwr\n\t"
1873                 ".set reorder");
1874 }
1875
1876 /*
1877  * Manipulate bits in a c0 register.
1878  */
1879 #define __BUILD_SET_C0(name)                                    \
1880 static inline unsigned int                                      \
1881 set_c0_##name(unsigned int set)                                 \
1882 {                                                               \
1883         unsigned int res, new;                                  \
1884                                                                 \
1885         res = read_c0_##name();                                 \
1886         new = res | set;                                        \
1887         write_c0_##name(new);                                   \
1888                                                                 \
1889         return res;                                             \
1890 }                                                               \
1891                                                                 \
1892 static inline unsigned int                                      \
1893 clear_c0_##name(unsigned int clear)                             \
1894 {                                                               \
1895         unsigned int res, new;                                  \
1896                                                                 \
1897         res = read_c0_##name();                                 \
1898         new = res & ~clear;                                     \
1899         write_c0_##name(new);                                   \
1900                                                                 \
1901         return res;                                             \
1902 }                                                               \
1903                                                                 \
1904 static inline unsigned int                                      \
1905 change_c0_##name(unsigned int change, unsigned int val)         \
1906 {                                                               \
1907         unsigned int res, new;                                  \
1908                                                                 \
1909         res = read_c0_##name();                                 \
1910         new = res & ~change;                                    \
1911         new |= (val & change);                                  \
1912         write_c0_##name(new);                                   \
1913                                                                 \
1914         return res;                                             \
1915 }
1916
1917 __BUILD_SET_C0(status)
1918 __BUILD_SET_C0(cause)
1919 __BUILD_SET_C0(config)
1920 __BUILD_SET_C0(config5)
1921 __BUILD_SET_C0(intcontrol)
1922 __BUILD_SET_C0(intctl)
1923 __BUILD_SET_C0(srsmap)
1924 __BUILD_SET_C0(pagegrain)
1925 __BUILD_SET_C0(brcm_config_0)
1926 __BUILD_SET_C0(brcm_bus_pll)
1927 __BUILD_SET_C0(brcm_reset)
1928 __BUILD_SET_C0(brcm_cmt_intr)
1929 __BUILD_SET_C0(brcm_cmt_ctrl)
1930 __BUILD_SET_C0(brcm_config)
1931 __BUILD_SET_C0(brcm_mode)
1932
1933 /*
1934  * Return low 10 bits of ebase.
1935  * Note that under KVM (MIPSVZ) this returns vcpu id.
1936  */
1937 static inline unsigned int get_ebase_cpunum(void)
1938 {
1939         return read_c0_ebase() & 0x3ff;
1940 }
1941
1942 #endif /* !__ASSEMBLY__ */
1943
1944 #endif /* _ASM_MIPSREGS_H */