1 #ifndef BCM63XX_REGS_H_
2 #define BCM63XX_REGS_H_
4 /*************************************************************************
5 * _REG relative to RSET_PERF
6 *************************************************************************/
8 /* Chip Identifier / Revision register */
9 #define PERF_REV_REG 0x0
10 #define REV_CHIPID_SHIFT 16
11 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
12 #define REV_REVID_SHIFT 0
13 #define REV_REVID_MASK (0xff << REV_REVID_SHIFT)
15 /* Clock Control register */
16 #define PERF_CKCTL_REG 0x4
18 #define CKCTL_3368_MAC_EN (1 << 3)
19 #define CKCTL_3368_TC_EN (1 << 5)
20 #define CKCTL_3368_US_TOP_EN (1 << 6)
21 #define CKCTL_3368_DS_TOP_EN (1 << 7)
22 #define CKCTL_3368_APM_EN (1 << 8)
23 #define CKCTL_3368_SPI_EN (1 << 9)
24 #define CKCTL_3368_USBS_EN (1 << 10)
25 #define CKCTL_3368_BMU_EN (1 << 11)
26 #define CKCTL_3368_PCM_EN (1 << 12)
27 #define CKCTL_3368_NTP_EN (1 << 13)
28 #define CKCTL_3368_ACP_B_EN (1 << 14)
29 #define CKCTL_3368_ACP_A_EN (1 << 15)
30 #define CKCTL_3368_EMUSB_EN (1 << 17)
31 #define CKCTL_3368_ENET0_EN (1 << 18)
32 #define CKCTL_3368_ENET1_EN (1 << 19)
33 #define CKCTL_3368_USBU_EN (1 << 20)
34 #define CKCTL_3368_EPHY_EN (1 << 21)
36 #define CKCTL_3368_ALL_SAFE_EN (CKCTL_3368_MAC_EN | \
38 CKCTL_3368_US_TOP_EN | \
39 CKCTL_3368_DS_TOP_EN | \
42 CKCTL_3368_USBS_EN | \
46 CKCTL_3368_ACP_B_EN | \
47 CKCTL_3368_ACP_A_EN | \
48 CKCTL_3368_EMUSB_EN | \
51 #define CKCTL_6328_PHYMIPS_EN (1 << 0)
52 #define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
53 #define CKCTL_6328_ADSL_AFE_EN (1 << 2)
54 #define CKCTL_6328_ADSL_EN (1 << 3)
55 #define CKCTL_6328_MIPS_EN (1 << 4)
56 #define CKCTL_6328_SAR_EN (1 << 5)
57 #define CKCTL_6328_PCM_EN (1 << 6)
58 #define CKCTL_6328_USBD_EN (1 << 7)
59 #define CKCTL_6328_USBH_EN (1 << 8)
60 #define CKCTL_6328_HSSPI_EN (1 << 9)
61 #define CKCTL_6328_PCIE_EN (1 << 10)
62 #define CKCTL_6328_ROBOSW_EN (1 << 11)
64 #define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \
65 CKCTL_6328_ADSL_QPROC_EN | \
66 CKCTL_6328_ADSL_AFE_EN | \
67 CKCTL_6328_ADSL_EN | \
70 CKCTL_6328_USBD_EN | \
71 CKCTL_6328_USBH_EN | \
72 CKCTL_6328_ROBOSW_EN | \
75 #define CKCTL_6338_ADSLPHY_EN (1 << 0)
76 #define CKCTL_6338_MPI_EN (1 << 1)
77 #define CKCTL_6338_DRAM_EN (1 << 2)
78 #define CKCTL_6338_ENET_EN (1 << 4)
79 #define CKCTL_6338_USBS_EN (1 << 4)
80 #define CKCTL_6338_SAR_EN (1 << 5)
81 #define CKCTL_6338_SPI_EN (1 << 9)
83 #define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \
85 CKCTL_6338_ENET_EN | \
89 /* BCM6345 clock bits are shifted by 16 on the left, because of the test
90 * control register which is 16-bits wide. That way we do not have any
91 * specific BCM6345 code for handling clocks, and writing 0 to the test
92 * control register is fine.
94 #define CKCTL_6345_CPU_EN (1 << 16)
95 #define CKCTL_6345_BUS_EN (1 << 17)
96 #define CKCTL_6345_EBI_EN (1 << 18)
97 #define CKCTL_6345_UART_EN (1 << 19)
98 #define CKCTL_6345_ADSLPHY_EN (1 << 20)
99 #define CKCTL_6345_ENET_EN (1 << 23)
100 #define CKCTL_6345_USBH_EN (1 << 24)
102 #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
103 CKCTL_6345_USBH_EN | \
104 CKCTL_6345_ADSLPHY_EN)
106 #define CKCTL_6348_ADSLPHY_EN (1 << 0)
107 #define CKCTL_6348_MPI_EN (1 << 1)
108 #define CKCTL_6348_SDRAM_EN (1 << 2)
109 #define CKCTL_6348_M2M_EN (1 << 3)
110 #define CKCTL_6348_ENET_EN (1 << 4)
111 #define CKCTL_6348_SAR_EN (1 << 5)
112 #define CKCTL_6348_USBS_EN (1 << 6)
113 #define CKCTL_6348_USBH_EN (1 << 8)
114 #define CKCTL_6348_SPI_EN (1 << 9)
116 #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \
117 CKCTL_6348_M2M_EN | \
118 CKCTL_6348_ENET_EN | \
119 CKCTL_6348_SAR_EN | \
120 CKCTL_6348_USBS_EN | \
121 CKCTL_6348_USBH_EN | \
124 #define CKCTL_6358_ENET_EN (1 << 4)
125 #define CKCTL_6358_ADSLPHY_EN (1 << 5)
126 #define CKCTL_6358_PCM_EN (1 << 8)
127 #define CKCTL_6358_SPI_EN (1 << 9)
128 #define CKCTL_6358_USBS_EN (1 << 10)
129 #define CKCTL_6358_SAR_EN (1 << 11)
130 #define CKCTL_6358_EMUSB_EN (1 << 17)
131 #define CKCTL_6358_ENET0_EN (1 << 18)
132 #define CKCTL_6358_ENET1_EN (1 << 19)
133 #define CKCTL_6358_USBSU_EN (1 << 20)
134 #define CKCTL_6358_EPHY_EN (1 << 21)
136 #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \
137 CKCTL_6358_ADSLPHY_EN | \
138 CKCTL_6358_PCM_EN | \
139 CKCTL_6358_SPI_EN | \
140 CKCTL_6358_USBS_EN | \
141 CKCTL_6358_SAR_EN | \
142 CKCTL_6358_EMUSB_EN | \
143 CKCTL_6358_ENET0_EN | \
144 CKCTL_6358_ENET1_EN | \
145 CKCTL_6358_USBSU_EN | \
148 #define CKCTL_6362_ADSL_QPROC_EN (1 << 1)
149 #define CKCTL_6362_ADSL_AFE_EN (1 << 2)
150 #define CKCTL_6362_ADSL_EN (1 << 3)
151 #define CKCTL_6362_MIPS_EN (1 << 4)
152 #define CKCTL_6362_WLAN_OCP_EN (1 << 5)
153 #define CKCTL_6362_SWPKT_USB_EN (1 << 7)
154 #define CKCTL_6362_SWPKT_SAR_EN (1 << 8)
155 #define CKCTL_6362_SAR_EN (1 << 9)
156 #define CKCTL_6362_ROBOSW_EN (1 << 10)
157 #define CKCTL_6362_PCM_EN (1 << 11)
158 #define CKCTL_6362_USBD_EN (1 << 12)
159 #define CKCTL_6362_USBH_EN (1 << 13)
160 #define CKCTL_6362_IPSEC_EN (1 << 14)
161 #define CKCTL_6362_SPI_EN (1 << 15)
162 #define CKCTL_6362_HSSPI_EN (1 << 16)
163 #define CKCTL_6362_PCIE_EN (1 << 17)
164 #define CKCTL_6362_FAP_EN (1 << 18)
165 #define CKCTL_6362_PHYMIPS_EN (1 << 19)
166 #define CKCTL_6362_NAND_EN (1 << 20)
168 #define CKCTL_6362_ALL_SAFE_EN (CKCTL_6362_PHYMIPS_EN | \
169 CKCTL_6362_ADSL_QPROC_EN | \
170 CKCTL_6362_ADSL_AFE_EN | \
171 CKCTL_6362_ADSL_EN | \
172 CKCTL_6362_SAR_EN | \
173 CKCTL_6362_PCM_EN | \
174 CKCTL_6362_IPSEC_EN | \
175 CKCTL_6362_USBD_EN | \
176 CKCTL_6362_USBH_EN | \
177 CKCTL_6362_ROBOSW_EN | \
181 #define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
182 #define CKCTL_6368_VDSL_AFE_EN (1 << 3)
183 #define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
184 #define CKCTL_6368_VDSL_EN (1 << 5)
185 #define CKCTL_6368_PHYMIPS_EN (1 << 6)
186 #define CKCTL_6368_SWPKT_USB_EN (1 << 7)
187 #define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
188 #define CKCTL_6368_SPI_EN (1 << 9)
189 #define CKCTL_6368_USBD_EN (1 << 10)
190 #define CKCTL_6368_SAR_EN (1 << 11)
191 #define CKCTL_6368_ROBOSW_EN (1 << 12)
192 #define CKCTL_6368_UTOPIA_EN (1 << 13)
193 #define CKCTL_6368_PCM_EN (1 << 14)
194 #define CKCTL_6368_USBH_EN (1 << 15)
195 #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
196 #define CKCTL_6368_NAND_EN (1 << 17)
197 #define CKCTL_6368_IPSEC_EN (1 << 18)
199 #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
200 CKCTL_6368_SWPKT_SAR_EN | \
201 CKCTL_6368_SPI_EN | \
202 CKCTL_6368_USBD_EN | \
203 CKCTL_6368_SAR_EN | \
204 CKCTL_6368_ROBOSW_EN | \
205 CKCTL_6368_UTOPIA_EN | \
206 CKCTL_6368_PCM_EN | \
207 CKCTL_6368_USBH_EN | \
208 CKCTL_6368_DISABLE_GLESS_EN | \
209 CKCTL_6368_NAND_EN | \
212 /* System PLL Control register */
213 #define PERF_SYS_PLL_CTL_REG 0x8
214 #define SYS_PLL_SOFT_RESET 0x1
216 /* Interrupt Mask register */
217 #define PERF_IRQMASK_3368_REG 0xc
218 #define PERF_IRQMASK_6328_REG 0x20
219 #define PERF_IRQMASK_6338_REG 0xc
220 #define PERF_IRQMASK_6345_REG 0xc
221 #define PERF_IRQMASK_6348_REG 0xc
222 #define PERF_IRQMASK_6358_REG 0xc
223 #define PERF_IRQMASK_6362_REG 0x20
224 #define PERF_IRQMASK_6368_REG 0x20
226 /* Interrupt Status register */
227 #define PERF_IRQSTAT_3368_REG 0x10
228 #define PERF_IRQSTAT_6328_REG 0x28
229 #define PERF_IRQSTAT_6338_REG 0x10
230 #define PERF_IRQSTAT_6345_REG 0x10
231 #define PERF_IRQSTAT_6348_REG 0x10
232 #define PERF_IRQSTAT_6358_REG 0x10
233 #define PERF_IRQSTAT_6362_REG 0x28
234 #define PERF_IRQSTAT_6368_REG 0x28
236 /* External Interrupt Configuration register */
237 #define PERF_EXTIRQ_CFG_REG_3368 0x14
238 #define PERF_EXTIRQ_CFG_REG_6328 0x18
239 #define PERF_EXTIRQ_CFG_REG_6338 0x14
240 #define PERF_EXTIRQ_CFG_REG_6345 0x14
241 #define PERF_EXTIRQ_CFG_REG_6348 0x14
242 #define PERF_EXTIRQ_CFG_REG_6358 0x14
243 #define PERF_EXTIRQ_CFG_REG_6362 0x18
244 #define PERF_EXTIRQ_CFG_REG_6368 0x18
246 #define PERF_EXTIRQ_CFG_REG2_6368 0x1c
249 #define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
250 #define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5))
251 #define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10))
252 #define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15))
253 #define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20))
254 #define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25))
255 #define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10)
256 #define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15)
259 #define EXTIRQ_CFG_SENSE(x) (1 << (x))
260 #define EXTIRQ_CFG_STAT(x) (1 << (x + 4))
261 #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8))
262 #define EXTIRQ_CFG_MASK(x) (1 << (x + 12))
263 #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16))
264 #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20))
265 #define EXTIRQ_CFG_CLEAR_ALL (0xf << 8)
266 #define EXTIRQ_CFG_MASK_ALL (0xf << 12)
268 /* Soft Reset register */
269 #define PERF_SOFTRESET_REG 0x28
270 #define PERF_SOFTRESET_6328_REG 0x10
271 #define PERF_SOFTRESET_6358_REG 0x34
272 #define PERF_SOFTRESET_6362_REG 0x10
273 #define PERF_SOFTRESET_6368_REG 0x10
275 #define SOFTRESET_3368_SPI_MASK (1 << 0)
276 #define SOFTRESET_3368_ENET_MASK (1 << 2)
277 #define SOFTRESET_3368_MPI_MASK (1 << 3)
278 #define SOFTRESET_3368_EPHY_MASK (1 << 6)
279 #define SOFTRESET_3368_USBS_MASK (1 << 11)
280 #define SOFTRESET_3368_PCM_MASK (1 << 13)
282 #define SOFTRESET_6328_SPI_MASK (1 << 0)
283 #define SOFTRESET_6328_EPHY_MASK (1 << 1)
284 #define SOFTRESET_6328_SAR_MASK (1 << 2)
285 #define SOFTRESET_6328_ENETSW_MASK (1 << 3)
286 #define SOFTRESET_6328_USBS_MASK (1 << 4)
287 #define SOFTRESET_6328_USBH_MASK (1 << 5)
288 #define SOFTRESET_6328_PCM_MASK (1 << 6)
289 #define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7)
290 #define SOFTRESET_6328_PCIE_MASK (1 << 8)
291 #define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9)
292 #define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10)
294 #define SOFTRESET_6338_SPI_MASK (1 << 0)
295 #define SOFTRESET_6338_ENET_MASK (1 << 2)
296 #define SOFTRESET_6338_USBH_MASK (1 << 3)
297 #define SOFTRESET_6338_USBS_MASK (1 << 4)
298 #define SOFTRESET_6338_ADSL_MASK (1 << 5)
299 #define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
300 #define SOFTRESET_6338_SAR_MASK (1 << 7)
301 #define SOFTRESET_6338_ACLC_MASK (1 << 8)
302 #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
303 #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
304 SOFTRESET_6338_ENET_MASK | \
305 SOFTRESET_6338_USBH_MASK | \
306 SOFTRESET_6338_USBS_MASK | \
307 SOFTRESET_6338_ADSL_MASK | \
308 SOFTRESET_6338_DMAMEM_MASK | \
309 SOFTRESET_6338_SAR_MASK | \
310 SOFTRESET_6338_ACLC_MASK | \
311 SOFTRESET_6338_ADSLMIPSPLL_MASK)
313 #define SOFTRESET_6348_SPI_MASK (1 << 0)
314 #define SOFTRESET_6348_ENET_MASK (1 << 2)
315 #define SOFTRESET_6348_USBH_MASK (1 << 3)
316 #define SOFTRESET_6348_USBS_MASK (1 << 4)
317 #define SOFTRESET_6348_ADSL_MASK (1 << 5)
318 #define SOFTRESET_6348_DMAMEM_MASK (1 << 6)
319 #define SOFTRESET_6348_SAR_MASK (1 << 7)
320 #define SOFTRESET_6348_ACLC_MASK (1 << 8)
321 #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
323 #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \
324 SOFTRESET_6348_ENET_MASK | \
325 SOFTRESET_6348_USBH_MASK | \
326 SOFTRESET_6348_USBS_MASK | \
327 SOFTRESET_6348_ADSL_MASK | \
328 SOFTRESET_6348_DMAMEM_MASK | \
329 SOFTRESET_6348_SAR_MASK | \
330 SOFTRESET_6348_ACLC_MASK | \
331 SOFTRESET_6348_ADSLMIPSPLL_MASK)
333 #define SOFTRESET_6358_SPI_MASK (1 << 0)
334 #define SOFTRESET_6358_ENET_MASK (1 << 2)
335 #define SOFTRESET_6358_MPI_MASK (1 << 3)
336 #define SOFTRESET_6358_EPHY_MASK (1 << 6)
337 #define SOFTRESET_6358_SAR_MASK (1 << 7)
338 #define SOFTRESET_6358_USBH_MASK (1 << 12)
339 #define SOFTRESET_6358_PCM_MASK (1 << 13)
340 #define SOFTRESET_6358_ADSL_MASK (1 << 14)
342 #define SOFTRESET_6362_SPI_MASK (1 << 0)
343 #define SOFTRESET_6362_IPSEC_MASK (1 << 1)
344 #define SOFTRESET_6362_EPHY_MASK (1 << 2)
345 #define SOFTRESET_6362_SAR_MASK (1 << 3)
346 #define SOFTRESET_6362_ENETSW_MASK (1 << 4)
347 #define SOFTRESET_6362_USBS_MASK (1 << 5)
348 #define SOFTRESET_6362_USBH_MASK (1 << 6)
349 #define SOFTRESET_6362_PCM_MASK (1 << 7)
350 #define SOFTRESET_6362_PCIE_CORE_MASK (1 << 8)
351 #define SOFTRESET_6362_PCIE_MASK (1 << 9)
352 #define SOFTRESET_6362_PCIE_EXT_MASK (1 << 10)
353 #define SOFTRESET_6362_WLAN_SHIM_MASK (1 << 11)
354 #define SOFTRESET_6362_DDR_PHY_MASK (1 << 12)
355 #define SOFTRESET_6362_FAP_MASK (1 << 13)
356 #define SOFTRESET_6362_WLAN_UBUS_MASK (1 << 14)
358 #define SOFTRESET_6368_SPI_MASK (1 << 0)
359 #define SOFTRESET_6368_MPI_MASK (1 << 3)
360 #define SOFTRESET_6368_EPHY_MASK (1 << 6)
361 #define SOFTRESET_6368_SAR_MASK (1 << 7)
362 #define SOFTRESET_6368_ENETSW_MASK (1 << 10)
363 #define SOFTRESET_6368_USBS_MASK (1 << 11)
364 #define SOFTRESET_6368_USBH_MASK (1 << 12)
365 #define SOFTRESET_6368_PCM_MASK (1 << 13)
367 /* MIPS PLL control register */
368 #define PERF_MIPSPLLCTL_REG 0x34
369 #define MIPSPLLCTL_N1_SHIFT 20
370 #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
371 #define MIPSPLLCTL_N2_SHIFT 15
372 #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
373 #define MIPSPLLCTL_M1REF_SHIFT 12
374 #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
375 #define MIPSPLLCTL_M2REF_SHIFT 9
376 #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
377 #define MIPSPLLCTL_M1CPU_SHIFT 6
378 #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
379 #define MIPSPLLCTL_M1BUS_SHIFT 3
380 #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
381 #define MIPSPLLCTL_M2BUS_SHIFT 0
382 #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
384 /* ADSL PHY PLL Control register */
385 #define PERF_ADSLPLLCTL_REG 0x38
386 #define ADSLPLLCTL_N1_SHIFT 20
387 #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
388 #define ADSLPLLCTL_N2_SHIFT 15
389 #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
390 #define ADSLPLLCTL_M1REF_SHIFT 12
391 #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
392 #define ADSLPLLCTL_M2REF_SHIFT 9
393 #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
394 #define ADSLPLLCTL_M1CPU_SHIFT 6
395 #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
396 #define ADSLPLLCTL_M1BUS_SHIFT 3
397 #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
398 #define ADSLPLLCTL_M2BUS_SHIFT 0
399 #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
401 #define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \
402 (((n1) << ADSLPLLCTL_N1_SHIFT) | \
403 ((n2) << ADSLPLLCTL_N2_SHIFT) | \
404 ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
405 ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
406 ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
407 ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
408 ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
411 /*************************************************************************
412 * _REG relative to RSET_TIMER
413 *************************************************************************/
415 #define BCM63XX_TIMER_COUNT 4
416 #define TIMER_T0_ID 0
417 #define TIMER_T1_ID 1
418 #define TIMER_T2_ID 2
419 #define TIMER_WDT_ID 3
421 /* Timer irqstat register */
422 #define TIMER_IRQSTAT_REG 0
423 #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x))
424 #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
425 #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1)
426 #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2)
427 #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3)
428 #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8))
429 #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8)
430 #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
431 #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
433 /* Timer control register */
434 #define TIMER_CTLx_REG(x) (0x4 + (x * 4))
435 #define TIMER_CTL0_REG 0x4
436 #define TIMER_CTL1_REG 0x8
437 #define TIMER_CTL2_REG 0xC
438 #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
439 #define TIMER_CTL_MONOTONIC_MASK (1 << 30)
440 #define TIMER_CTL_ENABLE_MASK (1 << 31)
443 /*************************************************************************
444 * _REG relative to RSET_WDT
445 *************************************************************************/
447 /* Watchdog default count register */
448 #define WDT_DEFVAL_REG 0x0
450 /* Watchdog control register */
451 #define WDT_CTL_REG 0x4
453 /* Watchdog control register constants */
454 #define WDT_START_1 (0xff00)
455 #define WDT_START_2 (0x00ff)
456 #define WDT_STOP_1 (0xee00)
457 #define WDT_STOP_2 (0x00ee)
459 /* Watchdog reset length register */
460 #define WDT_RSTLEN_REG 0x8
462 /* Watchdog soft reset register (BCM6328 only) */
463 #define WDT_SOFTRESET_REG 0xc
465 /*************************************************************************
466 * _REG relative to RSET_UARTx
467 *************************************************************************/
469 /* UART Control Register */
470 #define UART_CTL_REG 0x0
471 #define UART_CTL_RXTMOUTCNT_SHIFT 0
472 #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
473 #define UART_CTL_RSTTXDN_SHIFT 5
474 #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
475 #define UART_CTL_RSTRXFIFO_SHIFT 6
476 #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
477 #define UART_CTL_RSTTXFIFO_SHIFT 7
478 #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
479 #define UART_CTL_STOPBITS_SHIFT 8
480 #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
481 #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
482 #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
483 #define UART_CTL_BITSPERSYM_SHIFT 12
484 #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
485 #define UART_CTL_XMITBRK_SHIFT 14
486 #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
487 #define UART_CTL_RSVD_SHIFT 15
488 #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
489 #define UART_CTL_RXPAREVEN_SHIFT 16
490 #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
491 #define UART_CTL_RXPAREN_SHIFT 17
492 #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
493 #define UART_CTL_TXPAREVEN_SHIFT 18
494 #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
495 #define UART_CTL_TXPAREN_SHIFT 18
496 #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
497 #define UART_CTL_LOOPBACK_SHIFT 20
498 #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
499 #define UART_CTL_RXEN_SHIFT 21
500 #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
501 #define UART_CTL_TXEN_SHIFT 22
502 #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
503 #define UART_CTL_BRGEN_SHIFT 23
504 #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
506 /* UART Baudword register */
507 #define UART_BAUD_REG 0x4
509 /* UART Misc Control register */
510 #define UART_MCTL_REG 0x8
511 #define UART_MCTL_DTR_SHIFT 0
512 #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
513 #define UART_MCTL_RTS_SHIFT 1
514 #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
515 #define UART_MCTL_RXFIFOTHRESH_SHIFT 8
516 #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
517 #define UART_MCTL_TXFIFOTHRESH_SHIFT 12
518 #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
519 #define UART_MCTL_RXFIFOFILL_SHIFT 16
520 #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
521 #define UART_MCTL_TXFIFOFILL_SHIFT 24
522 #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
524 /* UART External Input Configuration register */
525 #define UART_EXTINP_REG 0xc
526 #define UART_EXTINP_RI_SHIFT 0
527 #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
528 #define UART_EXTINP_CTS_SHIFT 1
529 #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
530 #define UART_EXTINP_DCD_SHIFT 2
531 #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
532 #define UART_EXTINP_DSR_SHIFT 3
533 #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
534 #define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
535 #define UART_EXTINP_IRMASK(x) (1 << (x + 8))
536 #define UART_EXTINP_IR_RI 0
537 #define UART_EXTINP_IR_CTS 1
538 #define UART_EXTINP_IR_DCD 2
539 #define UART_EXTINP_IR_DSR 3
540 #define UART_EXTINP_RI_NOSENSE_SHIFT 16
541 #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
542 #define UART_EXTINP_CTS_NOSENSE_SHIFT 17
543 #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
544 #define UART_EXTINP_DCD_NOSENSE_SHIFT 18
545 #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
546 #define UART_EXTINP_DSR_NOSENSE_SHIFT 19
547 #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
549 /* UART Interrupt register */
550 #define UART_IR_REG 0x10
551 #define UART_IR_MASK(x) (1 << (x + 16))
552 #define UART_IR_STAT(x) (1 << (x))
553 #define UART_IR_EXTIP 0
554 #define UART_IR_TXUNDER 1
555 #define UART_IR_TXOVER 2
556 #define UART_IR_TXTRESH 3
557 #define UART_IR_TXRDLATCH 4
558 #define UART_IR_TXEMPTY 5
559 #define UART_IR_RXUNDER 6
560 #define UART_IR_RXOVER 7
561 #define UART_IR_RXTIMEOUT 8
562 #define UART_IR_RXFULL 9
563 #define UART_IR_RXTHRESH 10
564 #define UART_IR_RXNOTEMPTY 11
565 #define UART_IR_RXFRAMEERR 12
566 #define UART_IR_RXPARERR 13
567 #define UART_IR_RXBRK 14
568 #define UART_IR_TXDONE 15
570 /* UART Fifo register */
571 #define UART_FIFO_REG 0x14
572 #define UART_FIFO_VALID_SHIFT 0
573 #define UART_FIFO_VALID_MASK 0xff
574 #define UART_FIFO_FRAMEERR_SHIFT 8
575 #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
576 #define UART_FIFO_PARERR_SHIFT 9
577 #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
578 #define UART_FIFO_BRKDET_SHIFT 10
579 #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
580 #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
581 UART_FIFO_PARERR_MASK | \
582 UART_FIFO_BRKDET_MASK)
585 /*************************************************************************
586 * _REG relative to RSET_GPIO
587 *************************************************************************/
590 #define GPIO_CTL_HI_REG 0x0
591 #define GPIO_CTL_LO_REG 0x4
592 #define GPIO_DATA_HI_REG 0x8
593 #define GPIO_DATA_LO_REG 0xC
594 #define GPIO_DATA_LO_REG_6345 0x8
596 /* GPIO mux registers and constants */
597 #define GPIO_MODE_REG 0x18
599 #define GPIO_MODE_6348_G4_DIAG 0x00090000
600 #define GPIO_MODE_6348_G4_UTOPIA 0x00080000
601 #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
602 #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
603 #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
604 #define GPIO_MODE_6348_G3_DIAG 0x00009000
605 #define GPIO_MODE_6348_G3_UTOPIA 0x00008000
606 #define GPIO_MODE_6348_G3_EXT_MII 0x00007000
607 #define GPIO_MODE_6348_G2_DIAG 0x00000900
608 #define GPIO_MODE_6348_G2_PCI 0x00000500
609 #define GPIO_MODE_6348_G1_DIAG 0x00000090
610 #define GPIO_MODE_6348_G1_UTOPIA 0x00000080
611 #define GPIO_MODE_6348_G1_SPI_UART 0x00000060
612 #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
613 #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
614 #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
615 #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
616 #define GPIO_MODE_6348_G0_DIAG 0x00000009
617 #define GPIO_MODE_6348_G0_EXT_MII 0x00000007
619 #define GPIO_MODE_6358_EXTRACS (1 << 5)
620 #define GPIO_MODE_6358_UART1 (1 << 6)
621 #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
622 #define GPIO_MODE_6358_SERIAL_LED (1 << 10)
623 #define GPIO_MODE_6358_UTOPIA (1 << 12)
625 #define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0)
626 #define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1)
627 #define GPIO_MODE_6368_SYS_IRQ (1 << 2)
628 #define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3)
629 #define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4)
630 #define GPIO_MODE_6368_INET_LED (1 << 5)
631 #define GPIO_MODE_6368_EPHY0_LED (1 << 6)
632 #define GPIO_MODE_6368_EPHY1_LED (1 << 7)
633 #define GPIO_MODE_6368_EPHY2_LED (1 << 8)
634 #define GPIO_MODE_6368_EPHY3_LED (1 << 9)
635 #define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10)
636 #define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11)
637 #define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12)
638 #define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13)
639 #define GPIO_MODE_6368_USBD_LED (1 << 14)
640 #define GPIO_MODE_6368_NTR_PULSE (1 << 15)
641 #define GPIO_MODE_6368_PCI_REQ1 (1 << 16)
642 #define GPIO_MODE_6368_PCI_GNT1 (1 << 17)
643 #define GPIO_MODE_6368_PCI_INTB (1 << 18)
644 #define GPIO_MODE_6368_PCI_REQ0 (1 << 19)
645 #define GPIO_MODE_6368_PCI_GNT0 (1 << 20)
646 #define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22)
647 #define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23)
648 #define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24)
649 #define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25)
650 #define GPIO_MODE_6368_EBI_CS2 (1 << 26)
651 #define GPIO_MODE_6368_EBI_CS3 (1 << 27)
652 #define GPIO_MODE_6368_SPI_SSN2 (1 << 28)
653 #define GPIO_MODE_6368_SPI_SSN3 (1 << 29)
654 #define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
655 #define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
658 #define GPIO_PINMUX_OTHR_REG 0x24
659 #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
660 #define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
661 #define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
662 #define GPIO_PINMUX_OTHR_6328_USB_DEV (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
664 #define GPIO_BASEMODE_6368_REG 0x38
665 #define GPIO_BASEMODE_6368_UART2 0x1
666 #define GPIO_BASEMODE_6368_GPIO 0x0
667 #define GPIO_BASEMODE_6368_MASK 0x7
668 /* those bits must be kept as read in gpio basemode register*/
670 #define GPIO_STRAPBUS_REG 0x40
671 #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
672 #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
673 #define STRAPBUS_6368_BOOT_SEL_MASK 0x3
674 #define STRAPBUS_6368_BOOT_SEL_NAND 0
675 #define STRAPBUS_6368_BOOT_SEL_SERIAL 1
676 #define STRAPBUS_6368_BOOT_SEL_PARALLEL 3
679 /*************************************************************************
680 * _REG relative to RSET_ENET
681 *************************************************************************/
683 /* Receiver Configuration register */
684 #define ENET_RXCFG_REG 0x0
685 #define ENET_RXCFG_ALLMCAST_SHIFT 1
686 #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT)
687 #define ENET_RXCFG_PROMISC_SHIFT 3
688 #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT)
689 #define ENET_RXCFG_LOOPBACK_SHIFT 4
690 #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT)
691 #define ENET_RXCFG_ENFLOW_SHIFT 5
692 #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT)
694 /* Receive Maximum Length register */
695 #define ENET_RXMAXLEN_REG 0x4
696 #define ENET_RXMAXLEN_SHIFT 0
697 #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
699 /* Transmit Maximum Length register */
700 #define ENET_TXMAXLEN_REG 0x8
701 #define ENET_TXMAXLEN_SHIFT 0
702 #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
704 /* MII Status/Control register */
705 #define ENET_MIISC_REG 0x10
706 #define ENET_MIISC_MDCFREQDIV_SHIFT 0
707 #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
708 #define ENET_MIISC_PREAMBLEEN_SHIFT 7
709 #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
711 /* MII Data register */
712 #define ENET_MIIDATA_REG 0x14
713 #define ENET_MIIDATA_DATA_SHIFT 0
714 #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
715 #define ENET_MIIDATA_TA_SHIFT 16
716 #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
717 #define ENET_MIIDATA_REG_SHIFT 18
718 #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
719 #define ENET_MIIDATA_PHYID_SHIFT 23
720 #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
721 #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
722 #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
724 /* Ethernet Interrupt Mask register */
725 #define ENET_IRMASK_REG 0x18
727 /* Ethernet Interrupt register */
728 #define ENET_IR_REG 0x1c
729 #define ENET_IR_MII (1 << 0)
730 #define ENET_IR_MIB (1 << 1)
731 #define ENET_IR_FLOWC (1 << 2)
733 /* Ethernet Control register */
734 #define ENET_CTL_REG 0x2c
735 #define ENET_CTL_ENABLE_SHIFT 0
736 #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT)
737 #define ENET_CTL_DISABLE_SHIFT 1
738 #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT)
739 #define ENET_CTL_SRESET_SHIFT 2
740 #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT)
741 #define ENET_CTL_EPHYSEL_SHIFT 3
742 #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT)
744 /* Transmit Control register */
745 #define ENET_TXCTL_REG 0x30
746 #define ENET_TXCTL_FD_SHIFT 0
747 #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT)
749 /* Transmit Watermask register */
750 #define ENET_TXWMARK_REG 0x34
751 #define ENET_TXWMARK_WM_SHIFT 0
752 #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
754 /* MIB Control register */
755 #define ENET_MIBCTL_REG 0x38
756 #define ENET_MIBCTL_RDCLEAR_SHIFT 0
757 #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
759 /* Perfect Match Data Low register */
760 #define ENET_PML_REG(x) (0x58 + (x) * 8)
761 #define ENET_PMH_REG(x) (0x5c + (x) * 8)
762 #define ENET_PMH_DATAVALID_SHIFT 16
763 #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT)
766 #define ENET_MIB_REG(x) (0x200 + (x) * 4)
767 #define ENET_MIB_REG_COUNT 55
770 /*************************************************************************
771 * _REG relative to RSET_ENETDMA
772 *************************************************************************/
773 #define ENETDMA_CHAN_WIDTH 0x10
774 #define ENETDMA_6345_CHAN_WIDTH 0x40
776 /* Controller Configuration Register */
777 #define ENETDMA_CFG_REG (0x0)
778 #define ENETDMA_CFG_EN_SHIFT 0
779 #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT)
780 #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
782 /* Flow Control Descriptor Low Threshold register */
783 #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
785 /* Flow Control Descriptor High Threshold register */
786 #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
788 /* Flow Control Descriptor Buffer Alloca Threshold register */
789 #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
790 #define ENETDMA_BUFALLOC_FORCE_SHIFT 31
791 #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
793 /* Global interrupt status */
794 #define ENETDMA_GLB_IRQSTAT_REG (0x40)
796 /* Global interrupt mask */
797 #define ENETDMA_GLB_IRQMASK_REG (0x44)
799 /* Channel Configuration register */
800 #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
801 #define ENETDMA_CHANCFG_EN_SHIFT 0
802 #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
803 #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1
804 #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
806 /* Interrupt Control/Status register */
807 #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
808 #define ENETDMA_IR_BUFDONE_MASK (1 << 0)
809 #define ENETDMA_IR_PKTDONE_MASK (1 << 1)
810 #define ENETDMA_IR_NOTOWNER_MASK (1 << 2)
812 /* Interrupt Mask register */
813 #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
815 /* Maximum Burst Length */
816 #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
818 /* Ring Start Address register */
819 #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
821 /* State Ram Word 2 */
822 #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
824 /* State Ram Word 3 */
825 #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
827 /* State Ram Word 4 */
828 #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
830 /* Broadcom 6345 ENET DMA definitions */
831 #define ENETDMA_6345_CHANCFG_REG (0x00)
833 #define ENETDMA_6345_MAXBURST_REG (0x40)
835 #define ENETDMA_6345_RSTART_REG (0x08)
837 #define ENETDMA_6345_LEN_REG (0x0C)
839 #define ENETDMA_6345_IR_REG (0x14)
841 #define ENETDMA_6345_IRMASK_REG (0x18)
843 #define ENETDMA_6345_FC_REG (0x1C)
845 #define ENETDMA_6345_BUFALLOC_REG (0x20)
847 /* Shift down for EOP, SOP and WRAP bits */
848 #define ENETDMA_6345_DESC_SHIFT (3)
850 /*************************************************************************
851 * _REG relative to RSET_ENETDMAC
852 *************************************************************************/
854 /* Channel Configuration register */
855 #define ENETDMAC_CHANCFG_REG (0x0)
856 #define ENETDMAC_CHANCFG_EN_SHIFT 0
857 #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT)
858 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
859 #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
860 #define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
861 #define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
862 #define ENETDMAC_CHANCFG_CHAINING_SHIFT 2
863 #define ENETDMAC_CHANCFG_CHAINING_MASK (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
864 #define ENETDMAC_CHANCFG_WRAP_EN_SHIFT 3
865 #define ENETDMAC_CHANCFG_WRAP_EN_MASK (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
866 #define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4
867 #define ENETDMAC_CHANCFG_FLOWC_EN_MASK (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
869 /* Interrupt Control/Status register */
870 #define ENETDMAC_IR_REG (0x4)
871 #define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
872 #define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
873 #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
875 /* Interrupt Mask register */
876 #define ENETDMAC_IRMASK_REG (0x8)
878 /* Maximum Burst Length */
879 #define ENETDMAC_MAXBURST_REG (0xc)
882 /*************************************************************************
883 * _REG relative to RSET_ENETDMAS
884 *************************************************************************/
886 /* Ring Start Address register */
887 #define ENETDMAS_RSTART_REG (0x0)
889 /* State Ram Word 2 */
890 #define ENETDMAS_SRAM2_REG (0x4)
892 /* State Ram Word 3 */
893 #define ENETDMAS_SRAM3_REG (0x8)
895 /* State Ram Word 4 */
896 #define ENETDMAS_SRAM4_REG (0xc)
899 /*************************************************************************
900 * _REG relative to RSET_ENETSW
901 *************************************************************************/
903 /* Port traffic control */
904 #define ENETSW_PTCTRL_REG(x) (0x0 + (x))
905 #define ENETSW_PTCTRL_RXDIS_MASK (1 << 0)
906 #define ENETSW_PTCTRL_TXDIS_MASK (1 << 1)
908 /* Switch mode register */
909 #define ENETSW_SWMODE_REG (0xb)
910 #define ENETSW_SWMODE_FWD_EN_MASK (1 << 1)
912 /* IMP override Register */
913 #define ENETSW_IMPOV_REG (0xe)
914 #define ENETSW_IMPOV_FORCE_MASK (1 << 7)
915 #define ENETSW_IMPOV_TXFLOW_MASK (1 << 5)
916 #define ENETSW_IMPOV_RXFLOW_MASK (1 << 4)
917 #define ENETSW_IMPOV_1000_MASK (1 << 3)
918 #define ENETSW_IMPOV_100_MASK (1 << 2)
919 #define ENETSW_IMPOV_FDX_MASK (1 << 1)
920 #define ENETSW_IMPOV_LINKUP_MASK (1 << 0)
922 /* Port override Register */
923 #define ENETSW_PORTOV_REG(x) (0x58 + (x))
924 #define ENETSW_PORTOV_ENABLE_MASK (1 << 6)
925 #define ENETSW_PORTOV_TXFLOW_MASK (1 << 5)
926 #define ENETSW_PORTOV_RXFLOW_MASK (1 << 4)
927 #define ENETSW_PORTOV_1000_MASK (1 << 3)
928 #define ENETSW_PORTOV_100_MASK (1 << 2)
929 #define ENETSW_PORTOV_FDX_MASK (1 << 1)
930 #define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
932 /* MDIO control register */
933 #define ENETSW_MDIOC_REG (0xb0)
934 #define ENETSW_MDIOC_EXT_MASK (1 << 16)
935 #define ENETSW_MDIOC_REG_SHIFT 20
936 #define ENETSW_MDIOC_PHYID_SHIFT 25
937 #define ENETSW_MDIOC_RD_MASK (1 << 30)
938 #define ENETSW_MDIOC_WR_MASK (1 << 31)
940 /* MDIO data register */
941 #define ENETSW_MDIOD_REG (0xb4)
943 /* Global Management Configuration Register */
944 #define ENETSW_GMCR_REG (0x200)
945 #define ENETSW_GMCR_RST_MIB_MASK (1 << 0)
948 #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
949 #define ENETSW_MIB_REG_COUNT 47
951 /* Jumbo control register port mask register */
952 #define ENETSW_JMBCTL_PORT_REG (0x4004)
954 /* Jumbo control mib good frame register */
955 #define ENETSW_JMBCTL_MAXSIZE_REG (0x4008)
958 /*************************************************************************
959 * _REG relative to RSET_OHCI_PRIV
960 *************************************************************************/
962 #define OHCI_PRIV_REG 0x0
963 #define OHCI_PRIV_PORT1_HOST_SHIFT 0
964 #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
965 #define OHCI_PRIV_REG_SWAP_SHIFT 3
966 #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT)
969 /*************************************************************************
970 * _REG relative to RSET_USBH_PRIV
971 *************************************************************************/
973 #define USBH_PRIV_SWAP_6358_REG 0x0
974 #define USBH_PRIV_SWAP_6368_REG 0x1c
976 #define USBH_PRIV_SWAP_USBD_SHIFT 6
977 #define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT)
978 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
979 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
980 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
981 #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
982 #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
983 #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
984 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
985 #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
987 #define USBH_PRIV_UTMI_CTL_6368_REG 0x10
988 #define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12
989 #define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
990 #define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0
991 #define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
993 #define USBH_PRIV_TEST_6358_REG 0x24
994 #define USBH_PRIV_TEST_6368_REG 0x14
996 #define USBH_PRIV_SETUP_6368_REG 0x28
997 #define USBH_PRIV_SETUP_IOC_SHIFT 4
998 #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
1001 /*************************************************************************
1002 * _REG relative to RSET_USBD
1003 *************************************************************************/
1005 /* General control */
1006 #define USBD_CONTROL_REG 0x00
1007 #define USBD_CONTROL_TXZLENINS_SHIFT 14
1008 #define USBD_CONTROL_TXZLENINS_MASK (1 << USBD_CONTROL_TXZLENINS_SHIFT)
1009 #define USBD_CONTROL_AUTO_CSRS_SHIFT 13
1010 #define USBD_CONTROL_AUTO_CSRS_MASK (1 << USBD_CONTROL_AUTO_CSRS_SHIFT)
1011 #define USBD_CONTROL_RXZSCFG_SHIFT 12
1012 #define USBD_CONTROL_RXZSCFG_MASK (1 << USBD_CONTROL_RXZSCFG_SHIFT)
1013 #define USBD_CONTROL_INIT_SEL_SHIFT 8
1014 #define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
1015 #define USBD_CONTROL_FIFO_RESET_SHIFT 6
1016 #define USBD_CONTROL_FIFO_RESET_MASK (3 << USBD_CONTROL_FIFO_RESET_SHIFT)
1017 #define USBD_CONTROL_SETUPERRLOCK_SHIFT 5
1018 #define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
1019 #define USBD_CONTROL_DONE_CSRS_SHIFT 0
1020 #define USBD_CONTROL_DONE_CSRS_MASK (1 << USBD_CONTROL_DONE_CSRS_SHIFT)
1023 #define USBD_STRAPS_REG 0x04
1024 #define USBD_STRAPS_APP_SELF_PWR_SHIFT 10
1025 #define USBD_STRAPS_APP_SELF_PWR_MASK (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
1026 #define USBD_STRAPS_APP_DISCON_SHIFT 9
1027 #define USBD_STRAPS_APP_DISCON_MASK (1 << USBD_STRAPS_APP_DISCON_SHIFT)
1028 #define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8
1029 #define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
1030 #define USBD_STRAPS_APP_RMTWKUP_SHIFT 6
1031 #define USBD_STRAPS_APP_RMTWKUP_MASK (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)
1032 #define USBD_STRAPS_APP_RAM_IF_SHIFT 7
1033 #define USBD_STRAPS_APP_RAM_IF_MASK (1 << USBD_STRAPS_APP_RAM_IF_SHIFT)
1034 #define USBD_STRAPS_APP_8BITPHY_SHIFT 2
1035 #define USBD_STRAPS_APP_8BITPHY_MASK (1 << USBD_STRAPS_APP_8BITPHY_SHIFT)
1036 #define USBD_STRAPS_SPEED_SHIFT 0
1037 #define USBD_STRAPS_SPEED_MASK (3 << USBD_STRAPS_SPEED_SHIFT)
1040 #define USBD_STALL_REG 0x08
1041 #define USBD_STALL_UPDATE_SHIFT 7
1042 #define USBD_STALL_UPDATE_MASK (1 << USBD_STALL_UPDATE_SHIFT)
1043 #define USBD_STALL_ENABLE_SHIFT 6
1044 #define USBD_STALL_ENABLE_MASK (1 << USBD_STALL_ENABLE_SHIFT)
1045 #define USBD_STALL_EPNUM_SHIFT 0
1046 #define USBD_STALL_EPNUM_MASK (0xf << USBD_STALL_EPNUM_SHIFT)
1048 /* General status */
1049 #define USBD_STATUS_REG 0x0c
1050 #define USBD_STATUS_SOF_SHIFT 16
1051 #define USBD_STATUS_SOF_MASK (0x7ff << USBD_STATUS_SOF_SHIFT)
1052 #define USBD_STATUS_SPD_SHIFT 12
1053 #define USBD_STATUS_SPD_MASK (3 << USBD_STATUS_SPD_SHIFT)
1054 #define USBD_STATUS_ALTINTF_SHIFT 8
1055 #define USBD_STATUS_ALTINTF_MASK (0xf << USBD_STATUS_ALTINTF_SHIFT)
1056 #define USBD_STATUS_INTF_SHIFT 4
1057 #define USBD_STATUS_INTF_MASK (0xf << USBD_STATUS_INTF_SHIFT)
1058 #define USBD_STATUS_CFG_SHIFT 0
1059 #define USBD_STATUS_CFG_MASK (0xf << USBD_STATUS_CFG_SHIFT)
1062 #define USBD_EVENTS_REG 0x10
1063 #define USBD_EVENTS_USB_LINK_SHIFT 10
1064 #define USBD_EVENTS_USB_LINK_MASK (1 << USBD_EVENTS_USB_LINK_SHIFT)
1067 #define USBD_EVENT_IRQ_STATUS_REG 0x14
1069 /* IRQ level (2 bits per IRQ event) */
1070 #define USBD_EVENT_IRQ_CFG_HI_REG 0x18
1072 #define USBD_EVENT_IRQ_CFG_LO_REG 0x1c
1074 #define USBD_EVENT_IRQ_CFG_SHIFT(x) ((x & 0xf) << 1)
1075 #define USBD_EVENT_IRQ_CFG_MASK(x) (3 << USBD_EVENT_IRQ_CFG_SHIFT(x))
1076 #define USBD_EVENT_IRQ_CFG_RISING(x) (0 << USBD_EVENT_IRQ_CFG_SHIFT(x))
1077 #define USBD_EVENT_IRQ_CFG_FALLING(x) (1 << USBD_EVENT_IRQ_CFG_SHIFT(x))
1079 /* IRQ mask (1=unmasked) */
1080 #define USBD_EVENT_IRQ_MASK_REG 0x20
1083 #define USBD_EVENT_IRQ_USB_LINK 10
1084 #define USBD_EVENT_IRQ_SETCFG 9
1085 #define USBD_EVENT_IRQ_SETINTF 8
1086 #define USBD_EVENT_IRQ_ERRATIC_ERR 7
1087 #define USBD_EVENT_IRQ_SET_CSRS 6
1088 #define USBD_EVENT_IRQ_SUSPEND 5
1089 #define USBD_EVENT_IRQ_EARLY_SUSPEND 4
1090 #define USBD_EVENT_IRQ_SOF 3
1091 #define USBD_EVENT_IRQ_ENUM_ON 2
1092 #define USBD_EVENT_IRQ_SETUP 1
1093 #define USBD_EVENT_IRQ_USB_RESET 0
1095 /* TX FIFO partitioning */
1096 #define USBD_TXFIFO_CONFIG_REG 0x40
1097 #define USBD_TXFIFO_CONFIG_END_SHIFT 16
1098 #define USBD_TXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
1099 #define USBD_TXFIFO_CONFIG_START_SHIFT 0
1100 #define USBD_TXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
1102 /* RX FIFO partitioning */
1103 #define USBD_RXFIFO_CONFIG_REG 0x44
1104 #define USBD_RXFIFO_CONFIG_END_SHIFT 16
1105 #define USBD_RXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
1106 #define USBD_RXFIFO_CONFIG_START_SHIFT 0
1107 #define USBD_RXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
1109 /* TX FIFO/endpoint configuration */
1110 #define USBD_TXFIFO_EPSIZE_REG 0x48
1112 /* RX FIFO/endpoint configuration */
1113 #define USBD_RXFIFO_EPSIZE_REG 0x4c
1115 /* Endpoint<->DMA mappings */
1116 #define USBD_EPNUM_TYPEMAP_REG 0x50
1117 #define USBD_EPNUM_TYPEMAP_TYPE_SHIFT 8
1118 #define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
1119 #define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0
1120 #define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
1122 /* Misc per-endpoint settings */
1123 #define USBD_CSR_SETUPADDR_REG 0x80
1124 #define USBD_CSR_SETUPADDR_DEF 0xb550
1126 #define USBD_CSR_EP_REG(x) (0x84 + (x) * 4)
1127 #define USBD_CSR_EP_MAXPKT_SHIFT 19
1128 #define USBD_CSR_EP_MAXPKT_MASK (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)
1129 #define USBD_CSR_EP_ALTIFACE_SHIFT 15
1130 #define USBD_CSR_EP_ALTIFACE_MASK (0xf << USBD_CSR_EP_ALTIFACE_SHIFT)
1131 #define USBD_CSR_EP_IFACE_SHIFT 11
1132 #define USBD_CSR_EP_IFACE_MASK (0xf << USBD_CSR_EP_IFACE_SHIFT)
1133 #define USBD_CSR_EP_CFG_SHIFT 7
1134 #define USBD_CSR_EP_CFG_MASK (0xf << USBD_CSR_EP_CFG_SHIFT)
1135 #define USBD_CSR_EP_TYPE_SHIFT 5
1136 #define USBD_CSR_EP_TYPE_MASK (3 << USBD_CSR_EP_TYPE_SHIFT)
1137 #define USBD_CSR_EP_DIR_SHIFT 4
1138 #define USBD_CSR_EP_DIR_MASK (1 << USBD_CSR_EP_DIR_SHIFT)
1139 #define USBD_CSR_EP_LOG_SHIFT 0
1140 #define USBD_CSR_EP_LOG_MASK (0xf << USBD_CSR_EP_LOG_SHIFT)
1143 /*************************************************************************
1144 * _REG relative to RSET_MPI
1145 *************************************************************************/
1147 /* well known (hard wired) chip select */
1148 #define MPI_CS_PCMCIA_COMMON 4
1149 #define MPI_CS_PCMCIA_ATTR 5
1150 #define MPI_CS_PCMCIA_IO 6
1152 /* Chip select base register */
1153 #define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
1154 #define MPI_CSBASE_BASE_SHIFT 13
1155 #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
1156 #define MPI_CSBASE_SIZE_SHIFT 0
1157 #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
1159 #define MPI_CSBASE_SIZE_8K 0
1160 #define MPI_CSBASE_SIZE_16K 1
1161 #define MPI_CSBASE_SIZE_32K 2
1162 #define MPI_CSBASE_SIZE_64K 3
1163 #define MPI_CSBASE_SIZE_128K 4
1164 #define MPI_CSBASE_SIZE_256K 5
1165 #define MPI_CSBASE_SIZE_512K 6
1166 #define MPI_CSBASE_SIZE_1M 7
1167 #define MPI_CSBASE_SIZE_2M 8
1168 #define MPI_CSBASE_SIZE_4M 9
1169 #define MPI_CSBASE_SIZE_8M 10
1170 #define MPI_CSBASE_SIZE_16M 11
1171 #define MPI_CSBASE_SIZE_32M 12
1172 #define MPI_CSBASE_SIZE_64M 13
1173 #define MPI_CSBASE_SIZE_128M 14
1174 #define MPI_CSBASE_SIZE_256M 15
1176 /* Chip select control register */
1177 #define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
1178 #define MPI_CSCTL_ENABLE_MASK (1 << 0)
1179 #define MPI_CSCTL_WAIT_SHIFT 1
1180 #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
1181 #define MPI_CSCTL_DATA16_MASK (1 << 4)
1182 #define MPI_CSCTL_SYNCMODE_MASK (1 << 7)
1183 #define MPI_CSCTL_TSIZE_MASK (1 << 8)
1184 #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10)
1185 #define MPI_CSCTL_SETUP_SHIFT 16
1186 #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
1187 #define MPI_CSCTL_HOLD_SHIFT 20
1188 #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
1191 #define MPI_SP0_RANGE_REG 0x100
1192 #define MPI_SP0_REMAP_REG 0x104
1193 #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
1194 #define MPI_SP1_RANGE_REG 0x10C
1195 #define MPI_SP1_REMAP_REG 0x110
1196 #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
1198 #define MPI_L2PCFG_REG 0x11C
1199 #define MPI_L2PCFG_CFG_TYPE_SHIFT 0
1200 #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
1201 #define MPI_L2PCFG_REG_SHIFT 2
1202 #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
1203 #define MPI_L2PCFG_FUNC_SHIFT 8
1204 #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
1205 #define MPI_L2PCFG_DEVNUM_SHIFT 11
1206 #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
1207 #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
1208 #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
1210 #define MPI_L2PMEMRANGE1_REG 0x120
1211 #define MPI_L2PMEMBASE1_REG 0x124
1212 #define MPI_L2PMEMREMAP1_REG 0x128
1213 #define MPI_L2PMEMRANGE2_REG 0x12C
1214 #define MPI_L2PMEMBASE2_REG 0x130
1215 #define MPI_L2PMEMREMAP2_REG 0x134
1216 #define MPI_L2PIORANGE_REG 0x138
1217 #define MPI_L2PIOBASE_REG 0x13C
1218 #define MPI_L2PIOREMAP_REG 0x140
1219 #define MPI_L2P_BASE_MASK (0xffff8000)
1220 #define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
1221 #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
1223 #define MPI_PCIMODESEL_REG 0x144
1224 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
1225 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
1226 #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
1227 #define MPI_PCIMODESEL_PREFETCH_SHIFT 4
1228 #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
1230 #define MPI_LOCBUSCTL_REG 0x14C
1231 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
1232 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
1234 #define MPI_LOCINT_REG 0x150
1235 #define MPI_LOCINT_MASK(x) (1 << (x + 16))
1236 #define MPI_LOCINT_STAT(x) (1 << (x))
1237 #define MPI_LOCINT_DIR_FAILED 6
1238 #define MPI_LOCINT_EXT_PCI_INT 7
1239 #define MPI_LOCINT_SERR 8
1240 #define MPI_LOCINT_CSERR 9
1242 #define MPI_PCICFGCTL_REG 0x178
1243 #define MPI_PCICFGCTL_CFGADDR_SHIFT 2
1244 #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
1245 #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
1247 #define MPI_PCICFGDATA_REG 0x17C
1249 /* PCI host bridge custom register */
1250 #define BCMPCI_REG_TIMERS 0x40
1251 #define REG_TIMER_TRDY_SHIFT 0
1252 #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
1253 #define REG_TIMER_RETRY_SHIFT 8
1254 #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
1257 /*************************************************************************
1258 * _REG relative to RSET_PCMCIA
1259 *************************************************************************/
1261 #define PCMCIA_C1_REG 0x0
1262 #define PCMCIA_C1_CD1_MASK (1 << 0)
1263 #define PCMCIA_C1_CD2_MASK (1 << 1)
1264 #define PCMCIA_C1_VS1_MASK (1 << 2)
1265 #define PCMCIA_C1_VS2_MASK (1 << 3)
1266 #define PCMCIA_C1_VS1OE_MASK (1 << 6)
1267 #define PCMCIA_C1_VS2OE_MASK (1 << 7)
1268 #define PCMCIA_C1_CBIDSEL_SHIFT (8)
1269 #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
1270 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
1271 #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
1272 #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
1273 #define PCMCIA_C1_RESET_MASK (1 << 18)
1275 #define PCMCIA_C2_REG 0x8
1276 #define PCMCIA_C2_DATA16_MASK (1 << 0)
1277 #define PCMCIA_C2_BYTESWAP_MASK (1 << 1)
1278 #define PCMCIA_C2_RWCOUNT_SHIFT 2
1279 #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
1280 #define PCMCIA_C2_INACTIVE_SHIFT 8
1281 #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
1282 #define PCMCIA_C2_SETUP_SHIFT 16
1283 #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
1284 #define PCMCIA_C2_HOLD_SHIFT 24
1285 #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
1288 /*************************************************************************
1289 * _REG relative to RSET_SDRAM
1290 *************************************************************************/
1292 #define SDRAM_CFG_REG 0x0
1293 #define SDRAM_CFG_ROW_SHIFT 4
1294 #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
1295 #define SDRAM_CFG_COL_SHIFT 6
1296 #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
1297 #define SDRAM_CFG_32B_SHIFT 10
1298 #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
1299 #define SDRAM_CFG_BANK_SHIFT 13
1300 #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
1302 #define SDRAM_MBASE_REG 0xc
1304 #define SDRAM_PRIO_REG 0x2C
1305 #define SDRAM_PRIO_MIPS_SHIFT 29
1306 #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
1307 #define SDRAM_PRIO_ADSL_SHIFT 30
1308 #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT)
1309 #define SDRAM_PRIO_EN_SHIFT 31
1310 #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT)
1313 /*************************************************************************
1314 * _REG relative to RSET_MEMC
1315 *************************************************************************/
1317 #define MEMC_CFG_REG 0x4
1318 #define MEMC_CFG_32B_SHIFT 1
1319 #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
1320 #define MEMC_CFG_COL_SHIFT 3
1321 #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
1322 #define MEMC_CFG_ROW_SHIFT 6
1323 #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
1326 /*************************************************************************
1327 * _REG relative to RSET_DDR
1328 *************************************************************************/
1330 #define DDR_CSEND_REG 0x8
1332 #define DDR_DMIPSPLLCFG_REG 0x18
1333 #define DMIPSPLLCFG_M1_SHIFT 0
1334 #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
1335 #define DMIPSPLLCFG_N1_SHIFT 23
1336 #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
1337 #define DMIPSPLLCFG_N2_SHIFT 29
1338 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
1340 #define DDR_DMIPSPLLCFG_6368_REG 0x20
1341 #define DMIPSPLLCFG_6368_P1_SHIFT 0
1342 #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
1343 #define DMIPSPLLCFG_6368_P2_SHIFT 4
1344 #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
1345 #define DMIPSPLLCFG_6368_NDIV_SHIFT 16
1346 #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
1348 #define DDR_DMIPSPLLDIV_6368_REG 0x24
1349 #define DMIPSPLLDIV_6368_MDIV_SHIFT 0
1350 #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
1353 /*************************************************************************
1354 * _REG relative to RSET_M2M
1355 *************************************************************************/
1360 #define M2M_SRC_REG(x) ((x) * 0x40 + 0x00)
1361 #define M2M_DST_REG(x) ((x) * 0x40 + 0x04)
1362 #define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08)
1364 #define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c)
1365 #define M2M_CTRL_ENABLE_MASK (1 << 0)
1366 #define M2M_CTRL_IRQEN_MASK (1 << 1)
1367 #define M2M_CTRL_ERROR_CLR_MASK (1 << 6)
1368 #define M2M_CTRL_DONE_CLR_MASK (1 << 7)
1369 #define M2M_CTRL_NOINC_MASK (1 << 8)
1370 #define M2M_CTRL_PCMCIASWAP_MASK (1 << 9)
1371 #define M2M_CTRL_SWAPBYTE_MASK (1 << 10)
1372 #define M2M_CTRL_ENDIAN_MASK (1 << 11)
1374 #define M2M_STAT_REG(x) ((x) * 0x40 + 0x10)
1375 #define M2M_STAT_DONE (1 << 0)
1376 #define M2M_STAT_ERROR (1 << 1)
1378 #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
1379 #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
1381 /*************************************************************************
1382 * _REG relative to RSET_RNG
1383 *************************************************************************/
1385 #define RNG_CTRL 0x00
1386 #define RNG_EN (1 << 0)
1388 #define RNG_STAT 0x04
1389 #define RNG_AVAIL_MASK (0xff000000)
1391 #define RNG_DATA 0x08
1392 #define RNG_THRES 0x0c
1393 #define RNG_MASK 0x10
1395 /*************************************************************************
1396 * _REG relative to RSET_SPI
1397 *************************************************************************/
1399 /* BCM 6338/6348 SPI core */
1400 #define SPI_6348_CMD 0x00 /* 16-bits register */
1401 #define SPI_6348_INT_STATUS 0x02
1402 #define SPI_6348_INT_MASK_ST 0x03
1403 #define SPI_6348_INT_MASK 0x04
1404 #define SPI_6348_ST 0x05
1405 #define SPI_6348_CLK_CFG 0x06
1406 #define SPI_6348_FILL_BYTE 0x07
1407 #define SPI_6348_MSG_TAIL 0x09
1408 #define SPI_6348_RX_TAIL 0x0b
1409 #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
1410 #define SPI_6348_MSG_CTL_WIDTH 8
1411 #define SPI_6348_MSG_DATA 0x41
1412 #define SPI_6348_MSG_DATA_SIZE 0x3f
1413 #define SPI_6348_RX_DATA 0x80
1414 #define SPI_6348_RX_DATA_SIZE 0x3f
1416 /* BCM 3368/6358/6262/6368 SPI core */
1417 #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
1418 #define SPI_6358_MSG_CTL_WIDTH 16
1419 #define SPI_6358_MSG_DATA 0x02
1420 #define SPI_6358_MSG_DATA_SIZE 0x21e
1421 #define SPI_6358_RX_DATA 0x400
1422 #define SPI_6358_RX_DATA_SIZE 0x220
1423 #define SPI_6358_CMD 0x700 /* 16-bits register */
1424 #define SPI_6358_INT_STATUS 0x702
1425 #define SPI_6358_INT_MASK_ST 0x703
1426 #define SPI_6358_INT_MASK 0x704
1427 #define SPI_6358_ST 0x705
1428 #define SPI_6358_CLK_CFG 0x706
1429 #define SPI_6358_FILL_BYTE 0x707
1430 #define SPI_6358_MSG_TAIL 0x709
1431 #define SPI_6358_RX_TAIL 0x70B
1433 /* Shared SPI definitions */
1435 /* Message configuration */
1436 #define SPI_FD_RW 0x00
1437 #define SPI_HD_W 0x01
1438 #define SPI_HD_R 0x02
1439 #define SPI_BYTE_CNT_SHIFT 0
1440 #define SPI_6348_MSG_TYPE_SHIFT 6
1441 #define SPI_6358_MSG_TYPE_SHIFT 14
1444 #define SPI_CMD_NOOP 0x00
1445 #define SPI_CMD_SOFT_RESET 0x01
1446 #define SPI_CMD_HARD_RESET 0x02
1447 #define SPI_CMD_START_IMMEDIATE 0x03
1448 #define SPI_CMD_COMMAND_SHIFT 0
1449 #define SPI_CMD_COMMAND_MASK 0x000f
1450 #define SPI_CMD_DEVICE_ID_SHIFT 4
1451 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
1452 #define SPI_CMD_ONE_BYTE_SHIFT 11
1453 #define SPI_CMD_ONE_WIRE_SHIFT 12
1454 #define SPI_DEV_ID_0 0
1455 #define SPI_DEV_ID_1 1
1456 #define SPI_DEV_ID_2 2
1457 #define SPI_DEV_ID_3 3
1459 /* Interrupt mask */
1460 #define SPI_INTR_CMD_DONE 0x01
1461 #define SPI_INTR_RX_OVERFLOW 0x02
1462 #define SPI_INTR_TX_UNDERFLOW 0x04
1463 #define SPI_INTR_TX_OVERFLOW 0x08
1464 #define SPI_INTR_RX_UNDERFLOW 0x10
1465 #define SPI_INTR_CLEAR_ALL 0x1f
1468 #define SPI_RX_EMPTY 0x02
1469 #define SPI_CMD_BUSY 0x04
1470 #define SPI_SERIAL_BUSY 0x08
1472 /* Clock configuration */
1473 #define SPI_CLK_20MHZ 0x00
1474 #define SPI_CLK_0_391MHZ 0x01
1475 #define SPI_CLK_0_781MHZ 0x02 /* default */
1476 #define SPI_CLK_1_563MHZ 0x03
1477 #define SPI_CLK_3_125MHZ 0x04
1478 #define SPI_CLK_6_250MHZ 0x05
1479 #define SPI_CLK_12_50MHZ 0x06
1480 #define SPI_CLK_MASK 0x07
1481 #define SPI_SSOFFTIME_MASK 0x38
1482 #define SPI_SSOFFTIME_SHIFT 3
1483 #define SPI_BYTE_SWAP 0x80
1485 /*************************************************************************
1486 * _REG relative to RSET_MISC
1487 *************************************************************************/
1488 #define MISC_SERDES_CTRL_6328_REG 0x0
1489 #define MISC_SERDES_CTRL_6362_REG 0x4
1490 #define SERDES_PCIE_EN (1 << 0)
1491 #define SERDES_PCIE_EXD_EN (1 << 15)
1493 #define MISC_STRAPBUS_6362_REG 0x14
1494 #define STRAPBUS_6362_FCVO_SHIFT 1
1495 #define STRAPBUS_6362_HSSPI_CLK_FAST (1 << 13)
1496 #define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT)
1497 #define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15)
1498 #define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
1500 #define MISC_STRAPBUS_6328_REG 0x240
1501 #define STRAPBUS_6328_FCVO_SHIFT 7
1502 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
1503 #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
1504 #define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
1506 /*************************************************************************
1507 * _REG relative to RSET_PCIE
1508 *************************************************************************/
1510 #define PCIE_CONFIG2_REG 0x408
1511 #define CONFIG2_BAR1_SIZE_EN 1
1512 #define CONFIG2_BAR1_SIZE_MASK 0xf
1514 #define PCIE_IDVAL3_REG 0x43c
1515 #define IDVAL3_CLASS_CODE_MASK 0xffffff
1516 #define IDVAL3_SUBCLASS_SHIFT 8
1517 #define IDVAL3_CLASS_SHIFT 16
1519 #define PCIE_DLSTATUS_REG 0x1048
1520 #define DLSTATUS_PHYLINKUP (1 << 13)
1522 #define PCIE_BRIDGE_OPT1_REG 0x2820
1523 #define OPT1_RD_BE_OPT_EN (1 << 7)
1524 #define OPT1_RD_REPLY_BE_FIX_EN (1 << 9)
1525 #define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11)
1526 #define OPT1_L1_INT_STATUS_MASK_POL (1 << 12)
1528 #define PCIE_BRIDGE_OPT2_REG 0x2824
1529 #define OPT2_UBUS_UR_DECODE_DIS (1 << 2)
1530 #define OPT2_TX_CREDIT_CHK_EN (1 << 4)
1531 #define OPT2_CFG_TYPE1_BD_SEL (1 << 7)
1532 #define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16
1533 #define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
1535 #define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
1536 #define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830
1537 #define BASEMASK_REMAP_EN (1 << 0)
1538 #define BASEMASK_SWAP_EN (1 << 1)
1539 #define BASEMASK_MASK_SHIFT 4
1540 #define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
1541 #define BASEMASK_BASE_SHIFT 20
1542 #define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
1544 #define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
1545 #define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
1546 #define REBASE_ADDR_BASE_SHIFT 20
1547 #define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
1549 #define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
1550 #define PCIE_RC_INT_A (1 << 0)
1551 #define PCIE_RC_INT_B (1 << 1)
1552 #define PCIE_RC_INT_C (1 << 2)
1553 #define PCIE_RC_INT_D (1 << 3)
1555 #define PCIE_DEVICE_OFFSET 0x8000
1557 /*************************************************************************
1558 * _REG relative to RSET_OTP
1559 *************************************************************************/
1561 #define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4)
1562 #define OTP_6328_REG3_TP1_DISABLED BIT(9)
1564 #endif /* BCM63XX_REGS_H_ */
projects / firefly-linux-kernel-4.4.55.git / blob