2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 * Copyright (C) 2004 Maciej W. Rozycki
12 #ifndef __ASM_CPU_INFO_H
13 #define __ASM_CPU_INFO_H
15 #include <linux/types.h>
17 #include <asm/cache.h>
20 * Descriptor for a cache
23 unsigned int waysize; /* Bytes per way */
24 unsigned short sets; /* Number of lines per set */
25 unsigned char ways; /* Number of ways */
26 unsigned char linesz; /* Size of line in bytes */
27 unsigned char waybit; /* Bits to select in a cache set */
28 unsigned char flags; /* Flags describing cache properties */
34 #define MIPS_CACHE_NOT_PRESENT 0x00000001
35 #define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
36 #define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
37 #define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
38 #define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
39 #define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
42 unsigned int udelay_val;
43 unsigned int asid_cache;
46 * Capability and feature descriptor structure for MIPS CPU
48 unsigned long options;
50 unsigned int processor_id;
59 struct cache_desc icache; /* Primary I-cache */
60 struct cache_desc dcache; /* Primary D or combined I/D cache */
61 struct cache_desc scache; /* Secondary cache */
62 struct cache_desc tcache; /* Tertiary/split secondary cache */
63 int srsets; /* Shadow register sets */
64 int core; /* physical core number */
66 int vmbits; /* Virtual memory size in bits */
68 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
70 * In the MIPS MT "SMTC" model, each TC is considered
71 * to be a "CPU" for the purposes of scheduling, but
72 * exception resources, ASID spaces, etc, are common
73 * to all TCs within the same VPE.
75 int vpe_id; /* Virtual Processor number */
77 #ifdef CONFIG_MIPS_MT_SMTC
78 int tc_id; /* Thread Context number */
80 void *data; /* Additional data */
81 unsigned int watch_reg_count; /* Number that exist */
82 unsigned int watch_reg_use_cnt; /* Usable by ptrace */
83 #define NUM_WATCH_REGS 4
84 u16 watch_reg_masks[NUM_WATCH_REGS];
85 unsigned int kscratch_mask; /* Usable KScratch mask. */
86 } __attribute__((aligned(SMP_CACHE_BYTES)));
88 extern struct cpuinfo_mips cpu_data[];
89 #define current_cpu_data cpu_data[smp_processor_id()]
90 #define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
91 #define boot_cpu_data cpu_data[0]
93 extern void cpu_probe(void);
94 extern void cpu_report(void);
96 extern const char *__cpu_name[];
97 #define cpu_name_string() __cpu_name[smp_processor_id()]
100 struct notifier_block;
102 extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
103 extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
105 #define proc_cpuinfo_notifier(fn, pri) \
107 static struct notifier_block fn##_nb = { \
108 .notifier_call = fn, \
112 register_proc_cpuinfo_notifier(&fn##_nb); \
115 struct proc_cpuinfo_notifier_args {
120 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
121 # define cpu_vpe_id(cpuinfo) ((cpuinfo)->vpe_id)
123 # define cpu_vpe_id(cpuinfo) 0
126 #endif /* __ASM_CPU_INFO_H */