2 * Atheros AR71XX/AR724X/AR913X GPIO API support
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/spinlock.h>
21 #include <linux/ioport.h>
22 #include <linux/gpio.h>
23 #include <linux/platform_data/gpio-ath79.h>
24 #include <linux/of_device.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/ath79.h>
30 static void __iomem *ath79_gpio_base;
31 static u32 ath79_gpio_count;
32 static DEFINE_SPINLOCK(ath79_gpio_lock);
34 static void __ath79_gpio_set_value(unsigned gpio, int value)
36 void __iomem *base = ath79_gpio_base;
39 __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET);
41 __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR);
44 static int __ath79_gpio_get_value(unsigned gpio)
46 return (__raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_IN) >> gpio) & 1;
49 static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned offset)
51 return __ath79_gpio_get_value(offset);
54 static void ath79_gpio_set_value(struct gpio_chip *chip,
55 unsigned offset, int value)
57 __ath79_gpio_set_value(offset, value);
60 static int ath79_gpio_direction_input(struct gpio_chip *chip,
63 void __iomem *base = ath79_gpio_base;
66 spin_lock_irqsave(&ath79_gpio_lock, flags);
68 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
69 base + AR71XX_GPIO_REG_OE);
71 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
76 static int ath79_gpio_direction_output(struct gpio_chip *chip,
77 unsigned offset, int value)
79 void __iomem *base = ath79_gpio_base;
82 spin_lock_irqsave(&ath79_gpio_lock, flags);
85 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
87 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
89 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
90 base + AR71XX_GPIO_REG_OE);
92 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
97 static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
99 void __iomem *base = ath79_gpio_base;
102 spin_lock_irqsave(&ath79_gpio_lock, flags);
104 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
105 base + AR71XX_GPIO_REG_OE);
107 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
112 static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
115 void __iomem *base = ath79_gpio_base;
118 spin_lock_irqsave(&ath79_gpio_lock, flags);
121 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
123 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
125 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
126 base + AR71XX_GPIO_REG_OE);
128 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
133 static struct gpio_chip ath79_gpio_chip = {
135 .get = ath79_gpio_get_value,
136 .set = ath79_gpio_set_value,
137 .direction_input = ath79_gpio_direction_input,
138 .direction_output = ath79_gpio_direction_output,
142 static void __iomem *ath79_gpio_get_function_reg(void)
146 if (soc_is_ar71xx() ||
150 reg = AR71XX_GPIO_REG_FUNC;
151 else if (soc_is_ar934x())
152 reg = AR934X_GPIO_REG_FUNC;
156 return ath79_gpio_base + reg;
159 void ath79_gpio_function_setup(u32 set, u32 clear)
161 void __iomem *reg = ath79_gpio_get_function_reg();
164 spin_lock_irqsave(&ath79_gpio_lock, flags);
166 __raw_writel((__raw_readl(reg) & ~clear) | set, reg);
170 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
173 void ath79_gpio_function_enable(u32 mask)
175 ath79_gpio_function_setup(mask, 0);
178 void ath79_gpio_function_disable(u32 mask)
180 ath79_gpio_function_setup(0, mask);
183 static const struct of_device_id ath79_gpio_of_match[] = {
184 { .compatible = "qca,ar7100-gpio" },
185 { .compatible = "qca,ar9340-gpio" },
189 static int ath79_gpio_probe(struct platform_device *pdev)
191 struct ath79_gpio_platform_data *pdata = pdev->dev.platform_data;
192 struct device_node *np = pdev->dev.of_node;
193 struct resource *res;
198 err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
200 dev_err(&pdev->dev, "ngpios property is not valid\n");
203 if (ath79_gpio_count >= 32) {
204 dev_err(&pdev->dev, "ngpios must be less than 32\n");
207 oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
209 ath79_gpio_count = pdata->ngpios;
210 oe_inverted = pdata->oe_inverted;
212 dev_err(&pdev->dev, "No DT node or platform data found\n");
216 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
217 ath79_gpio_base = devm_ioremap_nocache(
218 &pdev->dev, res->start, resource_size(res));
219 if (!ath79_gpio_base)
222 ath79_gpio_chip.dev = &pdev->dev;
223 ath79_gpio_chip.ngpio = ath79_gpio_count;
225 ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
226 ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
229 err = gpiochip_add(&ath79_gpio_chip);
232 "cannot add AR71xx GPIO chip, error=%d", err);
239 static struct platform_driver ath79_gpio_driver = {
241 .name = "ath79-gpio",
242 .of_match_table = ath79_gpio_of_match,
244 .probe = ath79_gpio_probe,
247 module_platform_driver(ath79_gpio_driver);
249 int gpio_get_value(unsigned gpio)
251 if (gpio < ath79_gpio_count)
252 return __ath79_gpio_get_value(gpio);
254 return __gpio_get_value(gpio);
256 EXPORT_SYMBOL(gpio_get_value);
258 void gpio_set_value(unsigned gpio, int value)
260 if (gpio < ath79_gpio_count)
261 __ath79_gpio_set_value(gpio, value);
263 __gpio_set_value(gpio, value);
265 EXPORT_SYMBOL(gpio_set_value);
267 int gpio_to_irq(unsigned gpio)
272 EXPORT_SYMBOL(gpio_to_irq);
274 int irq_to_gpio(unsigned irq)
279 EXPORT_SYMBOL(irq_to_gpio);