2 * Atheros AR71XX/AR724X/AR913X GPIO API support
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/spinlock.h>
21 #include <linux/ioport.h>
22 #include <linux/gpio.h>
24 #include <asm/mach-ath79/ar71xx_regs.h>
25 #include <asm/mach-ath79/ath79.h>
28 static void __iomem *ath79_gpio_base;
29 static unsigned long ath79_gpio_count;
30 static DEFINE_SPINLOCK(ath79_gpio_lock);
32 static void __ath79_gpio_set_value(unsigned gpio, int value)
34 void __iomem *base = ath79_gpio_base;
37 __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET);
39 __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR);
42 static int __ath79_gpio_get_value(unsigned gpio)
44 return (__raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_IN) >> gpio) & 1;
47 static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned offset)
49 return __ath79_gpio_get_value(offset);
52 static void ath79_gpio_set_value(struct gpio_chip *chip,
53 unsigned offset, int value)
55 __ath79_gpio_set_value(offset, value);
58 static int ath79_gpio_direction_input(struct gpio_chip *chip,
61 void __iomem *base = ath79_gpio_base;
64 spin_lock_irqsave(&ath79_gpio_lock, flags);
66 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
67 base + AR71XX_GPIO_REG_OE);
69 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
74 static int ath79_gpio_direction_output(struct gpio_chip *chip,
75 unsigned offset, int value)
77 void __iomem *base = ath79_gpio_base;
80 spin_lock_irqsave(&ath79_gpio_lock, flags);
83 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
85 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
87 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
88 base + AR71XX_GPIO_REG_OE);
90 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
95 static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
97 void __iomem *base = ath79_gpio_base;
100 spin_lock_irqsave(&ath79_gpio_lock, flags);
102 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
103 base + AR71XX_GPIO_REG_OE);
105 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
110 static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
113 void __iomem *base = ath79_gpio_base;
116 spin_lock_irqsave(&ath79_gpio_lock, flags);
119 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
121 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
123 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
124 base + AR71XX_GPIO_REG_OE);
126 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
131 static struct gpio_chip ath79_gpio_chip = {
133 .get = ath79_gpio_get_value,
134 .set = ath79_gpio_set_value,
135 .direction_input = ath79_gpio_direction_input,
136 .direction_output = ath79_gpio_direction_output,
140 void ath79_gpio_function_enable(u32 mask)
142 void __iomem *base = ath79_gpio_base;
145 spin_lock_irqsave(&ath79_gpio_lock, flags);
147 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask,
148 base + AR71XX_GPIO_REG_FUNC);
150 __raw_readl(base + AR71XX_GPIO_REG_FUNC);
152 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
155 void ath79_gpio_function_disable(u32 mask)
157 void __iomem *base = ath79_gpio_base;
160 spin_lock_irqsave(&ath79_gpio_lock, flags);
162 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask,
163 base + AR71XX_GPIO_REG_FUNC);
165 __raw_readl(base + AR71XX_GPIO_REG_FUNC);
167 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
170 void ath79_gpio_function_setup(u32 set, u32 clear)
172 void __iomem *base = ath79_gpio_base;
175 spin_lock_irqsave(&ath79_gpio_lock, flags);
177 __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set,
178 base + AR71XX_GPIO_REG_FUNC);
180 __raw_readl(base + AR71XX_GPIO_REG_FUNC);
182 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
185 void __init ath79_gpio_init(void)
190 ath79_gpio_count = AR71XX_GPIO_COUNT;
191 else if (soc_is_ar724x())
192 ath79_gpio_count = AR724X_GPIO_COUNT;
193 else if (soc_is_ar913x())
194 ath79_gpio_count = AR913X_GPIO_COUNT;
195 else if (soc_is_ar933x())
196 ath79_gpio_count = AR933X_GPIO_COUNT;
197 else if (soc_is_ar934x())
198 ath79_gpio_count = AR934X_GPIO_COUNT;
202 ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
203 ath79_gpio_chip.ngpio = ath79_gpio_count;
204 if (soc_is_ar934x()) {
205 ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
206 ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
209 err = gpiochip_add(&ath79_gpio_chip);
211 panic("cannot add AR71xx GPIO chip, error=%d", err);
214 int gpio_get_value(unsigned gpio)
216 if (gpio < ath79_gpio_count)
217 return __ath79_gpio_get_value(gpio);
219 return __gpio_get_value(gpio);
221 EXPORT_SYMBOL(gpio_get_value);
223 void gpio_set_value(unsigned gpio, int value)
225 if (gpio < ath79_gpio_count)
226 __ath79_gpio_set_value(gpio, value);
228 __gpio_set_value(gpio, value);
230 EXPORT_SYMBOL(gpio_set_value);
232 int gpio_to_irq(unsigned gpio)
237 EXPORT_SYMBOL(gpio_to_irq);
239 int irq_to_gpio(unsigned irq)
244 EXPORT_SYMBOL(irq_to_gpio);