arch/mips/alchemy/devboards/db1550.c

   1 /*
   2  * Alchemy Db1550 board support
   3  *
   4  * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
   5  */
   6
   7 #include <linux/dma-mapping.h>
   8 #include <linux/gpio.h>
   9 #include <linux/i2c.h>
  10 #include <linux/init.h>
  11 #include <linux/io.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/mtd/mtd.h>
  14 #include <linux/mtd/nand.h>
  15 #include <linux/mtd/partitions.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm.h>
  18 #include <linux/spi/spi.h>
  19 #include <linux/spi/flash.h>
  20 #include <asm/mach-au1x00/au1000.h>
  21 #include <asm/mach-au1x00/au1xxx_eth.h>
  22 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  23 #include <asm/mach-au1x00/au1xxx_psc.h>
  24 #include <asm/mach-au1x00/au1550_spi.h>
  25 #include <asm/mach-db1x00/bcsr.h>
  26 #include <prom.h>
  27 #include "platform.h"
  28
  29
  30 const char *get_system_type(void)
  31 {
  32         return "DB1550";
  33 }
  34
  35 static void __init db1550_hw_setup(void)
  36 {
  37         void __iomem *base;
  38
  39         alchemy_gpio_direction_output(203, 0);  /* red led on */
  40
  41         /* complete SPI setup: link psc0_intclk to a 48MHz source,
  42          * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line)
  43          */
  44         base = (void __iomem *)SYS_CLKSRC;
  45         __raw_writel(__raw_readl(base) | 0x000001e0, base);
  46         base = (void __iomem *)SYS_PINFUNC;
  47         __raw_writel(__raw_readl(base) | 1, base);
  48         wmb();
  49
  50         /* reset the AC97 codec now, the reset time in the psc-ac97 driver
  51          * is apparently too short although it's ridiculous as it is.
  52          */
  53         base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR);
  54         __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE,
  55                      base + PSC_SEL_OFFSET);
  56         __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET);
  57         wmb();
  58         __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET);
  59         wmb();
  60
  61         alchemy_gpio_direction_output(202, 0);  /* green led on */
  62 }
  63
  64 void __init board_setup(void)
  65 {
  66         unsigned short whoami;
  67
  68         bcsr_init(DB1550_BCSR_PHYS_ADDR,
  69                   DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
  70
  71         whoami = bcsr_read(BCSR_WHOAMI);
  72         printk(KERN_INFO "Alchemy/AMD DB1550 Board, CPLD Rev %d"
  73                 "  Board-ID %d  Daughtercard ID %d\n",
  74                 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
  75
  76         db1550_hw_setup();
  77 }
  78
  79 /*****************************************************************************/
  80
  81 static struct mtd_partition db1550_spiflash_parts[] = {
  82         {
  83                 .name   = "spi_flash",
  84                 .offset = 0,
  85                 .size   = MTDPART_SIZ_FULL,
  86         },
  87 };
  88
  89 static struct flash_platform_data db1550_spiflash_data = {
  90         .name           = "s25fl010",
  91         .parts          = db1550_spiflash_parts,
  92         .nr_parts       = ARRAY_SIZE(db1550_spiflash_parts),
  93         .type           = "m25p10",
  94 };
  95
  96 static struct spi_board_info db1550_spi_devs[] __initdata = {
  97         {
  98                 /* TI TMP121AIDBVR temp sensor */
  99                 .modalias       = "tmp121",
 100                 .max_speed_hz   = 2400000,
 101                 .bus_num        = 0,
 102                 .chip_select    = 0,
 103                 .mode           = SPI_MODE_0,
 104         },
 105         {
 106                 /* Spansion S25FL001D0FMA SPI flash */
 107                 .modalias       = "m25p80",
 108                 .max_speed_hz   = 2400000,
 109                 .bus_num        = 0,
 110                 .chip_select    = 1,
 111                 .mode           = SPI_MODE_0,
 112                 .platform_data  = &db1550_spiflash_data,
 113         },
 114 };
 115
 116 static struct i2c_board_info db1550_i2c_devs[] __initdata = {
 117         { I2C_BOARD_INFO("24c04",  0x52),}, /* AT24C04-10 I2C eeprom */
 118         { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */
 119         { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */
 120 };
 121
 122 /**********************************************************************/
 123
 124 static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 125                                  unsigned int ctrl)
 126 {
 127         struct nand_chip *this = mtd->priv;
 128         unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
 129
 130         ioaddr &= 0xffffff00;
 131
 132         if (ctrl & NAND_CLE) {
 133                 ioaddr += MEM_STNAND_CMD;
 134         } else if (ctrl & NAND_ALE) {
 135                 ioaddr += MEM_STNAND_ADDR;
 136         } else {
 137                 /* assume we want to r/w real data  by default */
 138                 ioaddr += MEM_STNAND_DATA;
 139         }
 140         this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
 141         if (cmd != NAND_CMD_NONE) {
 142                 __raw_writeb(cmd, this->IO_ADDR_W);
 143                 wmb();
 144         }
 145 }
 146
 147 static int au1550_nand_device_ready(struct mtd_info *mtd)
 148 {
 149         return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
 150 }
 151
 152 static const char *db1550_part_probes[] = { "cmdlinepart", NULL };
 153
 154 static struct mtd_partition db1550_nand_parts[] = {
 155         {
 156                 .name   = "NAND FS 0",
 157                 .offset = 0,
 158                 .size   = 8 * 1024 * 1024,
 159         },
 160         {
 161                 .name   = "NAND FS 1",
 162                 .offset = MTDPART_OFS_APPEND,
 163                 .size   = MTDPART_SIZ_FULL
 164         },
 165 };
 166
 167 struct platform_nand_data db1550_nand_platdata = {
 168         .chip = {
 169                 .nr_chips       = 1,
 170                 .chip_offset    = 0,
 171                 .nr_partitions  = ARRAY_SIZE(db1550_nand_parts),
 172                 .partitions     = db1550_nand_parts,
 173                 .chip_delay     = 20,
 174                 .part_probe_types = db1550_part_probes,
 175         },
 176         .ctrl = {
 177                 .dev_ready      = au1550_nand_device_ready,
 178                 .cmd_ctrl       = au1550_nand_cmd_ctrl,
 179         },
 180 };
 181
 182 static struct resource db1550_nand_res[] = {
 183         [0] = {
 184                 .start  = 0x20000000,
 185                 .end    = 0x200000ff,
 186                 .flags  = IORESOURCE_MEM,
 187         },
 188 };
 189
 190 static struct platform_device db1550_nand_dev = {
 191         .name           = "gen_nand",
 192         .num_resources  = ARRAY_SIZE(db1550_nand_res),
 193         .resource       = db1550_nand_res,
 194         .id             = -1,
 195         .dev            = {
 196                 .platform_data = &db1550_nand_platdata,
 197         }
 198 };
 199
 200 /**********************************************************************/
 201
 202 static struct resource au1550_psc0_res[] = {
 203         [0] = {
 204                 .start  = AU1550_PSC0_PHYS_ADDR,
 205                 .end    = AU1550_PSC0_PHYS_ADDR + 0xfff,
 206                 .flags  = IORESOURCE_MEM,
 207         },
 208         [1] = {
 209                 .start  = AU1550_PSC0_INT,
 210                 .end    = AU1550_PSC0_INT,
 211                 .flags  = IORESOURCE_IRQ,
 212         },
 213         [2] = {
 214                 .start  = AU1550_DSCR_CMD0_PSC0_TX,
 215                 .end    = AU1550_DSCR_CMD0_PSC0_TX,
 216                 .flags  = IORESOURCE_DMA,
 217         },
 218         [3] = {
 219                 .start  = AU1550_DSCR_CMD0_PSC0_RX,
 220                 .end    = AU1550_DSCR_CMD0_PSC0_RX,
 221                 .flags  = IORESOURCE_DMA,
 222         },
 223 };
 224
 225 static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
 226 {
 227         if (cs)
 228                 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL);
 229         else
 230                 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0);
 231 }
 232
 233 static struct au1550_spi_info db1550_spi_platdata = {
 234         .mainclk_hz     = 48000000,     /* PSC0 clock: max. 2.4MHz SPI clk */
 235         .num_chipselect = 2,
 236         .activate_cs    = db1550_spi_cs_en,
 237 };
 238
 239 static u64 spi_dmamask = DMA_BIT_MASK(32);
 240
 241 static struct platform_device db1550_spi_dev = {
 242         .dev    = {
 243                 .dma_mask               = &spi_dmamask,
 244                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 245                 .platform_data          = &db1550_spi_platdata,
 246         },
 247         .name           = "au1550-spi",
 248         .id             = 0,    /* bus number */
 249         .num_resources  = ARRAY_SIZE(au1550_psc0_res),
 250         .resource       = au1550_psc0_res,
 251 };
 252
 253 /**********************************************************************/
 254
 255 static struct resource au1550_psc1_res[] = {
 256         [0] = {
 257                 .start  = AU1550_PSC1_PHYS_ADDR,
 258                 .end    = AU1550_PSC1_PHYS_ADDR + 0xfff,
 259                 .flags  = IORESOURCE_MEM,
 260         },
 261         [1] = {
 262                 .start  = AU1550_PSC1_INT,
 263                 .end    = AU1550_PSC1_INT,
 264                 .flags  = IORESOURCE_IRQ,
 265         },
 266         [2] = {
 267                 .start  = AU1550_DSCR_CMD0_PSC1_TX,
 268                 .end    = AU1550_DSCR_CMD0_PSC1_TX,
 269                 .flags  = IORESOURCE_DMA,
 270         },
 271         [3] = {
 272                 .start  = AU1550_DSCR_CMD0_PSC1_RX,
 273                 .end    = AU1550_DSCR_CMD0_PSC1_RX,
 274                 .flags  = IORESOURCE_DMA,
 275         },
 276 };
 277
 278 static struct platform_device db1550_ac97_dev = {
 279         .name           = "au1xpsc_ac97",
 280         .id             = 1,    /* PSC ID */
 281         .num_resources  = ARRAY_SIZE(au1550_psc1_res),
 282         .resource       = au1550_psc1_res,
 283 };
 284
 285
 286 static struct resource au1550_psc2_res[] = {
 287         [0] = {
 288                 .start  = AU1550_PSC2_PHYS_ADDR,
 289                 .end    = AU1550_PSC2_PHYS_ADDR + 0xfff,
 290                 .flags  = IORESOURCE_MEM,
 291         },
 292         [1] = {
 293                 .start  = AU1550_PSC2_INT,
 294                 .end    = AU1550_PSC2_INT,
 295                 .flags  = IORESOURCE_IRQ,
 296         },
 297         [2] = {
 298                 .start  = AU1550_DSCR_CMD0_PSC2_TX,
 299                 .end    = AU1550_DSCR_CMD0_PSC2_TX,
 300                 .flags  = IORESOURCE_DMA,
 301         },
 302         [3] = {
 303                 .start  = AU1550_DSCR_CMD0_PSC2_RX,
 304                 .end    = AU1550_DSCR_CMD0_PSC2_RX,
 305                 .flags  = IORESOURCE_DMA,
 306         },
 307 };
 308
 309 static struct platform_device db1550_i2c_dev = {
 310         .name           = "au1xpsc_smbus",
 311         .id             = 0,    /* bus number */
 312         .num_resources  = ARRAY_SIZE(au1550_psc2_res),
 313         .resource       = au1550_psc2_res,
 314 };
 315
 316 /**********************************************************************/
 317
 318 static struct resource au1550_psc3_res[] = {
 319         [0] = {
 320                 .start  = AU1550_PSC3_PHYS_ADDR,
 321                 .end    = AU1550_PSC3_PHYS_ADDR + 0xfff,
 322                 .flags  = IORESOURCE_MEM,
 323         },
 324         [1] = {
 325                 .start  = AU1550_PSC3_INT,
 326                 .end    = AU1550_PSC3_INT,
 327                 .flags  = IORESOURCE_IRQ,
 328         },
 329         [2] = {
 330                 .start  = AU1550_DSCR_CMD0_PSC3_TX,
 331                 .end    = AU1550_DSCR_CMD0_PSC3_TX,
 332                 .flags  = IORESOURCE_DMA,
 333         },
 334         [3] = {
 335                 .start  = AU1550_DSCR_CMD0_PSC3_RX,
 336                 .end    = AU1550_DSCR_CMD0_PSC3_RX,
 337                 .flags  = IORESOURCE_DMA,
 338         },
 339 };
 340
 341 static struct platform_device db1550_i2s_dev = {
 342         .name           = "au1xpsc_i2s",
 343         .id             = 3,    /* PSC ID */
 344         .num_resources  = ARRAY_SIZE(au1550_psc3_res),
 345         .resource       = au1550_psc3_res,
 346 };
 347
 348 /**********************************************************************/
 349
 350 static struct platform_device db1550_stac_dev = {
 351         .name           = "ac97-codec",
 352         .id             = 1,    /* on PSC1 */
 353 };
 354
 355 static struct platform_device db1550_ac97dma_dev = {
 356         .name           = "au1xpsc-pcm",
 357         .id             = 1,    /* on PSC3 */
 358 };
 359
 360 static struct platform_device db1550_i2sdma_dev = {
 361         .name           = "au1xpsc-pcm",
 362         .id             = 3,    /* on PSC3 */
 363 };
 364
 365 static struct platform_device db1550_sndac97_dev = {
 366         .name           = "db1550-ac97",
 367 };
 368
 369 static struct platform_device db1550_sndi2s_dev = {
 370         .name           = "db1550-i2s",
 371 };
 372
 373 /**********************************************************************/
 374
 375 static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
 376 {
 377         if ((slot < 11) || (slot > 13) || pin == 0)
 378                 return -1;
 379         if (slot == 11)
 380                 return (pin == 1) ? AU1550_PCI_INTC : 0xff;
 381         if (slot == 12) {
 382                 switch (pin) {
 383                 case 1: return AU1550_PCI_INTB;
 384                 case 2: return AU1550_PCI_INTC;
 385                 case 3: return AU1550_PCI_INTD;
 386                 case 4: return AU1550_PCI_INTA;
 387                 }
 388         }
 389         if (slot == 13) {
 390                 switch (pin) {
 391                 case 1: return AU1550_PCI_INTA;
 392                 case 2: return AU1550_PCI_INTB;
 393                 case 3: return AU1550_PCI_INTC;
 394                 case 4: return AU1550_PCI_INTD;
 395                 }
 396         }
 397         return -1;
 398 }
 399
 400 static struct resource alchemy_pci_host_res[] = {
 401         [0] = {
 402                 .start  = AU1500_PCI_PHYS_ADDR,
 403                 .end    = AU1500_PCI_PHYS_ADDR + 0xfff,
 404                 .flags  = IORESOURCE_MEM,
 405         },
 406 };
 407
 408 static struct alchemy_pci_platdata db1550_pci_pd = {
 409         .board_map_irq  = db1550_map_pci_irq,
 410 };
 411
 412 static struct platform_device db1550_pci_host_dev = {
 413         .dev.platform_data = &db1550_pci_pd,
 414         .name           = "alchemy-pci",
 415         .id             = 0,
 416         .num_resources  = ARRAY_SIZE(alchemy_pci_host_res),
 417         .resource       = alchemy_pci_host_res,
 418 };
 419
 420 /**********************************************************************/
 421
 422 static struct platform_device *db1550_devs[] __initdata = {
 423         &db1550_nand_dev,
 424         &db1550_i2c_dev,
 425         &db1550_ac97_dev,
 426         &db1550_spi_dev,
 427         &db1550_i2s_dev,
 428         &db1550_stac_dev,
 429         &db1550_ac97dma_dev,
 430         &db1550_i2sdma_dev,
 431         &db1550_sndac97_dev,
 432         &db1550_sndi2s_dev,
 433 };
 434
 435 /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
 436 static int __init db1550_pci_init(void)
 437 {
 438         return platform_device_register(&db1550_pci_host_dev);
 439 }
 440 arch_initcall(db1550_pci_init);
 441
 442 static int __init db1550_dev_init(void)
 443 {
 444         int swapped;
 445
 446         irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH);  /* CD0# */
 447         irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH);  /* CD1# */
 448         irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW);  /* CARD0# */
 449         irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW);  /* CARD1# */
 450         irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
 451         irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
 452
 453         i2c_register_board_info(0, db1550_i2c_devs,
 454                                 ARRAY_SIZE(db1550_i2c_devs));
 455         spi_register_board_info(db1550_spi_devs,
 456                                 ARRAY_SIZE(db1550_i2c_devs));
 457
 458         /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */
 459         __raw_writel(PSC_SEL_CLK_SERCLK,
 460             (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
 461         wmb();
 462         __raw_writel(PSC_SEL_CLK_SERCLK,
 463             (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
 464         wmb();
 465         /* SPI/I2C use internally supplied 50MHz source */
 466         __raw_writel(PSC_SEL_CLK_INTCLK,
 467             (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET);
 468         wmb();
 469         __raw_writel(PSC_SEL_CLK_INTCLK,
 470             (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
 471         wmb();
 472
 473         db1x_register_pcmcia_socket(
 474                 AU1000_PCMCIA_ATTR_PHYS_ADDR,
 475                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
 476                 AU1000_PCMCIA_MEM_PHYS_ADDR,
 477                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
 478                 AU1000_PCMCIA_IO_PHYS_ADDR,
 479                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
 480                 AU1550_GPIO3_INT, AU1550_GPIO0_INT,
 481                 /*AU1550_GPIO21_INT*/0, 0, 0);
 482
 483         db1x_register_pcmcia_socket(
 484                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
 485                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
 486                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
 487                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
 488                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
 489                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
 490                 AU1550_GPIO5_INT, AU1550_GPIO1_INT,
 491                 /*AU1550_GPIO22_INT*/0, 0, 1);
 492
 493         swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
 494         db1x_register_norflash(128 << 20, 4, swapped);
 495
 496         return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs));
 497 }
 498 device_initcall(db1550_dev_init);