2 * USB block power/access management abstraction.
4 * Au1000+: The OHCI block control register is at the far end of the OHCI memory
5 * area. Au1550 has OHCI on different base address. No need to handle
7 * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG
8 * as well as the PHY for EHCI and UDC.
12 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/syscore_ops.h>
18 #include <asm/mach-au1x00/au1000.h>
20 /* control register offsets */
21 #define AU1000_OHCICFG 0x7fffc
22 #define AU1550_OHCICFG 0x07ffc
23 #define AU1200_USBCFG 0x04
25 /* Au1000 USB block config bits */
26 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
27 #define USBHEN_CE (1 << 3) /* OHCI block clock enable */
28 #define USBHEN_E (1 << 2) /* OHCI block enable */
29 #define USBHEN_C (1 << 1) /* OHCI block coherency bit */
30 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
32 /* Au1200 USB config bits */
33 #define USBCFG_PFEN (1 << 31) /* prefetch enable (undoc) */
34 #define USBCFG_RDCOMB (1 << 30) /* read combining (undoc) */
35 #define USBCFG_UNKNOWN (5 << 20) /* unknown, leave this way */
36 #define USBCFG_SSD (1 << 23) /* serial short detect en */
37 #define USBCFG_PPE (1 << 19) /* HS PHY PLL */
38 #define USBCFG_UCE (1 << 18) /* UDC clock enable */
39 #define USBCFG_ECE (1 << 17) /* EHCI clock enable */
40 #define USBCFG_OCE (1 << 16) /* OHCI clock enable */
41 #define USBCFG_FLA(x) (((x) & 0x3f) << 8)
42 #define USBCFG_UCAM (1 << 7) /* coherent access (undoc) */
43 #define USBCFG_GME (1 << 6) /* OTG mem access */
44 #define USBCFG_DBE (1 << 5) /* UDC busmaster enable */
45 #define USBCFG_DME (1 << 4) /* UDC mem enable */
46 #define USBCFG_EBE (1 << 3) /* EHCI busmaster enable */
47 #define USBCFG_EME (1 << 2) /* EHCI mem enable */
48 #define USBCFG_OBE (1 << 1) /* OHCI busmaster enable */
49 #define USBCFG_OME (1 << 0) /* OHCI mem enable */
50 #define USBCFG_INIT_AU1200 (USBCFG_PFEN | USBCFG_RDCOMB | USBCFG_UNKNOWN |\
51 USBCFG_SSD | USBCFG_FLA(0x20) | USBCFG_UCAM | \
52 USBCFG_GME | USBCFG_DBE | USBCFG_DME | \
53 USBCFG_EBE | USBCFG_EME | USBCFG_OBE | \
56 /* Au1300 USB config registers */
57 #define USB_DWC_CTRL1 0x00
58 #define USB_DWC_CTRL2 0x04
59 #define USB_VBUS_TIMER 0x10
60 #define USB_SBUS_CTRL 0x14
61 #define USB_MSR_ERR 0x18
62 #define USB_DWC_CTRL3 0x1C
63 #define USB_DWC_CTRL4 0x20
64 #define USB_OTG_STATUS 0x28
65 #define USB_DWC_CTRL5 0x2C
66 #define USB_DWC_CTRL6 0x30
67 #define USB_DWC_CTRL7 0x34
68 #define USB_PHY_STATUS 0xC0
69 #define USB_INT_STATUS 0xC4
70 #define USB_INT_ENABLE 0xC8
72 #define USB_DWC_CTRL1_OTGD 0x04 /* set to DISable OTG */
73 #define USB_DWC_CTRL1_HSTRS 0x02 /* set to ENable EHCI */
74 #define USB_DWC_CTRL1_DCRS 0x01 /* set to ENable UDC */
76 #define USB_DWC_CTRL2_PHY1RS 0x04 /* set to enable PHY1 */
77 #define USB_DWC_CTRL2_PHY0RS 0x02 /* set to enable PHY0 */
78 #define USB_DWC_CTRL2_PHYRS 0x01 /* set to enable PHY */
80 #define USB_DWC_CTRL3_OHCI1_CKEN (1 << 19)
81 #define USB_DWC_CTRL3_OHCI0_CKEN (1 << 18)
82 #define USB_DWC_CTRL3_EHCI0_CKEN (1 << 17)
83 #define USB_DWC_CTRL3_OTG0_CKEN (1 << 16)
85 #define USB_SBUS_CTRL_SBCA 0x04 /* coherent access */
87 #define USB_INTEN_FORCE 0x20
88 #define USB_INTEN_PHY 0x10
89 #define USB_INTEN_UDC 0x08
90 #define USB_INTEN_EHCI 0x04
91 #define USB_INTEN_OHCI1 0x02
92 #define USB_INTEN_OHCI0 0x01
94 static DEFINE_SPINLOCK(alchemy_usb_lock);
96 static inline void __au1300_usb_phyctl(void __iomem *base, int enable)
100 r = __raw_readl(base + USB_DWC_CTRL2);
101 s = __raw_readl(base + USB_DWC_CTRL3);
103 s &= USB_DWC_CTRL3_OHCI1_CKEN | USB_DWC_CTRL3_OHCI0_CKEN |
104 USB_DWC_CTRL3_EHCI0_CKEN | USB_DWC_CTRL3_OTG0_CKEN;
107 /* simply enable all PHYs */
108 r |= USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
110 __raw_writel(r, base + USB_DWC_CTRL2);
113 /* no USB block active, do disable all PHYs */
114 r &= ~(USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
115 USB_DWC_CTRL2_PHYRS);
116 __raw_writel(r, base + USB_DWC_CTRL2);
121 static inline void __au1300_ohci_control(void __iomem *base, int enable, int id)
126 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */
129 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */
130 r |= (id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
131 : USB_DWC_CTRL3_OHCI1_CKEN;
132 __raw_writel(r, base + USB_DWC_CTRL3);
135 __au1300_usb_phyctl(base, enable); /* power up the PHYs */
137 r = __raw_readl(base + USB_INT_ENABLE);
138 r |= (id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1;
139 __raw_writel(r, base + USB_INT_ENABLE);
142 /* reset the OHCI start clock bit */
143 __raw_writel(0, base + USB_DWC_CTRL7);
146 r = __raw_readl(base + USB_INT_ENABLE);
147 r &= ~((id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1);
148 __raw_writel(r, base + USB_INT_ENABLE);
151 r = __raw_readl(base + USB_DWC_CTRL3);
152 r &= ~((id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
153 : USB_DWC_CTRL3_OHCI1_CKEN);
154 __raw_writel(r, base + USB_DWC_CTRL3);
157 __au1300_usb_phyctl(base, enable);
161 static inline void __au1300_ehci_control(void __iomem *base, int enable)
166 r = __raw_readl(base + USB_DWC_CTRL3);
167 r |= USB_DWC_CTRL3_EHCI0_CKEN;
168 __raw_writel(r, base + USB_DWC_CTRL3);
171 r = __raw_readl(base + USB_DWC_CTRL1);
172 r |= USB_DWC_CTRL1_HSTRS;
173 __raw_writel(r, base + USB_DWC_CTRL1);
176 __au1300_usb_phyctl(base, enable);
178 r = __raw_readl(base + USB_INT_ENABLE);
180 __raw_writel(r, base + USB_INT_ENABLE);
183 r = __raw_readl(base + USB_INT_ENABLE);
184 r &= ~USB_INTEN_EHCI;
185 __raw_writel(r, base + USB_INT_ENABLE);
188 r = __raw_readl(base + USB_DWC_CTRL1);
189 r &= ~USB_DWC_CTRL1_HSTRS;
190 __raw_writel(r, base + USB_DWC_CTRL1);
193 r = __raw_readl(base + USB_DWC_CTRL3);
194 r &= ~USB_DWC_CTRL3_EHCI0_CKEN;
195 __raw_writel(r, base + USB_DWC_CTRL3);
198 __au1300_usb_phyctl(base, enable);
202 static inline void __au1300_udc_control(void __iomem *base, int enable)
207 r = __raw_readl(base + USB_DWC_CTRL1);
208 r |= USB_DWC_CTRL1_DCRS;
209 __raw_writel(r, base + USB_DWC_CTRL1);
212 __au1300_usb_phyctl(base, enable);
214 r = __raw_readl(base + USB_INT_ENABLE);
216 __raw_writel(r, base + USB_INT_ENABLE);
219 r = __raw_readl(base + USB_INT_ENABLE);
221 __raw_writel(r, base + USB_INT_ENABLE);
224 r = __raw_readl(base + USB_DWC_CTRL1);
225 r &= ~USB_DWC_CTRL1_DCRS;
226 __raw_writel(r, base + USB_DWC_CTRL1);
229 __au1300_usb_phyctl(base, enable);
233 static inline void __au1300_otg_control(void __iomem *base, int enable)
237 r = __raw_readl(base + USB_DWC_CTRL3);
238 r |= USB_DWC_CTRL3_OTG0_CKEN;
239 __raw_writel(r, base + USB_DWC_CTRL3);
242 r = __raw_readl(base + USB_DWC_CTRL1);
243 r &= ~USB_DWC_CTRL1_OTGD;
244 __raw_writel(r, base + USB_DWC_CTRL1);
247 __au1300_usb_phyctl(base, enable);
249 r = __raw_readl(base + USB_DWC_CTRL1);
250 r |= USB_DWC_CTRL1_OTGD;
251 __raw_writel(r, base + USB_DWC_CTRL1);
254 r = __raw_readl(base + USB_DWC_CTRL3);
255 r &= ~USB_DWC_CTRL3_OTG0_CKEN;
256 __raw_writel(r, base + USB_DWC_CTRL3);
259 __au1300_usb_phyctl(base, enable);
263 static inline int au1300_usb_control(int block, int enable)
266 (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
270 case ALCHEMY_USB_OHCI0:
271 __au1300_ohci_control(base, enable, 0);
273 case ALCHEMY_USB_OHCI1:
274 __au1300_ohci_control(base, enable, 1);
276 case ALCHEMY_USB_EHCI0:
277 __au1300_ehci_control(base, enable);
279 case ALCHEMY_USB_UDC0:
280 __au1300_udc_control(base, enable);
282 case ALCHEMY_USB_OTG0:
283 __au1300_otg_control(base, enable);
291 static inline void au1300_usb_init(void)
294 (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
296 /* set some sane defaults. Note: we don't fiddle with DWC_CTRL4
297 * here at all: Port 2 routing (EHCI or UDC) must be set either
298 * by boot firmware or platform init code; I can't autodetect
301 __raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */
303 __raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */
305 __raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */
307 __raw_writel(~0, base + USB_INT_STATUS); /* clear int status */
309 /* set coherent access bit */
310 __raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL);
314 static inline void __au1200_ohci_control(void __iomem *base, int enable)
316 unsigned long r = __raw_readl(base + AU1200_USBCFG);
318 __raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG);
322 __raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG);
328 static inline void __au1200_ehci_control(void __iomem *base, int enable)
330 unsigned long r = __raw_readl(base + AU1200_USBCFG);
332 __raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG);
336 if (!(r & USBCFG_UCE)) /* UDC also off? */
337 r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */
338 __raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG);
344 static inline void __au1200_udc_control(void __iomem *base, int enable)
346 unsigned long r = __raw_readl(base + AU1200_USBCFG);
348 __raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG);
351 if (!(r & USBCFG_ECE)) /* EHCI also off? */
352 r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */
353 __raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG);
358 static inline int au1200_usb_control(int block, int enable)
361 (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
364 case ALCHEMY_USB_OHCI0:
365 __au1200_ohci_control(base, enable);
367 case ALCHEMY_USB_UDC0:
368 __au1200_udc_control(base, enable);
370 case ALCHEMY_USB_EHCI0:
371 __au1200_ehci_control(base, enable);
380 /* initialize USB block(s) to a known working state */
381 static inline void au1200_usb_init(void)
384 (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
385 __raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG);
390 static inline void au1000_usb_init(unsigned long rb, int reg)
392 void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg);
393 unsigned long r = __raw_readl(base);
395 #if defined(__BIG_ENDIAN)
400 __raw_writel(r, base);
406 static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg)
408 void __iomem *base = (void __iomem *)KSEG1ADDR(rb);
409 unsigned long r = __raw_readl(base + creg);
412 __raw_writel(r | USBHEN_CE, base + creg);
415 __raw_writel(r | USBHEN_CE | USBHEN_E, base + creg);
419 /* wait for reset complete (read reg twice: au1500 erratum) */
420 while (__raw_readl(base + creg),
421 !(__raw_readl(base + creg) & USBHEN_RD))
424 __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);
429 static inline int au1000_usb_control(int block, int enable, unsigned long rb,
435 case ALCHEMY_USB_OHCI0:
436 __au1xx0_ohci_control(enable, rb, creg);
445 * alchemy_usb_control - control Alchemy on-chip USB blocks
446 * @block: USB block to target
447 * @enable: set 1 to enable a block, 0 to disable
449 int alchemy_usb_control(int block, int enable)
454 spin_lock_irqsave(&alchemy_usb_lock, flags);
455 switch (alchemy_get_cputype()) {
456 case ALCHEMY_CPU_AU1000:
457 case ALCHEMY_CPU_AU1500:
458 case ALCHEMY_CPU_AU1100:
459 ret = au1000_usb_control(block, enable,
460 AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
462 case ALCHEMY_CPU_AU1550:
463 ret = au1000_usb_control(block, enable,
464 AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
466 case ALCHEMY_CPU_AU1200:
467 ret = au1200_usb_control(block, enable);
469 case ALCHEMY_CPU_AU1300:
470 ret = au1300_usb_control(block, enable);
475 spin_unlock_irqrestore(&alchemy_usb_lock, flags);
478 EXPORT_SYMBOL_GPL(alchemy_usb_control);
481 static unsigned long alchemy_usb_pmdata[2];
483 static void au1000_usb_pm(unsigned long br, int creg, int susp)
485 void __iomem *base = (void __iomem *)KSEG1ADDR(br);
488 alchemy_usb_pmdata[0] = __raw_readl(base + creg);
489 /* There appears to be some undocumented reset register.... */
490 __raw_writel(0, base + 0x04);
492 __raw_writel(0, base + creg);
495 __raw_writel(alchemy_usb_pmdata[0], base + creg);
500 static void au1200_usb_pm(int susp)
503 (void __iomem *)KSEG1ADDR(AU1200_USB_OTG_PHYS_ADDR);
505 /* save OTG_CAP/MUX registers which indicate port routing */
506 /* FIXME: write an OTG driver to do that */
507 alchemy_usb_pmdata[0] = __raw_readl(base + 0x00);
508 alchemy_usb_pmdata[1] = __raw_readl(base + 0x04);
510 /* restore access to all MMIO areas */
513 /* restore OTG_CAP/MUX registers */
514 __raw_writel(alchemy_usb_pmdata[0], base + 0x00);
515 __raw_writel(alchemy_usb_pmdata[1], base + 0x04);
520 static void au1300_usb_pm(int susp)
523 (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
524 /* remember Port2 routing */
526 alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4);
529 __raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4);
534 static void alchemy_usb_pm(int susp)
536 switch (alchemy_get_cputype()) {
537 case ALCHEMY_CPU_AU1000:
538 case ALCHEMY_CPU_AU1500:
539 case ALCHEMY_CPU_AU1100:
540 au1000_usb_pm(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG, susp);
542 case ALCHEMY_CPU_AU1550:
543 au1000_usb_pm(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG, susp);
545 case ALCHEMY_CPU_AU1200:
548 case ALCHEMY_CPU_AU1300:
554 static int alchemy_usb_suspend(void)
560 static void alchemy_usb_resume(void)
565 static struct syscore_ops alchemy_usb_pm_ops = {
566 .suspend = alchemy_usb_suspend,
567 .resume = alchemy_usb_resume,
570 static int __init alchemy_usb_init(void)
572 switch (alchemy_get_cputype()) {
573 case ALCHEMY_CPU_AU1000:
574 case ALCHEMY_CPU_AU1500:
575 case ALCHEMY_CPU_AU1100:
576 au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
578 case ALCHEMY_CPU_AU1550:
579 au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
581 case ALCHEMY_CPU_AU1200:
584 case ALCHEMY_CPU_AU1300:
589 register_syscore_ops(&alchemy_usb_pm_ops);
593 arch_initcall(alchemy_usb_init);