2 * Exception handling for Microblaze
4 * Rewriten interrupt handling
6 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
7 * Copyright (C) 2008-2009 PetaLogix
9 * uClinux customisation (C) 2005 John Williams
11 * MMU code derived from arch/ppc/kernel/head_4xx.S:
12 * Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org>
13 * Initial PowerPC version.
14 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
16 * Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
17 * Low-level exception handers, MMU support, and rewrite.
18 * Copyright (C) 1997 Dan Malek <dmalek@jlc.net>
19 * PowerPC 8xx modifications.
20 * Copyright (C) 1998-1999 TiVo, Inc.
21 * PowerPC 403GCX modifications.
22 * Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu>
23 * PowerPC 403GCX/405GP modifications.
24 * Copyright 2000 MontaVista Software Inc.
25 * PPC405 modifications
26 * PowerPC 403GCX/405GP modifications.
27 * Author: MontaVista Software, Inc.
28 * frank_rowand@mvista.com or source@mvista.com
29 * debbie_chu@mvista.com
32 * Copyright (C) 2004 Xilinx, Inc.
34 * This program is free software; you can redistribute it and/or modify it
35 * under the terms of the GNU General Public License version 2 as published
36 * by the Free Software Foundation.
40 * Here are the handlers which don't require enabling translation
41 * and calling other kernel code thus we can keep their design very simple
42 * and do all processing in real mode. All what they need is a valid current
43 * (that is an issue for the CONFIG_REGISTER_TASK_PTR case)
44 * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore
45 * these registers are saved/restored
46 * The handlers which require translation are in entry.S --KAA
48 * Microblaze HW Exception Handler
49 * - Non self-modifying exception handler for the following exception conditions
51 * - Instruction bus error
53 * - Illegal instruction opcode
56 * - Privileged instruction exception (MMU)
57 * - Data storage exception (MMU)
58 * - Instruction storage exception (MMU)
59 * - Data TLB miss exception (MMU)
60 * - Instruction TLB miss exception (MMU)
62 * Note we disable interrupts during exception handling, otherwise we will
63 * possibly get multiple re-entrancy if interrupt handles themselves cause
67 #include <asm/exceptions.h>
68 #include <asm/unistd.h>
71 #include <asm/entry.h>
72 #include <asm/current.h>
73 #include <linux/linkage.h>
76 #include <asm/pgtable.h>
77 #include <asm/signal.h>
78 #include <asm/registers.h>
79 #include <asm/asm-offsets.h>
84 #define NUM_TO_REG(num) r ## num
87 #define RESTORE_STATE \
95 lwi r11, r1, PT_R11; \
96 lwi r31, r1, PT_R31; \
98 #endif /* CONFIG_MMU */
101 bri ex_handler_unhandled; \
105 bri ex_handler_unhandled; \
108 /* FIXME this is weird - for noMMU kernel is not possible to use brid
109 * instruction which can shorten executed time
112 /* r3 is the source */
113 #define R3_TO_LWREG_V(regnum) \
114 swi r3, r1, 4 * regnum; \
117 /* r3 is the source */
118 #define R3_TO_LWREG(regnum) \
119 or NUM_TO_REG (regnum), r0, r3; \
122 /* r3 is the target */
123 #define SWREG_TO_R3_V(regnum) \
124 lwi r3, r1, 4 * regnum; \
127 /* r3 is the target */
128 #define SWREG_TO_R3(regnum) \
129 or r3, r0, NUM_TO_REG (regnum); \
133 #define R3_TO_LWREG_VM_V(regnum) \
135 swi r3, r7, 4 * regnum;
137 #define R3_TO_LWREG_VM(regnum) \
139 or NUM_TO_REG (regnum), r0, r3;
141 #define SWREG_TO_R3_VM_V(regnum) \
142 brid ex_sw_tail_vm; \
143 lwi r3, r7, 4 * regnum;
145 #define SWREG_TO_R3_VM(regnum) \
146 brid ex_sw_tail_vm; \
147 or r3, r0, NUM_TO_REG (regnum);
149 /* Shift right instruction depending on available configuration */
150 #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0
151 #define BSRLI(rD, rA, imm) \
154 #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA)
155 /* Only the used shift constants defined here - add more if needed */
156 #define BSRLI2(rD, rA) \
157 srl rD, rA; /* << 1 */ \
158 srl rD, rD; /* << 2 */
159 #define BSRLI10(rD, rA) \
160 srl rD, rA; /* << 1 */ \
161 srl rD, rD; /* << 2 */ \
162 srl rD, rD; /* << 3 */ \
163 srl rD, rD; /* << 4 */ \
164 srl rD, rD; /* << 5 */ \
165 srl rD, rD; /* << 6 */ \
166 srl rD, rD; /* << 7 */ \
167 srl rD, rD; /* << 8 */ \
168 srl rD, rD; /* << 9 */ \
169 srl rD, rD /* << 10 */
170 #define BSRLI20(rD, rA) \
174 #endif /* CONFIG_MMU */
176 .extern other_exception_handler /* Defined in exception.c */
179 * hw_exception_handler - Handler for exceptions
181 * Exception handler notes:
182 * - Handles all exceptions
183 * - Does not handle unaligned exceptions during load into r17, r1, r0.
184 * - Does not handle unaligned exceptions during store from r17 (cannot be
185 * done) and r1 (slows down common case)
187 * Relevant register structures
189 * EAR - |----|----|----|----|----|----|----|----|
190 * - < ## 32 bit faulting address ## >
192 * ESR - |----|----|----|----|----| - | - |-----|-----|
196 * STACK FRAME STRUCTURE (for NO_MMU)
197 * ---------------------------------
199 * +-------------+ + 0
201 * +-------------+ + 4
208 * +-------------+ + 76
212 * MMU kernel uses the same 'pt_pool_space' pointed space
213 * which is used for storing register values - noMMu style was, that values were
214 * stored in stack but in case of failure you lost information about register.
215 * Currently you can see register value in memory in specific place.
216 * In compare to with previous solution the speed should be the same.
218 * MMU exception handler has different handling compare to no MMU kernel.
219 * Exception handler use jump table for directing of what happen. For MMU kernel
220 * is this approach better because MMU relate exception are handled by asm code
221 * in this file. In compare to with MMU expect of unaligned exception
222 * is everything handled by C code.
226 * every of these handlers is entered having R3/4/5/6/11/current saved on stack
227 * and clobbered so care should be taken to restore them if someone is going to
228 * return from exception
231 /* wrappers to restore state before coming to entry.S */
239 /* Create space for exception counting. */
241 .global exception_debug_table
243 exception_debug_table:
244 /* Look at exception vector table. There is 32 exceptions * word size */
250 _MB_HW_ExceptionVectorTable:
252 .long TOPHYS(ex_handler_unhandled)
253 /* 1 - Unaligned data access exception */
254 .long TOPHYS(handle_unaligned_ex)
255 /* 2 - Illegal op-code exception */
256 .long TOPHYS(full_exception_trapw)
257 /* 3 - Instruction bus error exception */
258 .long TOPHYS(full_exception_trapw)
259 /* 4 - Data bus error exception */
260 .long TOPHYS(full_exception_trapw)
261 /* 5 - Divide by zero exception */
262 .long TOPHYS(full_exception_trapw)
263 /* 6 - Floating point unit exception */
264 .long TOPHYS(full_exception_trapw)
265 /* 7 - Privileged instruction exception */
266 .long TOPHYS(full_exception_trapw)
267 /* 8 - 15 - Undefined */
268 .long TOPHYS(ex_handler_unhandled)
269 .long TOPHYS(ex_handler_unhandled)
270 .long TOPHYS(ex_handler_unhandled)
271 .long TOPHYS(ex_handler_unhandled)
272 .long TOPHYS(ex_handler_unhandled)
273 .long TOPHYS(ex_handler_unhandled)
274 .long TOPHYS(ex_handler_unhandled)
275 .long TOPHYS(ex_handler_unhandled)
276 /* 16 - Data storage exception */
277 .long TOPHYS(handle_data_storage_exception)
278 /* 17 - Instruction storage exception */
279 .long TOPHYS(handle_instruction_storage_exception)
280 /* 18 - Data TLB miss exception */
281 .long TOPHYS(handle_data_tlb_miss_exception)
282 /* 19 - Instruction TLB miss exception */
283 .long TOPHYS(handle_instruction_tlb_miss_exception)
284 /* 20 - 31 - Undefined */
285 .long TOPHYS(ex_handler_unhandled)
286 .long TOPHYS(ex_handler_unhandled)
287 .long TOPHYS(ex_handler_unhandled)
288 .long TOPHYS(ex_handler_unhandled)
289 .long TOPHYS(ex_handler_unhandled)
290 .long TOPHYS(ex_handler_unhandled)
291 .long TOPHYS(ex_handler_unhandled)
292 .long TOPHYS(ex_handler_unhandled)
293 .long TOPHYS(ex_handler_unhandled)
294 .long TOPHYS(ex_handler_unhandled)
295 .long TOPHYS(ex_handler_unhandled)
296 .long TOPHYS(ex_handler_unhandled)
299 .global _hw_exception_handler
302 .ent _hw_exception_handler
303 _hw_exception_handler:
305 addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
307 swi r1, r0, TOPHYS(pt_pool_space + PT_R1); /* GET_SP */
308 /* Save date to kernel memory. Here is the problem
309 * when you came from user space */
310 ori r1, r0, TOPHYS(pt_pool_space);
320 lwi r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */
332 andi r5, r4, 0x1000; /* Check ESR[DS] */
333 beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */
334 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
340 andi r5, r4, 0x1F; /* Extract ESR[EXC] */
343 /* Calculate exception vector offset = r5 << 2 */
344 addk r6, r5, r5; /* << 1 */
345 addk r6, r6, r6; /* << 2 */
348 /* counting which exception happen */
349 lwi r5, r0, TOPHYS(exception_debug_table)
351 swi r5, r0, TOPHYS(exception_debug_table)
352 lwi r5, r6, TOPHYS(exception_debug_table)
354 swi r5, r6, TOPHYS(exception_debug_table)
357 /* Load the HW Exception vector */
358 lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)
361 full_exception_trapw:
363 bri full_exception_trap
365 /* Exceptions enabled here. This will allow nested exceptions */
368 swi r6, r1, 0; /* RMSR_OFFSET */
369 ori r6, r6, 0x100; /* Turn ON the EE bit */
370 andi r6, r6, ~2; /* Disable interrupts */
374 xori r6, r5, 1; /* 00001 = Unaligned Exception */
375 /* Jump to unalignment exception handler */
376 beqi r6, handle_unaligned_ex;
378 handle_other_ex: /* Handle Other exceptions here */
379 /* Save other volatiles before we make procedure calls below */
391 andi r6, r4, 0x1F; /* Load ESR[EC] */
392 lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */
396 addk r8, r17, r0; /* Load exception address */
397 bralid r15, full_exception; /* Branch to the handler */
399 mts rfsr, r0; /* Clear sticky fsr */
403 * Trigger execution of the signal handler by enabling
404 * interrupts and calling an invalid syscall.
409 mts rmsr, r5; /* enable interrupt */
411 addi r12, r0, __NR_syscalls;
413 mfs r5, rmsr; /* disable interrupt */
429 bri ex_handler_done; /* Complete exception handling */
432 /* 0x01 - Unaligned data access exception
433 * This occurs when a word access is not aligned on a word boundary,
434 * or when a 16-bit access is not aligned on a 16-bit boundary.
435 * This handler perform the access, and returns, except for MMU when
436 * the unaligned address is last on a 4k page or the physical address is
437 * not found in the page table, in which case unaligned_data_trap is called.
440 /* Working registers already saved: R3, R4, R5, R6
445 andi r6, r4, 0x1000 /* Check ESR[DS] */
446 beqi r6, _no_delayslot /* Branch if ESR[DS] not set */
447 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
450 /* jump to high level unaligned handler */
452 bri unaligned_data_trap
454 andi r6, r4, 0x3E0; /* Mask and extract the register operand */
455 srl r6, r6; /* r6 >> 5 */
460 /* Store the register operand in a temporary location */
461 sbi r6, r0, TOPHYS(ex_reg_op);
463 andi r6, r4, 0x400; /* Extract ESR[S] */
466 andi r6, r4, 0x800; /* Extract ESR[W] */
468 lbui r5, r3, 0; /* Exception address in r3 */
469 /* Load a word, byte-by-byte from destination address
470 and save it in tmp space */
471 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
473 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
475 sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);
477 sbi r5, r0, TOPHYS(ex_tmp_data_loc_3);
478 /* Get the destination register value into r4 */
479 lwi r4, r0, TOPHYS(ex_tmp_data_loc_0);
482 lbui r5, r3, 0; /* Exception address in r3 */
483 /* Load a half-word, byte-by-byte from destination
484 address and save it in tmp space */
485 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
487 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
488 /* Get the destination register value into r4 */
489 lhui r4, r0, TOPHYS(ex_tmp_data_loc_0);
491 /* Get the destination register number into r5 */
492 lbui r5, r0, TOPHYS(ex_reg_op);
493 /* Form load_word jump table offset (lw_table + (8 * regnum)) */
494 addik r6, r0, TOPHYS(lw_table);
500 ex_lw_end: /* Exception handling of load word, ends */
502 /* Get the destination register number into r5 */
503 lbui r5, r0, TOPHYS(ex_reg_op);
504 /* Form store_word jump table offset (sw_table + (8 * regnum)) */
505 addik r6, r0, TOPHYS(sw_table);
514 andi r6, r6, 0x800; /* Extract ESR[W] */
516 /* Get the word - delay slot */
517 swi r4, r0, TOPHYS(ex_tmp_data_loc_0);
518 /* Store the word, byte-by-byte into destination address */
519 lbui r4, r0, TOPHYS(ex_tmp_data_loc_0);
521 lbui r4, r0, TOPHYS(ex_tmp_data_loc_1);
523 lbui r4, r0, TOPHYS(ex_tmp_data_loc_2);
525 lbui r4, r0, TOPHYS(ex_tmp_data_loc_3);
530 /* Store the lower half-word, byte-by-byte into destination address */
531 swi r4, r0, TOPHYS(ex_tmp_data_loc_0);
532 lbui r4, r0, TOPHYS(ex_tmp_data_loc_2);
534 lbui r4, r0, TOPHYS(ex_tmp_data_loc_3);
536 ex_sw_end: /* Exception handling of store word, ends. */
540 lwi r5, r1, 0 /* RMSR */
550 addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
558 /* Exception vector entry code. This code runs with address translation
559 * turned off (i.e. using physical addresses). */
561 /* Exception vectors. */
563 /* 0x10 - Data Storage Exception
564 * This happens for just a few reasons. U0 set (but we don't do that),
565 * or zone protection fault (user violation, write to protected page).
566 * If this is just an update of modified status, we do that quickly
567 * and exit. Otherwise, we call heavyweight functions to do the work.
569 handle_data_storage_exception:
570 /* Working registers already saved: R3, R4, R5, R6
575 /* If we are faulting a kernel address, we have to use the
576 * kernel page tables.
578 ori r5, r0, CONFIG_KERNEL_START
581 /* First, check if it was a zone fault (which means a user
582 * tried to access a kernel or read-protected page - always
583 * a SEGV). All other faults here must be stores, so no
584 * need to check ESR_S as well. */
585 andi r4, r4, ESR_DIZ /* ESR_Z - zone protection */
588 ori r4, r0, swapper_pg_dir
589 mts rpid, r0 /* TLB will have 0 TID */
593 /* Get the PGD for the current thread. */
595 /* First, check if it was a zone fault (which means a user
596 * tried to access a kernel or read-protected page - always
597 * a SEGV). All other faults here must be stores, so no
598 * need to check ESR_S as well. */
599 andi r4, r4, ESR_DIZ /* ESR_Z */
601 /* get current task address */
602 addi r4 ,CURRENT_TASK, TOPHYS(0);
603 lwi r4, r4, TASK_THREAD+PGDIR
606 /* Create L1 (pgdir/pmd) address */
607 BSRLI(r5,r3, PGDIR_SHIFT - 2)
608 andi r5, r5, PAGE_SIZE - 4
609 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
611 lwi r4, r4, 0 /* Get L1 entry */
612 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
613 beqi r5, ex2 /* Bail if no table */
616 BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
617 andi r6, r6, PAGE_SIZE - 4
618 andi r5, r5, PAGE_MASK + 0x3
620 lwi r4, r5, 0 /* Get Linux PTE */
622 andi r6, r4, _PAGE_RW /* Is it writeable? */
623 beqi r6, ex2 /* Bail if not */
625 /* Update 'changed' */
626 ori r4, r4, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
627 swi r4, r5, 0 /* Update Linux page table */
629 /* Most of the Linux PTE is ready to load into the TLB LO.
630 * We set ZSEL, where only the LS-bit determines user access.
631 * We set execute, because we don't have the granularity to
632 * properly set this at the page level (Linux problem).
633 * If shared is set, we cause a zero PID->TID load.
634 * Many of these bits are software only. Bits we don't set
635 * here we (properly should) assume have the appropriate value.
637 /* Ignore memory coherent, just LSB on ZSEL is used + EX/WR */
638 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
639 TLB_ZSEL(1) | TLB_ATTR_MASK
640 ori r4, r4, _PAGE_HWEXEC /* make it executable */
642 /* find the TLB index that caused the fault. It has to be here*/
645 mfs r5, rtlbx /* DEBUG: TBD */
647 mts rtlblo, r4 /* Load TLB LO */
649 /* Will sync shadow TLBs */
651 /* Done...restore registers and get out of here. */
660 /* The bailout. Restore registers to pre-exception conditions
661 * and call the heavyweights to help us out. */
666 bri page_fault_data_trap
669 /* 0x11 - Instruction Storage Exception
670 * This is caused by a fetch from non-execute or guarded pages. */
671 handle_instruction_storage_exception:
672 /* Working registers already saved: R3, R4, R5, R6
677 bri page_fault_instr_trap
679 /* 0x12 - Data TLB Miss Exception
680 * As the name implies, translation is not in the MMU, so search the
681 * page tables and fix it. The only purpose of this function is to
682 * load TLB entries from the page table if they exist.
684 handle_data_tlb_miss_exception:
685 /* Working registers already saved: R3, R4, R5, R6
691 /* If we are faulting a kernel address, we have to use the
692 * kernel page tables. */
693 ori r6, r0, CONFIG_KERNEL_START
696 ori r4, r0, swapper_pg_dir
697 mts rpid, r0 /* TLB will have 0 TID */
701 /* Get the PGD for the current thread. */
703 /* get current task address */
704 addi r4 ,CURRENT_TASK, TOPHYS(0);
705 lwi r4, r4, TASK_THREAD+PGDIR
708 /* Create L1 (pgdir/pmd) address */
709 BSRLI(r5,r3, PGDIR_SHIFT - 2)
710 andi r5, r5, PAGE_SIZE - 4
711 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
713 lwi r4, r4, 0 /* Get L1 entry */
714 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
715 beqi r5, ex7 /* Bail if no table */
718 BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
719 andi r6, r6, PAGE_SIZE - 4
720 andi r5, r5, PAGE_MASK + 0x3
722 lwi r4, r5, 0 /* Get Linux PTE */
724 andi r6, r4, _PAGE_PRESENT
727 ori r4, r4, _PAGE_ACCESSED
730 /* Most of the Linux PTE is ready to load into the TLB LO.
731 * We set ZSEL, where only the LS-bit determines user access.
732 * We set execute, because we don't have the granularity to
733 * properly set this at the page level (Linux problem).
734 * If shared is set, we cause a zero PID->TID load.
735 * Many of these bits are software only. Bits we don't set
736 * here we (properly should) assume have the appropriate value.
739 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
740 TLB_ZSEL(1) | TLB_ATTR_MASK
742 /* The bailout. Restore registers to pre-exception conditions
743 * and call the heavyweights to help us out.
749 bri page_fault_data_trap
751 /* 0x13 - Instruction TLB Miss Exception
752 * Nearly the same as above, except we get our information from
753 * different registers and bailout to a different point.
755 handle_instruction_tlb_miss_exception:
756 /* Working registers already saved: R3, R4, R5, R6
762 /* If we are faulting a kernel address, we have to use the
763 * kernel page tables.
765 ori r4, r0, CONFIG_KERNEL_START
768 ori r4, r0, swapper_pg_dir
769 mts rpid, r0 /* TLB will have 0 TID */
773 /* Get the PGD for the current thread. */
775 /* get current task address */
776 addi r4 ,CURRENT_TASK, TOPHYS(0);
777 lwi r4, r4, TASK_THREAD+PGDIR
780 /* Create L1 (pgdir/pmd) address */
781 BSRLI(r5,r3, PGDIR_SHIFT - 2)
782 andi r5, r5, PAGE_SIZE - 4
783 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
785 lwi r4, r4, 0 /* Get L1 entry */
786 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
787 beqi r5, ex10 /* Bail if no table */
790 BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
791 andi r6, r6, PAGE_SIZE - 4
792 andi r5, r5, PAGE_MASK + 0x3
794 lwi r4, r5, 0 /* Get Linux PTE */
796 andi r6, r4, _PAGE_PRESENT
799 ori r4, r4, _PAGE_ACCESSED
802 /* Most of the Linux PTE is ready to load into the TLB LO.
803 * We set ZSEL, where only the LS-bit determines user access.
804 * We set execute, because we don't have the granularity to
805 * properly set this at the page level (Linux problem).
806 * If shared is set, we cause a zero PID->TID load.
807 * Many of these bits are software only. Bits we don't set
808 * here we (properly should) assume have the appropriate value.
811 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
812 TLB_ZSEL(1) | TLB_ATTR_MASK
814 /* The bailout. Restore registers to pre-exception conditions
815 * and call the heavyweights to help us out.
821 bri page_fault_instr_trap
823 /* Both the instruction and data TLB miss get to this point to load the TLB.
825 * r4 - TLB LO (info from Linux PTE)
826 * r5, r6 - available to use
827 * PID - loaded with proper value when we get here
828 * Upon exit, we reload everything and RFI.
829 * A common place to load the TLB.
835 .long MICROBLAZE_TLB_SKIP
837 /* MS: storing last used tlb index */
838 .long MICROBLAZE_TLB_SIZE/2
841 /* MS: load the last used TLB index. */
842 lwi r5, r0, TOPHYS(tlb_index)
843 addik r5, r5, 1 /* MS: inc tlb_index -> use next one */
845 /* MS: FIXME this is potential fault, because this is mask not count */
846 andi r5, r5, MICROBLAZE_TLB_SIZE - 1
850 lwi r5, r0, TOPHYS(tlb_skip)
852 /* MS: save back current TLB index */
853 swi r5, r0, TOPHYS(tlb_index)
855 ori r4, r4, _PAGE_HWEXEC /* make it executable */
856 mts rtlbx, r5 /* MS: save current TLB */
858 mts rtlblo, r4 /* MS: save to TLB LO */
861 /* Create EPN. This is the faulting address plus a static
862 * set of bits. These are size, valid, E, U0, and ensure
863 * bits 20 and 21 are zero.
865 andi r3, r3, PAGE_MASK
866 #ifdef CONFIG_MICROBLAZE_64K_PAGES
867 ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_64K)
868 #elif CONFIG_MICROBLAZE_16K_PAGES
869 ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_16K)
871 ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_4K)
873 mts rtlbhi, r3 /* Load TLB HI */
876 /* Done...restore registers and get out of here. */
884 /* extern void giveup_fpu(struct task_struct *prev)
886 * The MicroBlaze processor may have an FPU, so this should not just
892 bralid r15,0 /* TBD */
895 /* At present, this routine just hangs. - extern void abort(void) */
904 mts rpid, r5 /* Shadow TLBs are automatically */
906 bri 4 /* flushed by changing PID */
911 .end _hw_exception_handler
914 /* Unaligned data access exception last on a 4k page for MMU.
915 * When this is called, we are in virtual mode with exceptions enabled
916 * and registers 1-13,15,17,18 saved.
920 * R7 = pointer to saved registers (struct pt_regs *regs)
922 * This handler perform the access, and returns via ret_from_exc.
924 .global _unaligned_data_exception
925 .ent _unaligned_data_exception
926 _unaligned_data_exception:
927 andi r8, r3, 0x3E0; /* Mask and extract the register operand */
928 BSRLI(r8,r8,2); /* r8 >> 2 = register operand * 8 */
929 andi r6, r3, 0x400; /* Extract ESR[S] */
931 andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */
934 load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */
935 /* Load a word, byte-by-byte from destination address and save it in tmp space*/
936 addik r6, r0, ex_tmp_data_loc_0;
938 load2: lbui r5, r4, 1;
940 load3: lbui r5, r4, 2;
942 load4: lbui r5, r4, 3;
945 /* Get the destination register value into r3 - delay slot */
948 /* Load a half-word, byte-by-byte from destination address and
949 * save it in tmp space */
950 addik r6, r0, ex_tmp_data_loc_0;
952 load5: lbui r5, r4, 1;
954 lhui r3, r6, 0; /* Get the destination register value into r3 */
956 /* Form load_word jump table offset (lw_table_vm + (8 * regnum)) */
957 addik r5, r8, lw_table_vm;
959 ex_lw_end_vm: /* Exception handling of load word, ends */
962 /* Form store_word jump table offset (sw_table_vm + (8 * regnum)) */
963 addik r5, r8, sw_table_vm;
966 addik r5, r0, ex_tmp_data_loc_0;
968 swi r3, r5, 0; /* Get the word - delay slot */
969 /* Store the word, byte-by-byte into destination address */
971 store1: sbi r3, r4, 0;
973 store2: sbi r3, r4, 1;
975 store3: sbi r3, r4, 2;
978 store4: sbi r3, r4, 3; /* Delay slot */
980 /* Store the lower half-word, byte-by-byte into destination address */
981 #ifdef __MICROBLAZEEL__
983 store5: sbi r3, r4, 0;
986 store6: sbi r3, r4, 1; /* Delay slot */
989 store5: sbi r3, r4, 0;
992 store6: sbi r3, r4, 1; /* Delay slot */
995 ex_sw_end_vm: /* Exception handling of store word, ends. */
997 /* We have to prevent cases that get/put_user macros get unaligned pointer
998 * to bad page area. We have to find out which origin instruction caused it
999 * and called fixup for that origin instruction not instruction in unaligned
1002 ori r5, r7, 0 /* setup pointer to pt_regs */
1003 lwi r6, r7, PT_PC; /* faulting address is one instruction above */
1004 addik r6, r6, -4 /* for finding proper fixup */
1005 swi r6, r7, PT_PC; /* a save back it to PT_PC */
1006 addik r7, r0, SIGSEGV
1007 /* call bad_page_fault for finding aligned fixup, fixup address is saved
1008 * in PT_PC which is used as return address from exception */
1009 addik r15, r0, ret_from_exc-8 /* setup return address */
1013 /* We prevent all load/store because it could failed any attempt to access */
1014 .section __ex_table,"a";
1015 .word load1,ex_unaligned_fixup;
1016 .word load2,ex_unaligned_fixup;
1017 .word load3,ex_unaligned_fixup;
1018 .word load4,ex_unaligned_fixup;
1019 .word load5,ex_unaligned_fixup;
1020 .word store1,ex_unaligned_fixup;
1021 .word store2,ex_unaligned_fixup;
1022 .word store3,ex_unaligned_fixup;
1023 .word store4,ex_unaligned_fixup;
1024 .word store5,ex_unaligned_fixup;
1025 .word store6,ex_unaligned_fixup;
1027 .end _unaligned_data_exception
1028 #endif /* CONFIG_MMU */
1030 .global ex_handler_unhandled
1031 ex_handler_unhandled:
1032 /* FIXME add handle function for unhandled exception - dump register */
1036 * hw_exception_handler Jump Table
1037 * - Contains code snippets for each register that caused the unalign exception
1038 * - Hence exception handler is NOT self-modifying
1039 * - Separate table for load exceptions and store exceptions.
1040 * - Each table is of size: (8 * 32) = 256 bytes
1046 lw_r0: R3_TO_LWREG (0);
1048 lw_r2: R3_TO_LWREG (2);
1049 lw_r3: R3_TO_LWREG_V (3);
1050 lw_r4: R3_TO_LWREG_V (4);
1051 lw_r5: R3_TO_LWREG_V (5);
1052 lw_r6: R3_TO_LWREG_V (6);
1053 lw_r7: R3_TO_LWREG (7);
1054 lw_r8: R3_TO_LWREG (8);
1055 lw_r9: R3_TO_LWREG (9);
1056 lw_r10: R3_TO_LWREG (10);
1057 lw_r11: R3_TO_LWREG (11);
1058 lw_r12: R3_TO_LWREG (12);
1059 lw_r13: R3_TO_LWREG (13);
1060 lw_r14: R3_TO_LWREG (14);
1061 lw_r15: R3_TO_LWREG (15);
1062 lw_r16: R3_TO_LWREG (16);
1064 lw_r18: R3_TO_LWREG (18);
1065 lw_r19: R3_TO_LWREG (19);
1066 lw_r20: R3_TO_LWREG (20);
1067 lw_r21: R3_TO_LWREG (21);
1068 lw_r22: R3_TO_LWREG (22);
1069 lw_r23: R3_TO_LWREG (23);
1070 lw_r24: R3_TO_LWREG (24);
1071 lw_r25: R3_TO_LWREG (25);
1072 lw_r26: R3_TO_LWREG (26);
1073 lw_r27: R3_TO_LWREG (27);
1074 lw_r28: R3_TO_LWREG (28);
1075 lw_r29: R3_TO_LWREG (29);
1076 lw_r30: R3_TO_LWREG (30);
1078 lw_r31: R3_TO_LWREG_V (31);
1080 lw_r31: R3_TO_LWREG (31);
1084 sw_r0: SWREG_TO_R3 (0);
1086 sw_r2: SWREG_TO_R3 (2);
1087 sw_r3: SWREG_TO_R3_V (3);
1088 sw_r4: SWREG_TO_R3_V (4);
1089 sw_r5: SWREG_TO_R3_V (5);
1090 sw_r6: SWREG_TO_R3_V (6);
1091 sw_r7: SWREG_TO_R3 (7);
1092 sw_r8: SWREG_TO_R3 (8);
1093 sw_r9: SWREG_TO_R3 (9);
1094 sw_r10: SWREG_TO_R3 (10);
1095 sw_r11: SWREG_TO_R3 (11);
1096 sw_r12: SWREG_TO_R3 (12);
1097 sw_r13: SWREG_TO_R3 (13);
1098 sw_r14: SWREG_TO_R3 (14);
1099 sw_r15: SWREG_TO_R3 (15);
1100 sw_r16: SWREG_TO_R3 (16);
1102 sw_r18: SWREG_TO_R3 (18);
1103 sw_r19: SWREG_TO_R3 (19);
1104 sw_r20: SWREG_TO_R3 (20);
1105 sw_r21: SWREG_TO_R3 (21);
1106 sw_r22: SWREG_TO_R3 (22);
1107 sw_r23: SWREG_TO_R3 (23);
1108 sw_r24: SWREG_TO_R3 (24);
1109 sw_r25: SWREG_TO_R3 (25);
1110 sw_r26: SWREG_TO_R3 (26);
1111 sw_r27: SWREG_TO_R3 (27);
1112 sw_r28: SWREG_TO_R3 (28);
1113 sw_r29: SWREG_TO_R3 (29);
1114 sw_r30: SWREG_TO_R3 (30);
1116 sw_r31: SWREG_TO_R3_V (31);
1118 sw_r31: SWREG_TO_R3 (31);
1123 lw_r0_vm: R3_TO_LWREG_VM (0);
1124 lw_r1_vm: R3_TO_LWREG_VM_V (1);
1125 lw_r2_vm: R3_TO_LWREG_VM_V (2);
1126 lw_r3_vm: R3_TO_LWREG_VM_V (3);
1127 lw_r4_vm: R3_TO_LWREG_VM_V (4);
1128 lw_r5_vm: R3_TO_LWREG_VM_V (5);
1129 lw_r6_vm: R3_TO_LWREG_VM_V (6);
1130 lw_r7_vm: R3_TO_LWREG_VM_V (7);
1131 lw_r8_vm: R3_TO_LWREG_VM_V (8);
1132 lw_r9_vm: R3_TO_LWREG_VM_V (9);
1133 lw_r10_vm: R3_TO_LWREG_VM_V (10);
1134 lw_r11_vm: R3_TO_LWREG_VM_V (11);
1135 lw_r12_vm: R3_TO_LWREG_VM_V (12);
1136 lw_r13_vm: R3_TO_LWREG_VM_V (13);
1137 lw_r14_vm: R3_TO_LWREG_VM_V (14);
1138 lw_r15_vm: R3_TO_LWREG_VM_V (15);
1139 lw_r16_vm: R3_TO_LWREG_VM_V (16);
1140 lw_r17_vm: R3_TO_LWREG_VM_V (17);
1141 lw_r18_vm: R3_TO_LWREG_VM_V (18);
1142 lw_r19_vm: R3_TO_LWREG_VM_V (19);
1143 lw_r20_vm: R3_TO_LWREG_VM_V (20);
1144 lw_r21_vm: R3_TO_LWREG_VM_V (21);
1145 lw_r22_vm: R3_TO_LWREG_VM_V (22);
1146 lw_r23_vm: R3_TO_LWREG_VM_V (23);
1147 lw_r24_vm: R3_TO_LWREG_VM_V (24);
1148 lw_r25_vm: R3_TO_LWREG_VM_V (25);
1149 lw_r26_vm: R3_TO_LWREG_VM_V (26);
1150 lw_r27_vm: R3_TO_LWREG_VM_V (27);
1151 lw_r28_vm: R3_TO_LWREG_VM_V (28);
1152 lw_r29_vm: R3_TO_LWREG_VM_V (29);
1153 lw_r30_vm: R3_TO_LWREG_VM_V (30);
1154 lw_r31_vm: R3_TO_LWREG_VM_V (31);
1157 sw_r0_vm: SWREG_TO_R3_VM (0);
1158 sw_r1_vm: SWREG_TO_R3_VM_V (1);
1159 sw_r2_vm: SWREG_TO_R3_VM_V (2);
1160 sw_r3_vm: SWREG_TO_R3_VM_V (3);
1161 sw_r4_vm: SWREG_TO_R3_VM_V (4);
1162 sw_r5_vm: SWREG_TO_R3_VM_V (5);
1163 sw_r6_vm: SWREG_TO_R3_VM_V (6);
1164 sw_r7_vm: SWREG_TO_R3_VM_V (7);
1165 sw_r8_vm: SWREG_TO_R3_VM_V (8);
1166 sw_r9_vm: SWREG_TO_R3_VM_V (9);
1167 sw_r10_vm: SWREG_TO_R3_VM_V (10);
1168 sw_r11_vm: SWREG_TO_R3_VM_V (11);
1169 sw_r12_vm: SWREG_TO_R3_VM_V (12);
1170 sw_r13_vm: SWREG_TO_R3_VM_V (13);
1171 sw_r14_vm: SWREG_TO_R3_VM_V (14);
1172 sw_r15_vm: SWREG_TO_R3_VM_V (15);
1173 sw_r16_vm: SWREG_TO_R3_VM_V (16);
1174 sw_r17_vm: SWREG_TO_R3_VM_V (17);
1175 sw_r18_vm: SWREG_TO_R3_VM_V (18);
1176 sw_r19_vm: SWREG_TO_R3_VM_V (19);
1177 sw_r20_vm: SWREG_TO_R3_VM_V (20);
1178 sw_r21_vm: SWREG_TO_R3_VM_V (21);
1179 sw_r22_vm: SWREG_TO_R3_VM_V (22);
1180 sw_r23_vm: SWREG_TO_R3_VM_V (23);
1181 sw_r24_vm: SWREG_TO_R3_VM_V (24);
1182 sw_r25_vm: SWREG_TO_R3_VM_V (25);
1183 sw_r26_vm: SWREG_TO_R3_VM_V (26);
1184 sw_r27_vm: SWREG_TO_R3_VM_V (27);
1185 sw_r28_vm: SWREG_TO_R3_VM_V (28);
1186 sw_r29_vm: SWREG_TO_R3_VM_V (29);
1187 sw_r30_vm: SWREG_TO_R3_VM_V (30);
1188 sw_r31_vm: SWREG_TO_R3_VM_V (31);
1189 #endif /* CONFIG_MMU */
1191 /* Temporary data structures used in the handler */